Semiconductor device

Abstract

A semiconductor device is provided. The semiconductor device includes a substrate including a cell region, a core region, and a boundary region between the cell region and the core region; a boundary element isolation layer in the boundary region of the substrate to separate the cell region from the core region; a high dielectric constant dielectric layer on at least a portion of the boundary element isolation layer and the core region of the substrate; a first work function metal pattern including a first extension overlapping the boundary element isolation layer, the first work function metal pattern on the high dielectric constant dielectric layer; and a second work function metal pattern including a second extension overlapping the boundary element isolation layer, the second work function metal pattern on the first work function metal pattern, wherein a first length that the first extension extends in a direction from the core region toward the cell region is different from a second length that the second extension extends in the direction from the core region toward the cell region.

Description

[0001] This application is a divisional application of the application for "Semiconductor Device" filed on February 7, 2018, with application number 201810127428.0. TECHNICAL FIELD

[0002] The present inventive concept relates to a semiconductor device and / or a method of fabricating the same. BACKGROUND

[0003] A semiconductor memory element (e.g., a dynamic random access memory (DRAM)) has a cell region and a core region. Specifically, the core region includes a region in which a p-type metal oxide semiconductor (PMOS) transistor is formed and a region in which an n-type metal oxide semiconductor (NMOS) transistor is formed. Recently, a structure in which a p-type gate is provided in the region in which the PMOS transistor is formed and an n-type gate is provided in the region in which the NMOS transistor is formed is used.

[0004] In addition, as the integration of the semiconductor memory element increases, a leakage current through a gate dielectric layer of a transistor increases. Therefore, the gate dielectric layer is formed using a high dielectric material (a high dielectric constant dielectric material). SUMMARY

[0005] One aspect of the present inventive concept provides a semiconductor device having improved integration and reliability.

[0006] Another aspect provides a method of fabricating a semiconductor device having improved integration and reliability.

[0007] The technical problems of the present inventive concept are not limited to the above-mentioned technical problems, and another technical problem not mentioned will be clearly understood by those skilled in the art from the following description.

[0008] According to some example embodiments of the inventive concept, there is provided a semiconductor device comprising: a substrate comprising a cell region, a core region, and a border region between the cell region and the core region; a border element isolation layer in the substrate in the border region separating the cell region from the core region; a high dielectric constant dielectric layer on the substrate at least part of the border element isolation layer and the core region; a first work function metal pattern comprising a first extension overlapping the border element isolation layer, the first work function metal pattern being on the high dielectric constant dielectric layer; and a second work function metal pattern comprising a second extension overlapping the border element isolation layer, the second work function metal pattern being on the first work function metal pattern, wherein the first extension differs from the second extension in a first length extending in a direction from the core region towards the cell region.

[0009] According to some example embodiments of the inventive concept, there is provided a semiconductor device comprising: a substrate comprising a cell region, a core region, and a border region between the cell region and the core region; a border element isolation layer in the substrate in the border region separating the cell region from the core region; a high dielectric constant dielectric layer on the substrate at least part of the border element isolation layer and the core region; a first work function metal pattern comprising a first extension overlapping the border element isolation layer and being on the substrate; and a second work function metal pattern comprising a second extension overlapping the border element isolation layer, the second work function metal pattern being on the first work function metal pattern, wherein the border element isolation layer comprises a recess, the recess not overlapping the first extension and the second extension and being adjacent to at least one of the first extension and the second extension.

[0010] According to some example embodiments of the inventive concept, there is provided a semiconductor device comprising: a cell region in a substrate; an element isolation layer around the cell region; a high dielectric constant dielectric layer extending from a direction opposite a direction of the cell region onto a part of the element isolation layer; a first work function metal pattern extending a first length from the direction opposite the direction of the cell region onto the element isolation layer; and a second work function metal pattern extending a second length from the direction opposite the direction of the cell region onto the element isolation layer. At least a part of the second work function metal pattern is on the first work function metal pattern. The first work function metal pattern is on the high dielectric constant dielectric layer. The second length differs from the first length. BRIEF DESCRIPTION OF DRAWINGS

[0011] The above and other aspects and features of the present invention will become more apparent from the detailed description of some exemplary embodiments of the present invention with reference to the accompanying drawings, in which:

[0012] Figure 1 This is a layout diagram illustrating some exemplary embodiments of a semiconductor device according to the concept of the present invention.

[0013] Figure 2 yes Figure 1 An enlarged view of region R shown.

[0014] Figure 3 It is along Figure 1 The sectional views are taken along lines A-A', B-B', and C-C'.

[0015] Figure 4a yes Figure 3 An enlarged view of region D shown.

[0016] Figure 4b This is a diagram illustrating the boundary region of a semiconductor device according to some exemplary embodiments of the present invention.

[0017] Figure 4c This is a diagram illustrating the boundary region of a semiconductor device according to some exemplary embodiments of the present invention.

[0018] Figures 5 to 16 This is a diagram illustrating intermediate steps of a method for fabricating a semiconductor device according to some exemplary embodiments of the present invention.

[0019] [Explanation of Symbols]

[0020] 100: Substrate

[0021] 110: Component isolation layer

[0022] 110a: Boundary element isolation layer

[0023] 110r: Depression

[0024] 120: Line pattern

[0025] 122: Buried insulation layer

[0026] 124: Buried conductive layer

[0027] 126: Buried dielectric layer

[0028] 130: Gate insulating layer

[0029] 140: High dielectric constant dielectric layer

[0030] 140a, 140b, 140c: Third extension

[0031] 150: first work function metal layer

[0032] 150': first work function metal pattern

[0033] 150a, 150b, 150c: first extensions

[0034] 160: second work function metal layer

[0035] 160': second work function metal pattern

[0036] 160a, 160b, 160c: second extensions

[0037] 202: first insulating layer

[0038] 204: second insulating layer

[0039] 210: direct contact pattern

[0040] 220: bit line pattern

[0041] 222: first conductive layer

[0042] 224: second conductive layer

[0043] 226: third conductive layer

[0044] 230: top cap layer

[0045] 240: gate spacer

[0046] 300: first photoresist

[0047] 310: second photoresist

[0048] A-A', B-B', C-C': lines

[0049] AR: active region

[0050] BL: bit line

[0051] D, R: regions

[0052] DC: direct contact

[0053] I: first region

[0054] II: second region

[0055] L1: first length

[0056] L2: second length

[0057] L1a, L1b, L1c: first lengths

[0058] L2a, L2b, L2c: second lengths

[0059] L3a, L3b, L3c: third length

[0060] WL: word line

[0061] X: first direction

[0062] Y: second direction

[0063] Z: third direction DETAILED DESCRIPTION

[0064] Hereinafter, a semiconductor device according to some exemplary embodiments of the inventive concepts will be described with reference to the accompanying drawings. Figures 1 to 4a A semiconductor device according to some exemplary embodiments of the inventive concepts will be described.

[0065] Figure 1 is a layout showing a semiconductor device according to some exemplary embodiments of the inventive concepts. Figure 2 is Figure 1 is an enlarged view of a region R shown in Figure 3 is a sectional view taken along lines A-A', B-B', and C-C' shown in Figure 1 Figure 4a is Figure 3 is an enlarged view of a region D shown in

[0066] Referring to Figure 1 , a semiconductor device according to some exemplary embodiments of the inventive concepts includes a cell region, a core region, and a boundary region.

[0067] In the cell region, semiconductor cells can be provided to form an array. For example, when the semiconductor device to be formed is a semiconductor memory device, semiconductor memory cells can be provided in the cell region to form an array.

[0068] The core region can be provided around the cell region or can be provided in another region different from the cell region. In the core region, some control elements and dummy elements can be formed. Thus, in the core region, a circuit required for controlling the semiconductor cells formed in the cell region can be provided.

[0069] The boundary region can be provided between the cell region and the core region. Specifically, the boundary region can be provided adjacent to the cell region and the core region and between the cell region and the core region. For example, as shown in Figure 1 , the boundary region can be provided between the cell region and the core region provided around the cell region. Thus, the boundary region can surround the cell region.

[0070] In the boundary region, a boundary element isolation layer (110a) shown in Figure 3 may be provided. Thus, the boundary region can separate the cell region from the core region.

[0071] Referring to Figure 2 ​In the cell region, an active region AR, a word line WL, a bit line BL, and a direct contact DC can be provided.

[0072] The active region AR can be defined by an element isolation layer (110) as shown. Figure 3

[0073] As the design rule of a semiconductor device decreases, the active region AR can be provided in a form of a diagonal bar. Specifically, the active region AR can be provided in a form of a bar extending in an arbitrary direction other than a first direction X and a second direction Y in a plane extending in the first direction X and the second direction Y.

[0074] In addition, the active region AR can be in a form of a plurality of bars extending in directions parallel to each other. At this time, a center of one of the plurality of active regions AR can be provided adjacent to a distal end of another active region AR.

[0075] Impurities can be implanted into the active region AR to form a source region and a drain region. The implantation of impurities into the active region AR can be performed in an ion implantation process, but exemplary embodiments of the present disclosure are not limited thereto.

[0076] The word line WL can extend across the active region AR in the first direction X. A plurality of word lines WL can extend parallel to each other and can be spaced apart from each other by equal intervals. For example, the plurality of word lines WL can be buried in a substrate (100) to extend parallel to each other and can be spaced apart from each other by equal intervals. Figure 3

[0077] The bit line BL can extend across the active region AR and the word line WL in a second direction Y different from the first direction X. For example, the second direction Y can be a direction orthogonal to the first direction X. Accordingly, the bit line BL can extend diagonally across the active region AR and can extend perpendicularly across the word line WL.

[0078] A plurality of bit lines BL can extend parallel to each other and can be spaced apart from each other by equal intervals. For example, the plurality of bit lines BL can extend parallel to each other and can be spaced apart from each other by equal intervals on a substrate (100). Figure 3

[0079] The direct contact DC can be provided at a center of the active region AR. In addition, the direct contact DC can be electrically connected to the bit line BL. Accordingly, the center of the active region AR can be electrically connected to the bit line BL.

[0080] Referring to Figure 3 ​​​A semiconductor device according to some exemplary embodiments of the inventive concept includes a substrate 100, a device isolation layer 110, a word line pattern 120, a first insulating layer 202 and a second insulating layer 204, a bit line pattern 220, a direct contact pattern 210, a cap layer 230, a gate insulating layer 130, a high dielectric constant dielectric layer 140, a first work function metal pattern 150' and a second work function metal pattern 160', and a gate spacer 240.

[0081] The substrate 100 can have a structure in which a base substrate and an epitaxial layer are laminated, but the present disclosure is not limited thereto. The substrate 100 can be a silicon substrate, a gallium arsenide substrate, a silicon germanium substrate, a ceramic substrate, a quartz substrate, a display glass substrate, or the like, and can be a semiconductor on insulator (SOI) substrate. As an example, the substrate 100 can be a silicon substrate.

[0082] The substrate 100 includes a cell region, a core region, and a boundary region. At this time, the core region can include a first region I and a second region II. As shown in the drawing, the first region I and the second region II can be disposed to be spaced apart from each other, but exemplary embodiments of the present disclosure are not limited thereto, and the first region I and the second region II can be disposed to be adjacent to each other.

[0083] In some exemplary embodiments, conductive transistors different from each other can be formed in the first region I and the second region II. For example, PMOS transistors can be formed in the first region I, and NMOS transistors can be formed in the second region II. In this case, the substrate 100 of the first region I can be doped with an n-type impurity, and the substrate 100 of the second region II can be doped with a p-type impurity.

[0084] The device isolation layer 110 can define an active region (not shown) disposed on a top of the substrate 100. Figure 2 The device isolation layer 110 can include silicon oxide, silicon nitride, or a combination thereof, but exemplary embodiments of the present disclosure are not limited thereto. The device isolation layer 110 can be a single layer made of one insulating material or can be a plurality of layers made of a combination of several insulating materials.

[0085] The device isolation layer 110 can include a boundary device isolation layer 110a disposed in the boundary region. That is, the boundary device isolation layer 110a can be disposed in the substrate 100 of the boundary region. Accordingly, the boundary device isolation layer 110a can separate the cell region from the core region. That is, the boundary region can be defined by the boundary device isolation layer 110a.

[0086] The boundary device isolation layer 110a can include a recess 110r on an upper surface of the boundary device isolation layer 110a. Thereafter, in the recess 110r, a gate spacer 240 can be formed.Figure 4a This will be explained in detail in the description.

[0087] The word line pattern 120 can be disposed on the substrate 100 of the cell region. The word line pattern 120 may include a buried dielectric layer 126, a buried conductive layer 124, and a buried insulating layer 122. The word line pattern 120 may correspond to... Figure 2 The character line WL is shown. That is, the character line pattern 120 can extend in the first direction X. For example, as... Figure 3 As shown, the character line pattern 120 can be buried in the substrate 100 of the cell region to extend in the first direction X.

[0088] Specifically, word line trenches extending in the first direction X can be formed on the substrate 100. The lower surface of the word line trenches can be higher than the lower surface of the device isolation layer 110. A buried dielectric layer 126 can be disposed along the word line trenches. Furthermore, a buried conductive layer 124 and a buried insulating layer 122 can be sequentially stacked on the buried dielectric layer 126. Therefore, the buried dielectric layer 126, the buried conductive layer 124, and the buried insulating layer 122 can fill the word line trenches to form a word line pattern 120. At this time, the buried conductive layer 124 is electrically insulated from the substrate 100 through the buried dielectric layer 126.

[0089] As shown in the figure, the word line pattern 120 may be disposed on the component isolation layer 110. However, this disclosure is not limited thereto, and the word line pattern 120 may not be disposed on the component isolation layer 110.

[0090] The first insulating layer 202 and the second insulating layer 204 may be disposed on the substrate 100 and the component isolation layer 110. Specifically, the first insulating layer 202 and the second insulating layer 204 may be disposed on the substrate 100, the component isolation layer 110 and the word line pattern 120 of the cell area.

[0091] The first insulating layer 202 and the second insulating layer 204 may contain different materials. For example, the first insulating layer 202 may contain silicon oxide, while the second insulating layer 204 may contain silicon nitride. However, the exemplary embodiments of this disclosure are not limited thereto, and the first insulating layer 202 and the second insulating layer 204 may be formed from a single layer containing the same material. Alternatively, each of the first insulating layer 202 and the second insulating layer 204 may be formed from multiple layers.

[0092] Bit line pattern 220 may be disposed on substrate 100. Bit line pattern 220 may correspond to Figure 2 The bit line BL is shown. That is, the bit line pattern 220 can extend in the second direction Y on the substrate 100 of the cell region. Specifically, the bit line pattern 220 can be disposed on the first insulating layer 202 and the second insulating layer 204.

[0093] The bit line pattern 220 can be a single layer, but can also be a plurality of layers including a first conductive layer 222, a second conductive layer 224, and a third conductive layer 226, as shown in the drawing. That is, the bit line pattern 220 can be formed by sequentially disposing the first conductive layer 222, the second conductive layer 224, and the third conductive layer 226 on the first insulating layer 202 and the second insulating layer 204.

[0094] Each of the first conductive layer 222, the second conductive layer 224, and the third conductive layer 226 can include polysilicon, TiN, TiSiN, tungsten, tungsten silicide, or a combination thereof. For example, the first conductive layer 222 can contain polysilicon, the second conductive layer 224 can contain TiSiN, and the third conductive layer 226 can contain tungsten. However, exemplary embodiments of the present disclosure are not limited thereto.

[0095] The direct contact pattern 210 can be disposed on the substrate 100 of the cell region through the first insulating layer 202 and the second insulating layer 204. The direct contact pattern 210 can correspond to Figure 2 The direct contact pattern 210 is shown as a direct contact DC. That is, the direct contact pattern 210 is disposed on the substrate 100 and can be electrically connected with the bit line pattern 220. Accordingly, the substrate 100 disposed under the direct contact pattern 210 can be electrically connected with the bit line pattern 220.

[0096] A cap layer 230 can be disposed on the bit line pattern 220. That is, the cap layer 230 can extend in the second direction Y on the bit line pattern 220 of the cell region.

[0097] The cap layer 230 can contain silicon nitride, but exemplary embodiments of the present disclosure are not limited thereto.

[0098] The gate insulating layer 130 can be disposed on the substrate 100 of the core region. Specifically, the gate insulating layer 130 can be disposed on the substrate 100 of the core region adjacent to the boundary region. In addition, the gate insulating layer 130 can be partially disposed on the substrate 100 of the first region I and can be partially disposed on the substrate 100 of the second region II. However, exemplary embodiments of the present disclosure are not limited thereto, and the gate insulating layer 130 can be disposed on the element isolation layer 110 of the core region. In addition, the gate insulating layer 130 disposed on the substrate 100 of the core region adjacent to the boundary region can further extend in the second direction Y and can be disposed on the boundary element isolation layer 110a.

[0099] The gate insulating layer 130 disposed on the substrate 100 of the first region I and the substrate 100 of the second region II can extend in the first direction X. However, exemplary embodiments of the present disclosure are not limited thereto, and the gate insulating layer 130 can extend in various directions. For example, the gate insulating layer 130 can also extend in the second direction Y.

[0100] In addition, the gate insulating layer 130 located in the first region I and the gate insulating layer 130 located in the second region II can extend in different directions from each other. For example, the gate insulating layer 130 disposed on the substrate 100 in the first region I can extend in a first direction X, and the gate insulating layer 130 disposed on the substrate 100 in the second region II can extend in a second direction Y.

[0101] The gate insulating layer 130 can include silicon nitride, but exemplary embodiments of the present disclosure are not limited thereto.

[0102] The high dielectric constant dielectric layer 140 can be disposed on the substrate 100 of the border region and the substrate 100 of the core region. Specifically, the high dielectric constant dielectric layer 140 can be disposed on at least a portion of the border element isolation layer 110a located in the border region. In addition, the high dielectric constant dielectric layer 140 can be disposed on the gate insulating layer 130 located in the core region.

[0103] The high dielectric constant dielectric layer 140 can include silicon oxide, silicon nitride, silicon oxynitride ONO (oxide / nitride / oxide), or a high dielectric constant dielectric material having a higher dielectric constant than silicon oxide.

[0104] For example, the high dielectric constant dielectric layer 140 can include hafnium oxide (HfO), hafnium silicate (HfSiO), hafnium oxynitride (HfON), hafnium silicon oxynitride (HfSiON), lanthanum oxide (LaO), lanthanum aluminum oxide (LaAlO), zirconium oxide (ZrO), zirconium silicate (ZrSiO), zirconium oxynitride (ZrON), zirconium silicon oxynitride (ZrSiON), tantalum oxide (TaO), titanium oxide (TiO), barium strontium titanium oxide (BaSrTiO), barium titanium oxide (BaTiO), strontium titanium oxide (SrTiO), yttrium oxide (YO), aluminum oxide (AlO), lead scandium tantalum oxide (PbScTaO), or a combination thereof. However, exemplary embodiments of the present disclosure are not limited thereto.

[0105] Although not shown in the drawings, an interface layer can be further interposed between the gate insulating layer 130 and the high dielectric constant dielectric layer 140. The interface layer can prevent the existence of a defective interface between the gate insulating layer 130 and the high dielectric constant dielectric layer 140.

[0106] The first work function metal pattern 150' can be disposed on the substrate 100 of the border region and the substrate 100 of the core region. Specifically, the first work function metal pattern 150' can be disposed on the border element isolation layer 110a or the high dielectric constant dielectric layer 140 in the border region. In addition, the first work function metal pattern 150' can be disposed on the high dielectric constant dielectric layer 140 in the first region I.

[0107] However, the first work function metal pattern 150' can not be disposed in the second region II. That is, the first work function metal pattern 150' can be disposed on the high dielectric constant dielectric layer 140 of the first region I and can not be disposed on the substrate 100 of the second region II.

[0108] In some exemplary embodiments, the first region I can be a region in which a PMOS transistor is formed. That is, the substrate 100 of the first region I can be doped with an n-type impurity. That is, the first work function metal pattern 150' disposed on the high dielectric constant dielectric layer 140 of the first region I can be a metal layer for adjusting a threshold voltage of a PMOS transistor.

[0109] For example, the first work function metal pattern 150' can be formed of tungsten (W), tantalum (Ta), aluminum (Al), ruthenium (Ru), platinum (Pt), titanium nitride (TiN), tantalum nitride (TaN), titanium carbide (TiC), tantalum carbide (TaC), or a combination thereof, but exemplary embodiments of the present disclosure are not limited thereto.

[0110] In addition, the first work function metal pattern 150' can be formed of a multi-layer structure in which a plurality of thin metal layers are stacked. For example, the first work function metal pattern 150' can be formed of Al2O3 / TiN, Al2O3 / TaN, Al / TiN, Al / TaN, TiN / Al / TiN, TaN / Al / TaN, TiN / TiON, TaN / TiON, Ta / TiN, TaN / TiN, or a combination thereof.

[0111] The second work function metal pattern 160' can be disposed on the substrate 100 of the boundary region and the substrate 100 of the core region. Specifically, the second work function metal pattern 160' can be disposed on the boundary element isolation layer 110a, the first work function metal pattern 150', or the high dielectric constant dielectric layer 140 in the boundary region. In addition, the second work function metal pattern 160' can be disposed on the high dielectric constant dielectric layer 140 in the core region.

[0112] More specifically, the second work function metal pattern 160' can be disposed on the first work function metal pattern 150' in the first region I. In addition, the second work function metal pattern 160' can be disposed on the high dielectric constant dielectric layer 140 in the second region II. That is, the second work function metal pattern 160' can be disposed on the first work function metal pattern 150' of the first region I and can be disposed on the high dielectric constant dielectric layer 140 of the second region II.

[0113] In some example embodiments, the second region II can be a region in which an NMOS transistor is formed. That is, the substrate 100 of the second region II can be doped with a p-type impurity. That is, the second work function metal pattern 160' disposed on the high dielectric constant dielectric layer 140 of the second region II can be a metal layer for adjusting a threshold voltage of an NMOS transistor.

[0114] For example, the second work function metal pattern 160' can contain lanthanum (La), tantalum (Ta), tantalum nitride (TaN), niobium (Nb), titanium nitride (TiN), or a combination thereof. However, example embodiments of the present disclosure are not limited thereto.

[0115] In addition, the second work function metal pattern 160' can also be formed of a multi-layer structure in which a plurality of thin metal layers are stacked. For example, the second work function metal pattern 160' can be selected from TiN / TiON, Mg / TiN, TiN / Mg / TiN, La / TiN, TiN / La / TiN, Sr / TiN, TiN / Sr / TiN, or a combination thereof.

[0116] A first conductive layer 222, a second conductive layer 224, and a third conductive layer 226 can be disposed on the second work function metal pattern 160'. That is, the first conductive layer 222, the second conductive layer 224, and the third conductive layer 226 for forming a bit line pattern 220 in a cell region can also be disposed in a core region.

[0117] Specifically, the first conductive layer 222, the second conductive layer 224, and the third conductive layer 226 are sequentially stacked on the second work function metal pattern 160' in the first region I and on the second work function metal pattern 160' in the second region II. In addition, the first conductive layer 222, the second conductive layer 224, and the third conductive layer 226 can be stacked on the second work function metal pattern 160' in a border region. In some example embodiments, the first conductive layer 222, the second conductive layer 224, and the third conductive layer 226 can completely cover the second work function metal pattern 160'.

[0118] A cap layer 230 can be disposed on the first conductive layer 222, the second conductive layer 224, and the third conductive layer 226. That is, the cap layer 230 disposed on the bit line pattern 220 in a cell region can also be disposed in a core region.

[0119] A gate spacer 240 can be disposed on sidewalls of the gate insulating layer 130, sidewalls of the high dielectric constant dielectric layer 140, and sidewalls of the first work function metal pattern 150' and the second work function metal pattern 160'.

[0120] Specifically, the gate spacers 240 can be disposed on the sidewalls of the gate insulating layer 130, the sidewalls of the high dielectric constant dielectric layer 140, the sidewalls of the first work function metal pattern 150', the sidewalls of the second work function metal pattern 160', the sidewalls of the first conductive layer 222, the sidewalls of the second conductive layer 224, the sidewalls of the third conductive layer 226, and the sidewalls of the capping layer 230 in the first region I.

[0121] In addition, the gate spacers 240 can be disposed on the sidewalls of the gate insulating layer 130, the sidewalls of the high dielectric constant dielectric layer 140, the sidewalls of the second work function metal pattern 160', the sidewalls of the first conductive layer 222, the sidewalls of the second conductive layer 224, the sidewalls of the third conductive layer 226, and the sidewalls of the capping layer 230 in the second region II.

[0122] Hereinafter, the boundary region of the semiconductor device according to some exemplary embodiments of the inventive concept will be specifically described with reference to Figure 3 and Figure 4a The boundary region of the semiconductor device according to some exemplary embodiments of the inventive concept will be specifically described.

[0123] As described above, the high dielectric constant dielectric layer 140, the first work function metal pattern 150', and the second work function metal pattern 160' can be disposed on the substrate 100 of the boundary region and the substrate 100 of the core region.

[0124] Specifically, the high dielectric constant dielectric layer 140, the first work function metal pattern 150', and the second work function metal pattern 160' disposed on the substrate 100 of the core region can extend in a direction toward the cell region, and can be disposed on the boundary region. That is, a portion of the high dielectric constant dielectric layer 140, a portion of the first work function metal pattern 150', and a portion of the second work function metal pattern 160' can be disposed on the boundary element isolation layer 110a.

[0125] At this time, the portion of the first work function metal pattern 150' overlapping the boundary element isolation layer 110a can be defined as a first extension 150a. Here, the expression "the first work function metal pattern 150' overlaps the boundary element isolation layer 110a" means that the first work function metal pattern 150' includes a portion overlapping the boundary element isolation layer 110a in a third direction Z intersecting the first direction X and the second direction Y.

[0126] Similarly, a portion of the second work function metal pattern 160' overlapping the boundary element isolation layer 110a can be defined as a second extension 160a, and a portion of the high dielectric constant dielectric layer 140 overlapping the boundary element isolation layer 110a can be defined as a third extension 140a. That is, the first extension 150a, the second extension 160a, and the third extension 140a overlap the first work function metal pattern 150', the second work function metal pattern 160', and the high dielectric constant dielectric layer 140, respectively, in the third direction Z.

[0127] In addition, the first extension 150a, the second extension 160a, and the third extension 140a can extend in a direction from the core region toward the cell region, respectively. For example, the first extension 150a, the second extension 160a, and the third extension 140a can extend in the second direction Y.

[0128] In some exemplary embodiments, a first length L1a by which the first extension 150a extends in the second direction Y can be shorter than a second length L2a by which the second extension 160a extends in the second direction Y. That is, the length by which the first extension 150a extends in a direction from an end of the boundary region adjacent to the core region toward the cell region can be shorter than the length by which the second extension 160a extends in the direction from the end of the boundary region adjacent to the core region toward the cell region.

[0129] In addition, a third length L3a by which the third extension 140a extends in the second direction Y can be substantially the same as the second length L2a. Accordingly, a region of the second extension 160a corresponding to the first length L1a can be disposed on the first extension 150a. In addition, a region of the second extension 160a corresponding to a difference between the first length L1a and the second length L2a can be disposed on the third extension 140a.

[0130] The recess 110r formed on the upper surface of the boundary element isolation layer 110a does not overlap the first extension 150a and the second extension 160a and can be adjacent to at least one of the first extension 150a and the second extension 160a.

[0131] As shown in the drawing, when the first length L1a is shorter than the second length L2a, the recess 110r can be adjacent to the second extension 160a. In addition, as shown in the drawing, if the third length L3a is substantially the same as the second length L2a, the recess 110r can be adjacent to the second extension 160a and the third extension 140a. At this time, the recess 110r can not overlap the first extension 150a and the second extension 160a.

[0132] Hereinafter, a detailed description will be given of the first extension 150a, the second extension 160a, and the third extension 140a, with reference to Figure 4bA boundary region of a semiconductor device according to some exemplary embodiments of the present inventive concepts will be described below. For convenience of explanation, portions duplicated with the description of Figures 1 to 4a will be briefly explained or omitted.

[0133] Figure 4b is a diagram illustrating a boundary region of a semiconductor device according to some exemplary embodiments of the present inventive concepts.

[0134] Figure 4b is a region corresponding to Figure 4a . That is, a semiconductor device including the boundary region illustrated in Figure 4b may be the same as a semiconductor device according to Figure 3 except for the region D.

[0135] In some exemplary embodiments, a first length L1b at which the first extension 150b extends in the second direction Y can be longer than a second length L2b at which the second extension 160b extends in the second direction Y. That is, a length at which the first extension 150b extends in a direction from an end of the boundary region adjacent to the core region toward the cell region can be longer than a length at which the second extension 160b extends in the direction from the end of the boundary region adjacent to the core region toward the cell region. Accordingly, a region of the second extension 160b corresponding to the second length L2b can be disposed on the first extension 150b.

[0136] In addition, a third length L3b at which the third extension 140b extends in the second direction Y can be substantially the same as the first length L1b.

[0137] As illustrated in the drawing, when the first length L1b is longer than the second length L2b, the recessed portion 110r can be adjacent to the first extension 150b. In addition, as illustrated in the drawing, if the third length L3b is substantially the same as the first length L1b, the recessed portion 110r can be adjacent to the first extension 150b and the third extension 140b. At this time, the recessed portion 110r can not overlap the first extension 150b and the second extension 160b.

[0138] A boundary region of a semiconductor device according to some exemplary embodiments of the present inventive concepts will be described below. For convenience of explanation, portions duplicated with the description of Figure 4c will be briefly explained or omitted. Figures 1 to 4a

[0139] Figure 4c is a diagram illustrating a boundary region of a semiconductor device according to some exemplary embodiments of the present inventive concepts.

[0140] Figure 4c is a region corresponding to Figure 4a . That is, a semiconductor device including the boundary region according to Figure 4c may be the same as a semiconductor device according to​Figure 3 The semiconductor device according to the present application concept is the same as the semiconductor device of FIG. 1, except for the region D.

[0141] In some exemplary embodiments, a first length Llc at which the first extension 150c extends in the second direction Y can be substantially the same as a second length L2c at which the second extension 160c extends in the second direction Y. That is, a length at which the first extension 150c extends in a direction from an end of the boundary region adjacent to the core region toward the cell region can be substantially the same as a length at which the second extension 160c extends in a direction from an end of the boundary region adjacent to the core region toward the cell region. Accordingly, a region of the second extension 160c corresponding to the first length Llc and the second length L2c can be provided on the first extension 150c.

[0142] In addition, a third length L3c at which the third extension 140c extends in the second direction Y can be substantially the same as the first length Llc and the second length L2c.

[0143] As shown in the drawing, when the first length Llc is substantially the same as the second length L2c, the recess 110r can be adjacent to the first extension 150c and the second extension 160c. In addition, as shown in the drawing, if the third length L3c is substantially the same as the first length Llc and the second length L2c, the recess 110r can be adjacent to the first extension 150c, the second extension 160c, and the third extension 140c. At this time, the recess 110r can not overlap the first extension 150c and the second extension 160c.

[0144] Accordingly, in the semiconductor device according to some exemplary embodiments of the present application concept, a semiconductor device having improved integration and reliability can be provided while forming a high dielectric constant dielectric layer only in the core region.

[0145] The high dielectric constant dielectric layer 140 is not provided on the substrate 100 of the cell region, and can be provided on the substrate 100 of the core region. That is, the high dielectric constant dielectric layer 140 can be provided only in the core region without changing the structure of the bit line BL of the cell region. Accordingly, a high performance transistor driven at low power can be provided in the core region.

[0146] In addition, the gate insulating layer 130, the high dielectric constant dielectric layer 140, and the first work function metal pattern 150' and the second work function metal pattern 160' disposed in the core region can extend to a portion of the border region. That is, the gate insulating layer 130, the high dielectric constant dielectric layer 140, the first work function metal pattern 150', and the second work function metal pattern 160' can also be disposed on the substrate 100 of the border region adjacent to the core region. Accordingly, the substrate 100 of the border region adjacent to the core region can also function as a transistor. That is, the area of the core region can be minimized, and the integration of the semiconductor memory element can be improved.

[0147] In addition, the recess 110r formed on the border element isolation layer 110a can prevent a short circuit between the cell region and the core region. That is, by forming the recess 110r on the border element isolation layer 110a, the first work function metal pattern 150' or the second work function metal pattern 160' can be prevented from extending to the cell region. Accordingly, the reliability of the semiconductor memory element can be improved.

[0148] Hereinafter, a method of fabricating a semiconductor device according to some exemplary embodiments of the inventive concept will be described with reference to Figures 5 to 16 A method of fabricating a semiconductor device according to some exemplary embodiments of the inventive concept will be described. For the convenience of explanation, portions overlapping the description of Figures 1 to 4c will be briefly explained or omitted.

[0149] Figures 5 to 16 is an intermediate step diagram for explaining a method of fabricating a semiconductor device according to some exemplary embodiments of the inventive concept.

[0150] Referring to Figure 5 , an element isolation layer 110 and a word line pattern 120 are disposed on a substrate 100.

[0151] Specifically, the element isolation layer 110 can be formed on the substrate 100 of the cell region, the substrate 100 of the core region, and the substrate 100 of the border region. At this time, the border element isolation layer 110a can be formed on the substrate 100 of the border region.

[0152] Next, a word line trench can be formed on the substrate 100 of the cell region. A buried dielectric layer 126, a buried conductive layer 124, and a buried insulating layer 122 can be sequentially buried in the formed word line trench to form the word line pattern 120. At this time, although the word line pattern 120 can be formed on the element isolation layer 110, exemplary embodiments of the disclosure are not limited thereto, and the word line pattern 120 can not be formed on the element isolation layer 110.

[0153] Referring to Figure 6 , a first insulating layer 202 and a second insulating layer 204 are formed on the substrate 100 of the cell region.

[0154] Specifically, a first insulating layer 202 and a second insulating layer 204 are sequentially formed on the substrate 100, the element isolation layer 110, and the word line pattern 120 in the cell region.

[0155] Although the first insulating layer 202 can be formed of an oxide layer and the second insulating layer 204 can be formed of a nitride layer, exemplary embodiments of the present disclosure are not limited thereto.

[0156] Referring to Figure 7 A gate insulating layer 130 is formed on the substrate 100 in the core region.

[0157] For example, the gate insulating layer 130 can be formed by oxidation of the substrate 100. Thus, the gate insulating layer 130 can include an oxide of the substrate 100. In addition, the gate insulating layer 130 can be formed on the substrate 100 in the core region and can not be formed on the element isolation layer 110.

[0158] However, exemplary embodiments of the present disclosure are not limited thereto, and the gate insulating layer 130 can be formed on the substrate 100 and the element isolation layer 110 in the core region by another process, such as atomic layer deposition (ALD). In addition, the gate insulating layer 130 can be formed on the boundary element isolation layer 110a.

[0159] Referring to Figure 8 A high dielectric constant dielectric layer 140 is formed on the resulting structure of Figure 7

[0160] For example, the high dielectric constant dielectric layer 140 can be formed on the substrate 100 by a process such as chemical vapor deposition (CVD) or atomic layer deposition (ALD).

[0161] Thus, the high dielectric constant dielectric layer 140 can be conformally formed on the resulting structure of Figure 7 That is, the high dielectric constant dielectric layer 140 can be formed on the first insulating layer 202 and the second insulating layer 204 in the cell region, can be formed on the boundary element isolation layer 110a in the boundary region, and can be formed on the gate insulating layer 130 in the core region.

[0162] Referring to Figure 9 A first work function metal layer 150 is formed on the high dielectric constant dielectric layer 140. The first work function metal layer 150 can be conformally formed on the high dielectric constant dielectric layer 140.

[0163] ​For example, the first work function metal layer 150 can be formed of tungsten (W), tantalum (Ta), aluminum (Al), ruthenium (Ru), platinum (Pt), titanium nitride (TiN), tantalum nitride (TaN), titanium carbide (TiC), tantalum carbide (TaC), or a combination thereof.

[0164] In addition, the first work function metal layer 150 can be formed of a multi-layer structure by stacking a plurality of thin metal layers. For example, the first work function metal layer 150 can be formed of Al2O3 / TiN, Al2O3 / TaN, Al / TiN, Al / TaN, TiN / Al / TiN, TaN / Al / TaN, TiN / TiON, TaN / TiON, Ta / TiN, TaN / TiN, or a combination thereof.

[0165] Referring to Figure 10 A first photoresist 300 is formed on the first work function metal layer 150.

[0166] Specifically, the first photoresist 300 can be formed to overlap at least a portion of the boundary element isolation layer 110a and the first region I. In addition, the first photoresist 300 can be formed not to overlap the second region II.

[0167] At this time, the first photoresist 300 can be formed to overlap the boundary element isolation layer 110a by a first length L1. That is, the first photoresist 300 can extend in a direction from an end of the boundary region adjacent to the core region toward the cell region by the first length L1.

[0168] Referring to Figure 11 The first work function metal layer 150 is patterned using the first photoresist 300 as an etching mask. Accordingly, the first work function metal layer 150 can be patterned to form a first work function metal pattern 150'.

[0169] Specifically, the first work function metal pattern 150' can be formed by performing a photolithography process. That is, the first work function metal layer 150 not overlapping the first photoresist 300 is removed, and the remaining first work function metal layer 150 can form the first work function metal pattern 150'.

[0170] Accordingly, the first work function metal pattern 150' can extend in a direction from an end of the boundary region adjacent to the core region toward the cell region by the first length L1.

[0171] After the first work function metal pattern 150' is formed, the first photoresist 300 can be removed.

[0172] In some example embodiments, the high dielectric constant dielectric layer 140 can be used as an etching stopper layer. Accordingly, when the first work function metal layer 150 is patterned, the high dielectric constant dielectric layer 140 can not be patterned.

[0173] Referring to Figure 12 , a second work function metal layer 160 is formed on the resulting structure of Figure 11 The second work function metal layer 160 can be conformally formed on the resulting structure of Figure 11 .

[0174] For example, the second work function metal layer 160 can be formed of lanthanum (La), tantalum (Ta), tantalum nitride (TaN), niobium (Nb), titanium nitride (TiN), or a combination thereof.

[0175] In addition, the second work function metal layer 160 can be formed of a multi-layer structure by stacking a plurality of thin metal layers. For example, the second work function metal layer 160 can be formed of TiN / TiON, Mg / TiN, TiN / Mg / TiN, La / TiN, TiN / La / TiN, Sr / TiN, TiN / Sr / TiN, or a combination thereof.

[0176] Referring to Figure 13 , a second photoresist 310 is formed on the second work function metal layer 160.

[0177] Specifically, the second photoresist 310 can be formed to overlap at least a portion of the boundary element isolation layer 110a and the first region I and the second region II.

[0178] At this time, the second photoresist 310 can be formed to overlap the boundary element isolation layer 110a by a second length L2. That is, the second photoresist 310 can extend in a direction from an end of the boundary region adjacent to the core region toward the cell region by the second length L2.

[0179] In some example embodiments, the second length L2 can be formed to be different from the first length L1. That is, forming the second photoresist 310 can include forming a length of the second photoresist 310 overlapping the boundary element isolation layer 110a, which is different from a length of the first photoresist 300 overlapping the boundary element isolation layer 110a.

[0180] For example, when the second length L2 is formed to be longer than the first length L1, the second photoresist 310 can completely cover the first work function metal pattern 150'.

[0181] Referring to Figure 14 , the second work function metal layer 160 is patterned using the second photoresist 310 as an etching mask. Accordingly, the second work function metal layer 160 can be patterned to form a second work function metal pattern 160'.

[0182] Specifically, the second active power metal pattern 160' can be formed by performing a photolithography process. That is, the second active power metal layer 160 that does not overlap with the second photoresist 310 is removed, and the remaining second active power metal layer 160 can form the second active power metal pattern 160'.

[0183] Therefore, the second work function metal pattern 160' can extend a second length L2 from the end of the boundary region adjacent to the core region toward the unit region.

[0184] After the second work function metal pattern 160' is formed, the second photoresist 310 can be removed.

[0185] In some exemplary embodiments, the second photoresist 310 can be used as an etching mask to simultaneously pattern the second active power metal layer 160 and the high dielectric constant dielectric layer 140. That is, the patterning of the second active power metal layer 160 may include using the second photoresist 310 as an etching mask to pattern the high dielectric constant dielectric layer 140.

[0186] For example, when the second length L2 is formed to be longer than the first length L1, the second work function metal pattern 160' and the high dielectric constant dielectric layer 140 can extend the second length L2 in the direction from the end of the boundary region adjacent to the core region toward the cell region.

[0187] At this time, a portion of the upper part of the boundary element isolation layer 110a can be etched to form a recess 110r. Specifically, the second active power metal layer 160 and the high dielectric constant dielectric layer 140 exposed by the second photoresist 310 can be patterned to expose a portion of the upper part of the boundary element isolation layer 110a. Therefore, a portion of the exposed upper part of the boundary element isolation layer 110a can be etched to form the recess 110r.

[0188] For example, when the second length L2 is formed to be longer than the first length L1, the recess 110r can be formed to be adjacent to the second work function metal layer 160 and the high dielectric constant dielectric layer 140.

[0189] Reference Figure 15 A direct contact pattern 210 is formed on the substrate 100 of the unit region. Then, a first conductive layer 222, a second conductive layer 224, a third conductive layer 226, and a top cover layer 230 are sequentially stacked on the substrate 100.

[0190] Specifically, direct contact trenches can be formed through the first insulating layer 202 and the second insulating layer 204 to expose a portion of the substrate 100 of the cell region. The direct contact trenches are then buried, and a direct contact pattern 210 can be formed.

[0191] Next, the first conductive layer 222, the second conductive layer 224, the third conductive layer 226, and the cap layer 230 can be formed conformally on the substrate 100. The first conductive layer 222 can comprise the same material as the direct contact pattern 210, for example, but the exemplary embodiments of the present disclosure are not limited thereto.

[0192] Referring to Figure 16 The resulting structure of Figure 15 is patterned. Next, the gate spacers 240 are formed on the sidewalls of the structures formed in the first region I and the second region II. Thus, the semiconductor device according to Figure 3 can be formed.

[0193] For example, in Figure 13 , when the second length L2 is formed longer than the first length L1, the boundary region of the semiconductor device according to some exemplary embodiments of the present inventive concept can be the same as the boundary region shown in Figure 4a .

[0194] For example, in Figure 13 , when the second length L2 is formed shorter than the first length L1, the boundary region of the semiconductor device according to some exemplary embodiments of the present inventive concept can be the same as the boundary region shown in Figure 4b .

[0195] For example, in Figure 13 , when the second length L2 is formed substantially the same as the first length L1, the boundary region of the semiconductor device according to some exemplary embodiments of the present inventive concept can be the same as the boundary region shown in Figure 4c .

[0196] Thus, the method for fabricating a semiconductor device according to some exemplary embodiments of the present inventive concept can provide a method for fabricating a semiconductor device with improved integration and reliability while forming a high dielectric constant dielectric layer only in a core region.

[0197] While the present inventive concept has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those of ordinary skill in the art that various changes in form and details can be made therein without departing from the spirit and scope of the present inventive concept as defined by the following claims. Each exemplary embodiment should be considered in the context of the entire written description and drawings, and not a standalone.

Claims

1. A semiconductor device, comprising: The substrate includes a cell region, a core region, and a boundary region located between the cell region and the core region; A boundary element isolation layer is located in the substrate of the boundary region, the boundary element isolation layer separating the cell region from the core region; A high dielectric constant dielectric layer is located on at least a portion of the boundary element isolation layer and the substrate of the core region; A first conductive pattern includes a first extension overlapping the boundary element isolation layer, the first conductive pattern being located on the high dielectric constant dielectric layer; The second conductive pattern includes a second extension overlapping the boundary element isolation layer, and at least a portion of the second conductive pattern is located on the first conductive pattern; A conductive layer extending onto the boundary element isolation layer, a first portion of the conductive layer being located on the second conductive pattern; and Bit lines, including a second portion of the conductive layer on the cell region. The high dielectric constant dielectric layer includes a third extension overlapping the boundary element isolation layer. The first extension portion extends a first length in the direction from the core region toward the unit region, which is shorter than the second extension portion extends a second length in the same direction. The third extension extends for the same length as the first extension in the direction from the core region toward the unit region, and The boundary element isolation layer includes a recess in the boundary element isolation layer that does not overlap with the first extension to the third extension.

2. The semiconductor device of claim 1, wherein the end of each of the first extension to the third extension extending in the direction from the core region toward the cell region overlaps with the boundary element isolation layer.

3. The semiconductor device of claim 1, wherein the conductive layer includes a fourth extension overlapping the boundary element isolation layer, at least a portion of the conductive layer is on the second conductive pattern, and The fourth length of the conductive layer extending in the direction from the core region toward the cell region is longer than each of the first to third lengths.

4. The semiconductor device according to claim 1, further comprising: The active region is located in the substrate of the unit region; The character line extends along the first direction and extends through the active region; as well as Direct contact component, electrically connecting the active area and the bit line. The bit line extends in a second direction different from the first direction and extends through the active region and the word line, and The upper surface of the word line is lower than the upper surface of the substrate.

5. A semiconductor device, comprising: The substrate includes a cell region, a core region, and a boundary region disposed between the cell region and the core region; A boundary element isolation layer is located in the boundary region of the substrate to separate the cell region from the core region; A high dielectric constant dielectric layer is located on at least a portion of the boundary element isolation layer and on the core region of the substrate; The first conductive pattern includes a first extension that overlaps with the boundary element isolation layer and is located on the substrate; The second conductive pattern includes a second extension overlapping the boundary element isolation layer, and at least a portion of the second conductive pattern is located on the first conductive pattern; A conductive layer extending onto the boundary element isolation layer, a first portion of the conductive layer being located on the second conductive pattern; and Bit lines, including a second portion of the conductive layer on the cell region. The second extension extends further than the first extension in the direction from the core region toward the unit region, and The boundary element isolation layer includes a recess that does not overlap with the first extension and the second extension.

6. The semiconductor device of claim 5, wherein the high dielectric constant dielectric layer includes a third extension overlapping the boundary element isolation layer, and The first extension extends a first length in the direction from the core region toward the unit region, and the third extension extends a second length in the direction from the core region toward the unit region.

7. The semiconductor device of claim 6, wherein the conductive layer includes a fourth extension overlapping the boundary element isolation layer, at least a portion of the conductive layer is on the second conductive pattern, and The fourth extension extends further than the first and second extensions in the direction from the core region toward the unit region.

8. The semiconductor device of claim 5, wherein the conductive layer comprises a first conductive layer, a second conductive layer, and a third conductive layer sequentially stacked on the second conductive pattern. The first conductive layer comprises polycrystalline silicon. The second conductive layer comprises TiSiN, and The third conductive layer comprises tungsten.

9. The semiconductor device of claim 5, wherein the core region comprises a first region and a second region. The first conductive pattern is located on the first region of the substrate and is not disposed on the second region of the substrate. The second conductive pattern is located on the first conductive pattern in the first region of the substrate and on the second region.

10. A semiconductor device, comprising: The substrate includes a cell region, a core region, and a boundary region located between the cell region and the core region; A boundary element isolation layer is located in the substrate of the boundary region, the boundary element isolation layer separating the cell region from the core region; A high dielectric constant dielectric layer is located on at least a portion of the boundary element isolation layer and the substrate of the core region; A first conductive pattern includes a first extension overlapping the boundary element isolation layer, the first conductive pattern being located on the high dielectric constant dielectric layer; The second conductive pattern includes a second extension overlapping the boundary element isolation layer, and at least a portion of the second conductive pattern is located on the first conductive pattern; The high dielectric constant dielectric layer includes a third extension overlapping the boundary element isolation layer. The first extension portion extends a first length in the direction from the core region toward the unit region, which is shorter than the second extension portion extends a second length in the same direction. The third extension has the same third length as the second length in the direction from the core region toward the unit region, and The boundary element isolation layer includes a recess in the boundary element isolation layer that does not overlap with the first extension to the third extension.

11. The semiconductor device of claim 10, wherein the end of each of the first extension to the third extension extending in the direction from the core region toward the cell region overlaps with the boundary element isolation layer.

12. The semiconductor device of claim 10, further comprising a conductive layer, the conductive layer including a fourth extension overlapping the boundary element isolation layer, at least a portion of the conductive layer being on the second conductive pattern. The fourth length of the conductive layer extending in the direction from the core region toward the cell region is longer than each of the first to third lengths.

13. The semiconductor device of claim 10, further comprising: The active region is located in the substrate of the unit region; The character line extends along the first direction and extends through the active region; The bit line extends in a second direction different from the first direction and extends through the active region and the word line; as well as Direct contact component, electrically connecting the active area and the bit line. The upper surface of the word line is lower than the upper surface of the substrate.

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