Semiconductor device

Abstract

The present invention discloses a semiconductor device, comprising: a semiconductor substrate; a p-type body region located on top of the semiconductor substrate, the p-type body region being in contact with an emitter metal layer; the semiconductor substrate includes at least one first region, and the region outside the first region is a second region; a first p-type body region contact area is provided in the p-type body region within the first region, and the emitter metal layer is in contact with the first p-type body region contact area to form an ohmic contact; the p-type body region within the second region does not form an ohmic contact with the emitter metal layer. The present invention can improve the voltage oscillation, current oscillation and EMI problems generated when the semiconductor device is applied.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor devices, and particularly relates to a power semiconductor device. Background Art

[0002] Power semiconductor devices in the prior art usually improve the switching speed by reducing the Miller capacitance of the devices to reduce switching losses. However, too fast switching speed will lead to large voltage oscillations and current oscillations, which makes the EMI problem of power semiconductor devices serious during application. Summary of the Invention

[0003] In view of this, an object of the present invention is to provide a semiconductor device to reduce the EMI problem generated during the application of the semiconductor device.

[0004] To achieve the above object of the present invention, the present invention provides a semiconductor device, including:

[0005] A semiconductor substrate;

[0006] An n-type collector region and a p-type collector region which are alternately and spaced apart at the bottom of the semiconductor substrate;

[0007] An n-type drift region located in the semiconductor substrate and above the n-type collector region and the p-type collector region;

[0008] A p-type body region located at the top of the semiconductor substrate, and the p-type body region is in contact with an emitter metal layer;

[0009] The semiconductor substrate includes at least one first region, and the region outside the first region is a second region;

[0010] A first p-type body region contact area is provided in the p-type body region within the first region, and the emitter metal layer is in contact with the first p-type body region contact area and forms an ohmic contact;

[0011] The p-type body region within the second region does not form an ohmic contact with the emitter metal layer.

[0012] Optionally, the shape of the first region includes at least one of a polygon, a circle or an ellipse.

[0013] Optionally, a second p-type body region contact area is provided in the p-type body region within the second region, and the doping concentration of the second p-type body region contact area is less than that of the first p-type body region contact area.

[0014] Optionally, the emitter metal layer is in contact with the second p-type body region contact area but does not form an ohmic contact.

[0015] Optionally, it further includes an n-type emitter region located in the p-type body region, and the n-type emitter region is in contact with the emitter metal layer.

[0016] Optionally, it further includes an n-type field stop region located in the semiconductor substrate, and the n-type field stop region is located above the n-type collector region and the p-type collector region and below the n-type drift region.

[0017] Optionally, it further includes a gate structure, and the gate structure includes a gate dielectric layer and a gate.

[0018] Optionally, the gate structure is a planar gate structure or a trench gate structure.

[0019] For the semiconductor device proposed by the present invention, a first p-type body region contact region is arranged in the p-type body region of the first region, and the first p-type body region contact region forms an ohmic contact with the emitter metal layer, that is, the p-type body region in the first region forms an ohmic contact with the emitter metal layer. The p-type body region in the second region does not form an ohmic contact with the emitter metal layer. The potential of the p-type body region that does not form an ohmic contact is not fixed, resulting in a change in the threshold voltage Vth. Moreover, the greater the distance from the p-type body region that does not form an ohmic contact to the p-type body region that forms an ohmic contact, the greater the difference in the threshold voltage Vth between the p-type body region that does not form an ohmic contact and the p-type body region that forms an ohmic contact. Therefore, the semiconductor device of the present invention has a gradually changing threshold voltage Vth. When turning on and off, the current and voltage do not easily mutate, thereby reducing the EMI problem generated when the semiconductor device is applied. Brief Description of the Drawings

[0020] In order to more clearly illustrate the technical solutions of the exemplary embodiments of the present invention, the following briefly introduces the drawings required for describing the embodiments.

[0021] Figure 1 is a top view schematic diagram of the first embodiment of the semiconductor device provided by the present invention;

[0022] Figure 2 is Figure 1 a cross-sectional schematic diagram of the structure shown along the AA direction;

[0023] Figure 3 is a top view schematic diagram of the second embodiment of the semiconductor device provided by the present invention. Detailed Description of the Embodiments

[0024] The following will fully describe the technical solutions of the present invention in combination with the drawings in the embodiments of the present invention. It should be understood that the terms such as "having", "including", and "comprising" used in the present invention do not exclude the presence of one or more other elements or their combinations.

[0025] Those skilled in the art should understand that a power semiconductor device chip includes a cell region and a terminal region, wherein the cell region is a current working region, and the terminal region is used to improve the withstand voltage of the cells at the outermost edge of the cell region. The semiconductor device described in the embodiment of the present invention refers to the cell region in the power semiconductor device chip.

[0026] Figure 1 is a schematic top view of a first embodiment of a semiconductor device provided by the present invention, Figure 2 yes Figure 1 The cross-sectional view of the structure shown in FIG. Figure 1 and Figure 2 As shown, the semiconductor device of the present invention includes a semiconductor substrate 10, which is usually a silicon substrate, an n-type collector region 11 and a p-type collector region 13 located at the bottom of the semiconductor substrate 10 and alternately spaced, and an n-type drift region 12 located above the n-type collector region 11 and the p-type collector region 13. A p-type body region 20 is located at the top of the semiconductor substrate 10, and the p-type body region 20 forms a pn junction structure with the n-type drift region 12. The cell region of the semiconductor device chip includes several p-type body regions. Figure 1 and Figure 2 Only six p-type body regions 20 are shown as examples. The n-type emitter region 21 is located within the p-type body region 20 . Both the p-type body region 20 and the n-type emitter region 21 are in contact with the emitter metal layer 17 .

[0027] Optionally, an n-type field stop region may be further provided in the semiconductor substrate 10 . The n-type field stop region is located above the n-type collector region 11 and the p-type collector region 13 and below the n-type drift region 12 . The n-type field stop region is a conventional choice in the prior art and will not be specifically illustrated in the embodiments of the present invention.

[0028] like Figure 1 As shown, in a top view of the upper surface of the semiconductor substrate 10, the semiconductor substrate 10 includes at least one first region 51. The present invention does not specifically limit the number and shape of the first region 51. Figure 1 Only one first area 51 is shown as an example, and the first area 51 is a circular structure, and the area outside the first area 51 is defined as the second area.

[0029] A first p-type body contact region 22 is provided within the p-type body region 20 located within the first region 51. The emitter metal layer 17 contacts the first p-type body contact region 22, forming an ohmic contact. Because the doping concentration of the first p-type body contact region 22 is greater than the doping concentration of the p-type body region 20, the first p-type body contact region 22 increases the doping concentration at the point of contact between the p-type body region 20 and the emitter metal layer 17, thereby forming an ohmic contact between the p-type body region 20 within the first region 51 and the emitter metal layer 17.

[0030] Since the doping concentration of the p-type body region 20 in the second region is relatively low, an ohmic contact is not formed after the p-type body region 20 in the second region contacts the emitter metal layer 17. Optionally, a second p-type body contact region may also be formed in the p-type body region 20 in this second region. However, the doping concentration of the second p-type body region is lower than that of the first p-type body contact region 22, so that an ohmic contact cannot be formed after the second p-type body contact region contacts the emitter metal layer 17, or the ohmic contact resistance formed after the second p-type body contact region contacts the emitter metal layer 17 is relatively large.

[0031] As Figure 2 shown, the semiconductor device of the present invention further includes a gate structure. The gate structure includes a gate dielectric layer 14 and a gate 15. The gate structure is isolated from the emitter metal layer 17 by an interlayer insulating layer 16. Figure 2 In, the gate structure of the semiconductor device of the present invention is a planar gate structure. Optionally, the gate structure of the semiconductor device of the present invention may also be a trench gate structure. This structure is a conventional choice in the prior art and will not be specifically shown in the embodiments of the present invention.

[0032] In the semiconductor device of the present invention, the p-type body region 20 in the first region 51 forms an ohmic contact with the emitter metal layer 17 through the first p-type body contact region 22. The p-type body region 20 in the second region does not form an ohmic contact with the emitter metal layer 17. The potential of the p-type body region 20 that does not form an ohmic contact is not fixed, resulting in a change in the threshold voltage Vth. Moreover, the greater the distance from the p-type body region 20 that forms an ohmic contact, the greater the difference in the threshold voltage Vth between the p-type body region 20 that does not form an ohmic contact and the threshold voltage Vth of the p-type body region that forms an ohmic contact. That is, in the second region, the threshold voltage difference between the p-type body region close to the first region and the p-type body region in the first region is smaller than the threshold voltage difference between the p-type body region far from the first region and the p-type body region in the first region. Therefore, the semiconductor device of the present invention has a gradually changing threshold voltage Vth. When turning on and off, the current and voltage do not easily mutate, thereby reducing the voltage oscillation, current oscillation, and EMI problems generated during the application of the semiconductor device. At the same time, the reverse recovery characteristics of the device can also be improved.

[0033] Figure 3 is a top view schematic diagram of the second embodiment of the semiconductor device provided by the present invention. In Figure 3Among them, the semiconductor substrate 10 includes six first regions 51. The first regions 51 are rectangular. Optionally, the first regions 51 can be regular figures such as triangles, squares, regular polygons, rectangles, parallelograms, trapezoids, circles, ellipses, etc., or irregular figures. The embodiments of the present invention do not limit the shape of the first regions 51. The top view shape of the first regions 51 only needs to be a packaging figure, for example, a closed figure formed by sequentially connecting the head and tail of straight lines and / or curves.

[0034] Further, in Figure 1 and Figure 3 In the top view schematic diagrams shown, the example of the second region surrounding the first region is used for illustration. It should be noted that the embodiments of the present invention do not limit the relative positional relationship between the first region and the second region. It can be as Figure 1 and Figure 3 shown, or the first region can surround the second region, or the first region and the second region can be arranged in sequence along a direction parallel to the plane where the semiconductor substrate is located.

[0035] The above specific implementation manners and embodiments are specific supports for the technical idea of the present invention. The protection scope of the present invention cannot be limited thereby. Any equivalent change or equivalent modification made on the basis of this technical solution according to the technical idea proposed by the present invention still belongs to the protection scope of the technical solution of the present invention.

Claims

1. A semiconductor device, characterized in that, Comprising: A semiconductor substrate; An n-type collector region and a p-type collector region which are alternately and spacedly arranged at the bottom of the semiconductor substrate; An n-type drift region located within the conductor substrate and above the n-type collector region and the p-type collector region; A p-type body region located at the top of the semiconductor substrate, and the p-type body region is in contact with an emitter metal layer; The semiconductor substrate includes at least one first region, and the region outside the first region is a second region; A first p-type body region contact area is provided in the p-type body region within the first region, and the emitter metal layer is in contact with the first p-type body region contact area to form an ohmic contact; No ohmic contact is formed between the p-type body region within the second region and the emitter metal layer; The semiconductor device further includes an n-type emitter region located within the p-type body region, and the n-type emitter region is in contact with the emitter metal layer.

2. The semiconductor device according to claim 1, wherein, The shape of the first region includes at least one of a polygon, a circle or an ellipse.

3. The semiconductor device according to claim 1, characterized in that, A second p-type body region contact area is provided in the p-type body region within the second region, and the doping concentration of the second p-type body region contact area is less than that of the first p-type body region contact area.

4. The semiconductor device according to claim 3, characterized in that, The emitter metal layer is in contact with the second p-type body region contact area but no ohmic contact is formed.

5. The semiconductor device according to claim 1, wherein, It further includes an n-type field stop region located within the semiconductor substrate, and the n-type field stop region is located above the n-type collector region and the p-type collector region and below the n-type drift region.

6. The semiconductor device according to claim 1, wherein, It further includes a gate structure, and the gate structure includes a gate dielectric layer and a gate.

7. The semiconductor device according to claim 6, wherein, The gate structure is a planar gate structure or a trench gate structure.

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