Semiconductor device

Abstract

Embodiments provide a semiconductor device capable of suppressing warpage. The semiconductor device of the embodiments includes a first metal layer, a dielectric layer, a second metal layer, a first semiconductor region, a second semiconductor region, a third semiconductor region, a first control electrode, and a first electrode. The dielectric layer is provided on the first metal layer. The second metal layer is provided on the dielectric layer and electrically connected to the first metal layer. The first semiconductor region is provided on the second metal layer and is a first conductive type electrically connected to the second metal layer. The second semiconductor region is provided on the first semiconductor region and is a second conductive type. The third semiconductor region is provided on the second semiconductor region and is the first conductive type. The first control electrode faces the second semiconductor region with a first insulating film interposed therebetween. The first electrode is provided on the third semiconductor region and the first control electrode, is electrically connected to the third semiconductor region, and is insulated from the first control electrode by a first insulating portion.

Description

[0001] Related applications

[0002] This application claims priority to Japanese Patent Application No. 2021-23985 (filed on February 18, 2021), which is the basic application. This application includes all contents of the basic application by reference to it. Technical Field

[0003] Embodiments of the present invention relate to semiconductor devices. Background Technology

[0004] In the manufacturing process of semiconductor devices, warping sometimes occurs on the wafers on which the semiconductor devices are mounted. Wafer warping poses a potential risk of reducing the manufacturing efficiency of semiconductor devices. Therefore, it is desirable to suppress warping in semiconductor devices. Summary of the Invention

[0005] Embodiments of the present invention provide a semiconductor device capable of suppressing warping.

[0006] The semiconductor device of the embodiment includes a first metal layer, a dielectric layer, a second metal layer, a first semiconductor region, a second semiconductor region, a third semiconductor region, a first control electrode, and a first electrode. The dielectric layer is disposed on the first metal layer. The second metal layer is disposed on the dielectric layer and is electrically connected to the first metal layer. The first semiconductor region is disposed on the second metal layer and is of a first conductivity type, electrically connected to the second metal layer. The second semiconductor region is disposed on the first semiconductor region and is of a second conductivity type. The third semiconductor region is disposed on the second semiconductor region and is of a first conductivity type. The first control electrode is positioned opposite the second semiconductor region through a first insulating film. The first electrode is disposed on the third semiconductor region and the first control electrode, is electrically connected to the third semiconductor region, and is insulated from the first control electrode through a first insulating portion. Attached Figure Description

[0007] Figure 1 This is a top view of a semiconductor device illustrating an embodiment.

[0008] Figure 2 This is a cross-sectional view of a semiconductor device illustrating an embodiment.

[0009] Figure 3 This is a cross-sectional view of a semiconductor device illustrating an embodiment.

[0010] Figure 4 (a) and (b) are cross-sectional views of modified examples of the semiconductor device illustrating the embodiments.

[0011] Figure 5(a) and (b) are cross-sectional views of modified examples of the semiconductor device illustrating the embodiments.

[0012] Figure 6 (a)~ Figure 7 (d) is a cross-sectional view illustrating the manufacturing method of an embodiment. Detailed Implementation

[0013] Hereinafter, various embodiments of the present invention will be described with reference to the accompanying drawings.

[0014] The accompanying drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the ratio of the size between parts, etc., may not be the same as in reality. Even when representing the same part, there are cases where the dimensions and ratios of each part are represented differently in the accompanying drawings.

[0015] In this application specification and figures, elements that are the same as those already described are labeled with the same reference numerals and detailed descriptions are omitted where appropriate.

[0016] In the following description and accompanying figures, n ++ n + n － The markings indicate the relative levels of impurity concentration. Specifically, a "+" marking indicates a relatively higher impurity concentration compared to markings without either "+" or "-" markings; a "-" marking indicates a relatively lower impurity concentration compared to markings without either "+" or "-" markings; and a "++" marking indicates a relatively higher impurity concentration compared to markings with "+". These markings represent the relative levels of net impurity concentration after mutual compensation when both p-type and n-type impurities are present in each region. For the embodiments described below, the p-type (an example of the second conductivity type) and n-type (an example of the first conductivity type) of each semiconductor region can also be reversed to implement these embodiments.

[0017] Figure 1 This is a top view of a semiconductor device illustrating an implementation method.

[0018] like Figure 1 As shown, the semiconductor device 100 of the embodiment includes a first element region R1 and a second element region R2 arranged in the X direction. A first element MOS1 is provided in the first element region R1, and a second element MOS2 is provided in the second element region R2. The first element MOS1 and the second element MOS2 are transistors. An intermediate region R3 without any elements (transistors) is provided between the first element region R1 and the second element region R2.

[0019] Furthermore, the semiconductor device in the embodiment may not necessarily have two transistors; it may also have only one transistor. That is, it may not necessarily have a second element region R2 and an intermediate region R3.

[0020] A source electrode 61, a first electrode pad 71, a second electrode pad 72, and a third electrode pad 73 are provided on the surface of the first component region R1. The first to third electrode pads 71 ​​to 73 are arranged in the Y direction. The second electrode pad 72 is located between the first electrode pad 71 and the third electrode pad 73. The source electrode 61 has an opening 61a that covers substantially the entire first component region R1 except for the area where the opening 61a is provided. The first electrode pad 71 and the third electrode pad 73 are, for example, source electrode pads and are electrically connected to the source electrode 61. The second electrode pad 72 is, for example, connected to the gate electrode 41 (see reference). Figure 2 The gate electrode pads, which are electrically connected, are disposed within the opening 61a and are insulated from the source electrode 61.

[0021] Similarly, a source electrode 62, a fourth electrode pad 74, a fifth electrode pad 75, and a sixth electrode pad 76 are provided on the surface of the second element region R2. The fourth to sixth electrode pads 74 to 76 are arranged in the Y direction. The fifth electrode pad 75 is located between the fourth electrode pad 74 and the sixth electrode pad 76. The source electrode 62 has an opening 62a that covers substantially the entire second element region R2 except for the area where the opening 62a is provided. The fourth electrode pad 74 and the sixth electrode pad 76 are, for example, source electrode pads and are electrically connected to the source electrode 62. The fifth electrode pad 75 is, for example, connected to the gate electrode 42 (see reference). Figure 2 The gate electrode pads, which are electrically connected, are disposed within the opening 62a and are insulated from the source electrode 62.

[0022] In this example, with the intermediate region R3 extending in the Y direction as the center, the first element region R1 and the second element region R2 have a symmetrical structure.

[0023] Figure 2 This is a cross-sectional view of a semiconductor device illustrating an embodiment.

[0024] Figure 2 express Figure 1 The cross-section along line A1-A2 is shown. Figure 2 As shown, the semiconductor device 100 of the embodiment includes a first metal layer 11, a second metal layer 12, a conductive portion 13, a dielectric layer 20, and a semiconductor region 31 (first semiconductor region). These are disposed throughout the first element region R1, the second element region R2, and the intermediate region R3.

[0025] Furthermore, in the description of the implementation, the direction from the first metal layer 11 toward the second metal layer 12 is defined as the Z direction (first direction), a direction perpendicular to the Z direction is defined as the X direction (second direction), and a direction perpendicular to both the Z and X directions is defined as the Y direction (third direction). For clarity, the direction from the first metal layer 11 toward the second metal layer 12 is referred to as "up," and its opposite direction as "down." These directions are based on the relative positional relationship between the first metal layer 11 and the second metal layer 12 and are independent of the direction of gravity.

[0026] A dielectric layer 20 is disposed on top of a first metal layer 11 and is in contact with the upper surface of the first metal layer 11. A second metal layer 12 is disposed on top of the dielectric layer 20 and is in contact with the upper surface of the dielectric layer 20. A conductive portion 13 is arranged with the dielectric layer 20 in a direction perpendicular to the Z direction and is in contact with the side surface of the dielectric layer 20. The second metal layer 12 and the first metal layer 11 are electrically connected through the conductive portion 13. The conductive portion 13 may also be formed integrally and continuously with at least one of the first metal layer 11 and the second metal layer 12.

[0027] For example, the first metal layer 11, the second metal layer 12, and the dielectric layer 20 each apply stress to the semiconductor region 31. For example, the first metal layer 11 applies compressive stress to the semiconductor region 31 by contracting in the direction along the X-Y plane. For example, the second metal layer 12 applies compressive stress to the semiconductor region 31 by contracting in the direction along the X-Y plane.

[0028] On the other hand, the stress exerted by the dielectric layer 20 on the semiconductor region 31 may include a component whose direction is opposite to that of the stress exerted on the semiconductor region 31 by at least one of the first metal layer 11 and the second metal layer 12. For example, the dielectric layer 20 applies stresses in directions opposite to those generated by the first metal layer 11 and the second metal layer 12. More specifically, for example, the dielectric layer 20 applies tensile stress (stress of the tensile semiconductor region 31) to the semiconductor region 31 in a manner in which the dielectric layer 20 extends in a direction along the X-Y plane.

[0029] For example, stress may sometimes be generated during the film formation process due to differences in the coefficients of thermal expansion (linear expansion) of each layer and temperature changes. For example, the coefficient of thermal expansion of the first metal layer 11 is greater than that of the dielectric layer 20 and the semiconductor region 31. For example, the coefficient of thermal expansion of the second metal layer 12 is greater than that of the dielectric layer 20 and the semiconductor region 31.

[0030] The thickness of the first metal layer 11 (along its length in the Z direction) is greater than the thickness of the second metal layer 12. The thickness of the dielectric layer 20 is greater than the thickness of the second metal layer 12.

[0031] Semiconductor region 31 is disposed on the second metal layer 12. Semiconductor region 31 is n-type (first conductivity type). Semiconductor region 31 and the second metal layer 12 are in an ohmic contact, for example. Semiconductor region 37 is disposed on semiconductor region 31. For example, semiconductor region 31 is n-type. ++ Type, semiconductor region 37 is n － For example, the n-type impurity concentration in semiconductor region 31 is higher than that in semiconductor region 37.

[0032] Furthermore, the first element region R1 includes a base region 32 (second semiconductor region), a source region 33 (third semiconductor region), a gate electrode 41 (first control electrode), and a gate insulating film 51 (first insulating film). The first element MOS1 is a field-effect transistor (e.g., Metal-Oxide-Semiconductor Field-Effect Transistor: MOSFET) formed from a portion of the semiconductor region 31, the base region 32, the source region 33, the gate electrode 41, and the gate insulating film 51.

[0033] The base region 32 is selectively disposed on the semiconductor region 37. The base region 32 is p-type (second conductivity type).

[0034] The source region 33 is selectively disposed above the base region 32. The source region 33 is of the first conductivity type (n). + (e.g., source region 33). For example, the n-type impurity concentration of source region 33 is higher than that of semiconductor region 37 and lower than that of semiconductor region 31. In this example, multiple source regions 33 are provided and arranged in the X direction.

[0035] A gate electrode 41 is disposed on the semiconductor region 37 via a gate insulating film 51. The gate electrode 41 is opposed to a portion of the semiconductor region 37, a portion of the base region 32, and a portion of the source region 33 via the gate insulating film 51. In this example, multiple gate electrodes 41 and gate insulating films 51 are provided. The multiple gate electrodes 41 are arranged in the X direction, and each gate electrode 41 extends in the Y direction. The gate electrode 41 is connected to a second electrode pad 72 (see reference 1) via a contact (not shown). Figure 1 Electrical connection.

[0036] Multiple trenches T1 are formed on the semiconductor region 37. The multiple trenches T1 are arranged in the X direction and each trench T1 extends in the Y direction. Each trench T1 is disposed in the source region 33 and the base region 32, and reaches the semiconductor region 37. A gate insulating film 51 is disposed in each trench T1, and a gate electrode 41 is disposed on the gate insulating film 51. Moreover, an insulating portion 55 is provided between the gate electrode 41 and the source electrode 61 in each trench T1.

[0037] The source electrode 61 is disposed on the source region 33 and the gate electrode 41, and is electrically connected to the source region 33. The gate electrode 41 and the source electrode 61 are electrically insulated from each other by an insulating portion 55 (first insulating portion).

[0038] Similar to the first element region R1, the second element region R2 includes a base region 34 (fourth semiconductor region), a source region 35 (fifth semiconductor region), a gate electrode 42 (second control electrode), and a gate insulating film 52 (second insulating film). The second element MOS2 is a MOSFET formed by a portion of the semiconductor region 31, the base region 34, the source region 35, the gate electrode 42, and the gate insulating film 52.

[0039] The base region 34 is selectively disposed on the semiconductor region 37. The base region 34 is p-type (second conductivity type).

[0040] The source region 35 is selectively disposed above the base region 34. The source region 35 is of the first conductivity type (n). + (e.g., source region 35). For example, the n-type impurity concentration in source region 35 is higher than that in semiconductor region 37, but lower than that in semiconductor region 31. In this example, multiple source regions 35 are provided, and the multiple source regions 35 are arranged in the X direction.

[0041] A gate electrode 42 is disposed on the semiconductor region 37, separated by a gate insulating film 52. The gate electrode 42 is opposed to a portion of the semiconductor region 37, a portion of the base region 34, and a portion of the source region 35, separated by the gate insulating film 52. In this example, multiple gate electrodes 42 and gate insulating films 52 are provided. The multiple gate electrodes 42 are arranged in the X direction, and each gate electrode 42 extends in the Y direction. The gate electrode 42 is connected to a fifth electrode pad 75 (see reference 55) via a contact (not shown). Figure 1 Electrical connection.

[0042] Multiple trenches T2 are formed on the semiconductor region 37. The multiple trenches T2 are arranged in the X direction and each trench T2 extends in the Y direction. Each trench T2 is disposed in the source region 35 and the base region 34, and reaches the semiconductor region 37. A gate insulating film 52 is disposed in each trench T2, and a gate electrode 42 is disposed on the gate insulating film 52. Moreover, an insulating portion 56 is provided between the gate electrode 42 and the source electrode 62 in each trench T2.

[0043] The source electrode 62 is disposed on the source region 35 and the gate electrode 42, and is electrically connected to the source region 33. The gate electrode 42 and the source electrode 62 are electrically insulated from each other by the insulating portion 56 (the second insulating portion).

[0044] Figure 3 This is a cross-sectional view of a semiconductor device illustrating an embodiment.

[0045] Figure 3 express Figure 2 The cross-section shown is along line A3-A4. (As shown...) Figure 3 As shown, the dielectric layer 20 has an opening 20e. A conductive portion 13 is disposed within the opening 20e. That is, the conductive portion 13 is surrounded by the dielectric layer 20 in the X-Y plane. The side of the conductive portion 13 is in contact with the dielectric layer 20. In this example, the opening 20e is approximately circular. Therefore, the conductive portion 13 is cylindrical, connecting the first metal layer 11 and the second metal layer 12. In other words, the first metal layer 11 and the second metal layer 12 form a double-layer metal structure sandwiching the dielectric layer 20 with openings.

[0046] In this example, when viewed from above, multiple conductive portions 13 are provided in the regions overlapping with the first element region R1 and the regions overlapping with the second element region R2. For example, multiple conductive portions 13 are provided below the source electrode 61 and below the source electrode 62, respectively. The multiple conductive portions 13 may also be arranged at equal intervals in the X or Y direction, for example.

[0047] An example of the material of each component of the semiconductor device 100 will be described.

[0048] Semiconductor regions 31, 37, 32, 33, 34, and 35 are semiconductor materials, including silicon, silicon carbide, gallium nitride, or gallium arsenide. When silicon is used as the semiconductor material, arsenic, phosphorus, or antimony can be used as the n-type impurity. Boron can be used as the p-type impurity. For example, base regions 32, 33, 34, and 35 can be formed by ion implantation of impurities into a silicon semiconductor substrate. A semiconductor substrate can be used in at least one of semiconductor regions 31 and 37. Either semiconductor region 31 or semiconductor region 37 can also be formed by ion implantation of impurities.

[0049] Gate electrode 41 and gate electrode 42 contain conductive materials such as polycrystalline silicon doped with impurities.

[0050] The gate insulating film 51, the gate insulating film 52, the insulating portion 55, and the insulating portion 56 contain insulating materials such as silicon oxide.

[0051] The first metal layer 11, the second metal layer 12, the conductive portion 13, the source electrode 61, and the source electrode 62 comprise metals such as aluminum, copper, silver, titanium, and tungsten. The material of the first metal layer 11 may be the same as or different from the material of the second metal layer 12. The material of the conductive portion 13 may be the same as or different from the material of the first metal layer 11 or the second metal layer 12.

[0052] The dielectric layer 20 comprises aluminum oxide (e.g., Al2O3) or silicon nitride (e.g., Si3N4). The dielectric layer 20 is, for example, an insulator.

[0053] The operation of the semiconductor device 100 will be explained.

[0054] The semiconductor device 100 operates by applying a gate bias voltage to the gate electrodes 41 and 42 when a voltage is applied between the source electrodes 61 and 62. For example, when the MOSFET is turned on by applying a gate bias voltage to the gate electrodes 41 and 42, the current is as follows: Figure 2 The path shown in CP1 flows from source electrode 61 to source electrode 62, or as shown in CP1. Figure 2 The current flows from source electrode 62 to source electrode 61 in the path CP2 shown. Alternatively, the current may also include components that flow through the second metal layer 12 without passing through the conductive portion 13 and the first metal layer 11.

[0055] The first metal layer 11, the second metal layer 12, and the conductive portion 13 serve as the drain electrode for each of the first element MOS1 and the second element MOS2. In other words, the first element MOS1 and the second element MOS2 have a structure that shares a drain electrode.

[0056] This type of MOSFET with a shared drain structure can be used, for example, as a protection circuit for a battery pack (rechargeable battery) in a smartphone or similar device. For example, a battery is connected to source electrode 61, and a power source is connected to source electrode 62. In this case, the battery is charged by flowing current from the power source at source electrode 62 to the battery at source electrode 61. Alternatively, for example, a battery is connected to source electrode 61, and a battery pack is connected to source electrode 62. In this case, the battery is discharged by flowing current from the battery at source electrode 61 to the rechargeable battery at source electrode 62, and the battery pack is charged. A protection IC is connected to gate electrodes 41 and 42, and the gate bias is controlled by the protection IC. By controlling the gate bias, the protection IC can suppress overcharging of the battery pack. However, the semiconductor device in this embodiment may not necessarily be a shared drain structure, nor may it be a protection circuit for a battery pack.

[0057] The effects of the implementation method are explained.

[0058] The metal layer formed on the back side of the semiconductor region applies stress to the semiconductor region. Therefore, for example, if the metal layer is thick, there is a risk of warping of the wafer or chip on which the semiconductor device is located. For example, the first metal layer 11 and the second metal layer 12 apply stress to the semiconductor region. In contrast, in this embodiment, a dielectric layer 20 is provided between the first metal layer 11 and the second metal layer 12. As a result, compared to simply thickening the metal layer without providing the dielectric layer 20, the stress applied to the semiconductor region 31 can be mitigated. As a result, wafer or chip warping can be suppressed. In addition, for example, the strength of the wafer or chip can be improved.

[0059] The stress exerted by the dielectric layer 20 on the semiconductor region 31 preferably includes a component whose direction is opposite to that of the stress exerted on the semiconductor region 31 by at least one of the first metal layer 11 and the second metal layer 12. This reduces the total stress exerted on the semiconductor region 31, and consequently reduces the total stress generated throughout the wafer or chip.

[0060] In this way, the dielectric layer 20 can function as a strength protection layer or a stress buffer layer (stress relief layer). As an example of the material for this dielectric layer 20, alumina or silicon nitride are preferred.

[0061] In the semiconductor device 100, current flows longitudinally (Z-direction) through the semiconductor layers (semiconductor regions 31, 37, base regions 32, 34, and source regions 33, 35). By thinning the semiconductor layers, the longitudinal current path is shortened, thereby reducing the longitudinal resistive component. That is, the on-resistance of the semiconductor device 100 can be reduced. However, thinning the semiconductor layers poses a risk of reducing the bending strength of the chip or wafer.

[0062] Furthermore, current flows laterally (along the X-Y plane) in the drain electrode (e.g., the first metal layer 11 and the second metal layer 12). By thickening the drain electrode, the effective lateral current path increases, thereby reducing the lateral resistive component. That is, the on-resistance of the semiconductor device 100 can be reduced. However, if the metal layer (drain electrode) is thickened, the stress exerted by the metal layer on the semiconductor layer increases. Therefore, the effect of film stress on the chip or wafer increases, posing a risk of increased warpage.

[0063] Especially when the semiconductor layer is thinned and the metal layer is thickened to reduce on-resistance, there is a risk of increased warpage due to the decrease in the bending strength of the chip or wafer and the increase in film stress. That is, it is difficult to simultaneously achieve thinner semiconductor layers and thicker metal layers. In contrast, in this embodiment, warpage can be suppressed by providing the dielectric layer 20, thus making it easier to simultaneously thin the semiconductor layer and thicken the metal layer (e.g., the first metal layer 11). According to this embodiment, chip or wafer warpage can be suppressed while reducing on-resistance. Compared to simply thickening the metal layer (drain electrode) without providing the dielectric layer 20, the amount of chip or wafer warpage can be reduced.

[0064] For example, the thickness of the semiconductor layer (the distance between the lower surface of the semiconductor region 31 and the upper surface of the source region 33) is 15 μm or more and 100 μm or less. The thickness of the semiconductor layer can also be thinner than the thickness of the drain electrode (the distance between the lower surface of the first metal layer 11 and the upper surface of the second metal layer 12). As a result, the on-resistance can be reduced.

[0065] The second metal layer 12 is thinner than the first metal layer 11. For example, the second metal layer 12 only needs to have a thickness sufficient to make a 31-ohm contact with the semiconductor region 31. Therefore, by thinning the second metal layer 12, the stress generated by the second metal layer 12 can be reduced. On the other hand, by thickening the first metal layer 11, the on-resistance can be reduced. The thickness of the dielectric layer 20 can be appropriately adjusted according to the thickness (stress) of the first metal layer 11 (and the second metal layer 12) to reduce the warpage of the chip or wafer. For example, the dielectric layer 20 is thicker than the second metal layer 12. The dielectric layer 20 can be thicker or thinner than the first metal layer 11.

[0066] Figure 4 of (a), Figure 4 (b) Figure 5 (a) and Figure 5 (b) is a cross-sectional view of a modified example of the semiconductor device illustrating the embodiment.

[0067] Figure 4 (a) and Figure 4 (b) represents semiconductor device 101. Figure 5 (a) and Figure 5 (b) represents semiconductor device 102. The planar shapes of the dielectric layer 20 and conductive portion 13 of these semiconductor devices 101 and 102 are different from the planar shapes of the dielectric layer 20 and conductive portion 13 of the semiconductor device 100. Otherwise, semiconductor devices 101 and 102 are the same as semiconductor device 100.

[0068] Figure 4 (b) indicates Figure 4 The cross-section along line A5-A6 is shown in (a). Additionally, in Figure 4 In (b), dashed lines indicate the positions of the first to sixth electrode pads 71 ​​to 76, etc. For example... Figure 4 As shown in (b), in this example, the dielectric layer 20 has an opening 20e in the center. A conductive portion 13 is provided within the opening 20e.

[0069] The conductive portion 13 includes a first portion 13a, a second portion 13b, and a third portion 13c. The first portion 13a, second portion 13b, and third portion 13c are arranged continuously in the X direction. The first portion 13a is located between the second portion 13b and the third portion 13c. The first portion 13a overlaps with the intermediate region R3 (the region between source region 33 and source region 35) in the Z direction. That is, the first portion 13a is located below the first element MOS1 and the second element MOS2. The second portion 13b overlaps with the gate electrode 41 and a portion of the source region 33 in the Z direction. The third portion 13c overlaps with the gate electrode 42 and a portion of the source region 35 in the Z direction.

[0070] In the drain electrode of a semiconductor device with a shared drain structure, current tends to concentrate in the portion between the two transistors. In contrast, the conductive portion 13 includes a first portion 13a, a second portion 13b, and a third portion 13c. That is, in the portion where the current density increases, the first metal layer 11 and the second metal layer 12 are connected through the conductive portion 13. In other words, the dielectric layer 20 has a planar pattern that conducts the current path portions of the two MOSFETs. Therefore, even with the dielectric layer 20, the increase in resistance in the drain electrode can be suppressed. By providing the dielectric layer 20, the semiconductor layer can be thinned, thus reducing the overall on-resistance.

[0071] Figure 5 (b) indicates Figure 5 The cross-section along line A7-A8 is shown in (a). Additionally, in Figure 5 In (b), dashed lines indicate the positions of the first to sixth electrode pads 71 ​​to 76, etc. For example... Figure 5 As shown in (b), in this example, the dielectric layer 20 has a plurality of openings 20e in the central portion in the X direction along the Y direction. A conductive portion 13 is provided in each opening 20e.

[0072] Each conductive portion 13 includes a first portion 13a, a second portion 13b, and a third portion 13c. Therefore, in this example, in the portion where the current density increases, since the first metal layer 11 and the second metal layer 12 are connected through the conductive portion 13, the increase in resistance in the drain electrode can also be suppressed.

[0073] Furthermore, a plurality of conductive portions 13 are arranged in the Y direction. A portion 20p of a dielectric layer 20 extending in the X direction is provided between two adjacent conductive portions 13. The portion 20p of the dielectric layer 20 can suppress the stress exerted on the semiconductor region 31 from the first metal layer 11 and the second metal layer 12. For example, the portion 20p of the dielectric layer 20 exerts stress on the semiconductor region 31 in the opposite direction to that of the first metal layer 11 and the conductive portions 13.

[0074] By increasing the total area of ​​the openings 20e (the total area of ​​the plurality of conductive portions 13 on the X-Y plane), the current path is expanded, thus suppressing the increase in on-resistance. By decreasing the total area of ​​the openings 20e, the area of ​​the dielectric layer 20, which serves as a stress-relieving layer, is increased, further suppressing warping.

[0075] However, in the embodiments, the planar pattern of the opening 20e (the planar pattern of the conductive portion 13) is not limited to the above. The area, width, spacing, and number of the openings 20e can be appropriately varied. When multiple openings 20e are provided, the opening 20e in the central part of the chip, which becomes the current path, can be wider than the opening 20e in the outer periphery of the chip. Appropriate combinations are also possible. Figure 3 The pattern of the roughly circular opening 20e shown is similar to... Figure 4 (b) or Figure 5 The pattern of the roughly rectangular opening 20e is shown in (b).

[0076] The manufacturing method of semiconductor devices is explained.

[0077] Figure 6 (a)~ Figure 7 (d) is a cross-sectional view illustrating the manufacturing method of an embodiment.

[0078] like Figure 6 As shown in (a), on the surface 200fs side of the substrate 200 (e.g., a silicon substrate), a semiconductor region 37, base regions 32 and 34, source regions 33 and 35, gate electrodes 41 and 42, gate insulating films 51 and 52, and source electrodes 61 and 62 are provided. The back side 200b side of the substrate 200 becomes the semiconductor film 31f, which serves as the semiconductor region 31. For convenience, the diagram of the gate insulating film is omitted.

[0079] like Figure 6 As shown in (b), a support substrate 202 (e.g., a glass substrate) is attached to the surface 200fs side of the substrate 200 using an adhesive 201.

[0080] like Figure 6 As shown in (c), the substrate 200 is thinned on the back side 200b of the polished substrate 200. This forms a semiconductor region 31. Then, a metal film 12f, which becomes a metal layer 12, is formed on the back side 200b of the substrate 200, i.e., the back side 31bs of the semiconductor region 31 (the side opposite to the base region 32). Sputtering, evaporation, deposition, or other methods can be used to form the metal film 12f. The metal film 12f may be, for example, a seed metal.

[0081] like Figure 6 As shown in (d), a dielectric film 20f, which forms the dielectric layer 20, is formed on the back side 12bs (the side opposite to the semiconductor region 31) of the metal film 12f. In the formation of the dielectric film 20f, methods that do not degrade the quality of the binder 201 and are formed without high temperatures can be used. For example, coating or PEALD (Plasma Enhanced Atomic Layer Deposition) methods can be used.

[0082] like Figure 7 As shown in (a), through-holes 20h are formed on the dielectric film 20f, for example, by RIE (reactive ion etching). The metal film 12f is exposed within the through-holes 20h. The through-holes 20h correspond to the openings 20e described above. Then, a conductive film 13f, forming conductive portions 13, is formed on the back surface 12bs of the metal film 12f and the back surface 20bs of the dielectric film 20f (the side opposite to the metal film 12f). Sputtering, evaporation, or deposition methods can be used to form the conductive film 13f.

[0083] In this example, through holes 20h are formed after the dielectric film 20f is formed, but a method of pasting a pre-formed porous film sheet can also be used.

[0084] like Figure 7As shown in (b), the back side 13bs (the side opposite to the metal film 12f) of the conductive film 13f is ground and planarized until the back side 20bs of the dielectric film 20f is exposed.

[0085] like Figure 7 As shown in (c), a metal film 11f is formed as a metal layer 11 on the back surface 20bs of the dielectric film 20f and the back surface 13bs of the conductive film 13f. Sputtering, evaporation, or deposition methods can be used to form the metal film 11f.

[0086] For example, the metal film 12f is thinner than the metal film 11f and thinner than the dielectric film 20f. By thinning the metal film 12f, the stress exerted on the substrate by the metal film 12f can be suppressed. Therefore, for example, the load on the substrate in processes following the formation of the metal film 12f (e.g., the formation of the dielectric film 20f, the formation of the through-hole 20h, etc.) can be suppressed. Thus, by thinning the substrate (semiconductor layer), the on-resistance of the semiconductor device can be reduced.

[0087] like Figure 7 As shown in (d), the adhesive 201 and the support substrate 202 are peeled off. Then, the substrate is appropriately cut. Through the above, semiconductor devices 100, 101, and 102 can be manufactured.

[0088] As described above, according to the embodiments, it is possible to provide a semiconductor device that can suppress warping.

[0089] The relative levels of impurity concentrations among the semiconductor regions in the embodiments described above can be confirmed, for example, using SCM (scanning electrostatic capacitance microscopy). Furthermore, the carrier concentration in each semiconductor region can be considered equal to the concentration of impurities activated in that region. Therefore, the relative levels of carrier concentrations among the semiconductor regions can also be confirmed using SCM. Additionally, the impurity concentration in each semiconductor region can be measured, for example, using SIMS (secondary ion mass analysis).

[0090] In this application specification, "electrical connection" includes not only direct contact connection, but also connection via other conductive components.

[0091] The embodiments of the present invention have been described above with reference to specific examples. However, the present invention is not limited to these specific examples. For example, any specific configuration of the elements included in a semiconductor device, provided that a person skilled in the art can similarly implement the present invention and obtain the same effects by appropriately selecting from the known scope, is included within the scope of the present invention.

[0092] Any combination of two or more elements from the various specific examples within the scope of technical feasibility, as long as it contains the spirit of the present invention, is included within the scope of the present invention.

[0093] Furthermore, as embodiments of the present invention, all semiconductor devices that can be implemented by those skilled in the art based on the above-described semiconductor device with appropriate design modifications, as long as they contain the spirit of the present invention, are also within the scope of the present invention.

[0094] Furthermore, within the scope of the present invention, any modifications and alterations that can be conceived by those skilled in the art are also considered to fall within the scope of the present invention.

[0095] Several embodiments of the present invention have been described, but these embodiments are provided as examples and are not intended to limit the scope of the invention. These new embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, and are also included in the scope of the invention and its equivalents as described in the claims.

Claims

1. A semiconductor device, wherein, have: First metal layer; A dielectric layer is disposed on top of the first metal layer; A second metal layer is disposed on the dielectric layer, is thinner than the first metal layer, and is electrically connected to the first metal layer. A first semiconductor region of a first conductivity type is disposed on the second metal layer and electrically connected to the second metal layer; A second semiconductor region of a second conductivity type is disposed on top of the first semiconductor region; A third semiconductor region of a first conductivity type is disposed on top of the second semiconductor region; The first control electrode is positioned opposite the second semiconductor region through the first insulating film; as well as A first electrode is disposed on the third semiconductor region and the first control electrode, is electrically connected to the third semiconductor region, and is insulated from the first control electrode by a first insulating portion.

2. The semiconductor device of claim 1, wherein, The semiconductor device also includes: A fourth semiconductor region of a second conductivity type is disposed on top of the first semiconductor region; A fifth semiconductor region of a first conductivity type is disposed on the fourth semiconductor region; The second control electrode is positioned opposite the fourth semiconductor region through the second insulating film; as well as The second electrode is disposed on the fifth semiconductor region and the second control electrode, is electrically connected to the fifth semiconductor region, and is insulated from the second control electrode through the second insulating portion.

3. The semiconductor device as claimed in claim 2, wherein, The semiconductor device further includes a conductive portion arranged with the dielectric layer in a direction perpendicular to a first direction from the first metal layer toward the second metal layer, thereby electrically connecting the first metal layer and the second metal layer.

4. The semiconductor device of claim 3, wherein, Multiple conductive portions are provided below the first electrode and below the second electrode, respectively.

5. The semiconductor device of claim 3, wherein, The conductive portion has a first portion that overlaps with an intermediate region between the third semiconductor region and the fifth semiconductor region in the first direction.

6. The semiconductor device of claim 5, wherein, The conductive part is provided in multiple ways.

7. The semiconductor device according to any one of claims 1 to 6, wherein, The dielectric layer comprises at least one of silicon nitride and aluminum oxide.

8. A semiconductor device, wherein, have: First metal layer; A dielectric layer is disposed on top of the first metal layer; A second metal layer is disposed on the dielectric layer and electrically connected to the first metal layer; A first semiconductor region of a first conductivity type is disposed on the second metal layer and electrically connected to the second metal layer; A second semiconductor region of a second conductivity type is disposed on top of the first semiconductor region; A third semiconductor region of a first conductivity type is disposed on top of the second semiconductor region; A fourth semiconductor region of a second conductivity type is disposed on top of the first semiconductor region; A fifth semiconductor region of a first conductivity type is disposed on the fourth semiconductor region; The first control electrode is positioned opposite the second semiconductor region through the first insulating film; The second control electrode is positioned opposite the fourth semiconductor region through the second insulating film; A first electrode is disposed on the third semiconductor region and the first control electrode, is electrically connected to the third semiconductor region, and is insulated from the first control electrode through a first insulating portion; The second electrode is disposed on the fifth semiconductor region and the second control electrode, is electrically connected to the fifth semiconductor region, and is insulated from the second control electrode through the second insulating portion; as well as The conductive portion is arranged with the dielectric layer in a direction perpendicular to a first direction from the first metal layer toward the second metal layer, electrically connecting the first metal layer and the second metal layer. The conductive portion has: a first portion that overlaps with an intermediate region between the third semiconductor region and the fifth semiconductor region in the first direction; The second part overlaps with the third semiconductor region in the first direction; And the third part overlaps with the fifth semiconductor region in the first direction.

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