Lateral double diffused metal oxide semiconductor field effect transistor and method of fabricating the same

Abstract

The present application discloses a lateral double-diffused metal oxide semiconductor field effect transistor and a manufacturing method thereof. The lateral double-diffused metal oxide semiconductor field effect transistor comprises a semiconductor substrate, a well region arranged in the semiconductor substrate, a base region arranged in the well region, a first gate electrode arranged on the semiconductor substrate, a source electrode arranged on one side of the first gate electrode, wherein the source electrode comprises a source contact region and a plurality of spurs, the spurs are connected with the source contact region, the spurs extend into the semiconductor substrate, and a first drain electrode arranged on the other side of the first gate electrode opposite to the source electrode.

Description

Laterally double-diffused metal-oxide-semiconductor field-effect transistors and their fabrication methods Technical Field

[0001] This invention relates to a laterally double-diffused metal-oxide-semiconductor field-effect transistor and its fabrication method, particularly to a laterally double-diffused metal-oxide-semiconductor field-effect transistor having multiple vias inserted into the source position and its fabrication method. Background Technology

[0002] In power devices with high-voltage handling capabilities, double-diffused MOS (DMOS) transistors continue to receive significant attention. Common DMOS transistors include vertical double-diffused MOS (VDMOS) and lateral double-diffused MOS (LDMOS) transistors. LDMOS transistors, due to their high operating bandwidth and efficiency, as well as their planar structure that facilitates integration with other integrated circuits, are now widely used in high-voltage operating environments, such as CPU power supplies, power management systems, AC / DC converters, and high-power or high-frequency power amplifiers.

[0003] To increase the linear drain current in the linear region of LDMOS transistors, the industry currently places the P-type body at a shallower depth. However, this causes charge to accumulate on the substrate, resulting in leakage current. Summary of the Invention

[0004] In view of this, the present invention provides a double-diffused metal-oxide-semiconductor field-effect transistor (LDMOS) that increases the drain current in the linear region while avoiding leakage current.

[0005] According to a preferred embodiment of the present invention, a laterally double-diffused metal-oxide-semiconductor field-effect transistor includes a semiconductor substrate, a well region disposed in the semiconductor substrate, a substrate region disposed in the well region, a first gate electrode disposed on the semiconductor substrate, a source electrode disposed on one side of the first gate electrode, wherein the source electrode includes a source contact region and a plurality of vias, and the vias are connected to the source contact region and extend into the semiconductor substrate, and a first drain electrode is disposed on the other side of the first gate electrode opposite to the source electrode.

[0006] According to another preferred embodiment of the present invention, a method for fabricating a laterally double-diffused metal-oxide-semiconductor field-effect transistor includes providing a semiconductor substrate, wherein a well region is disposed in the semiconductor substrate, a substrate region is disposed in the well region, a gate electrode is disposed on the semiconductor substrate, and a drain and a source electrode are located in the semiconductor substrate on both sides of the gate electrode. Then, a metal silicide barrier layer is formed to cover the source electrode, wherein the metal silicide barrier layer includes a plurality of elongated contours. Next, a dielectric layer is formed to cover the semiconductor substrate. Then, the dielectric layer and the metal silicide barrier layer are etched to form a source contact hole located directly above the source electrode. The source contact hole includes a trench and a plurality of vias, each via being connected to the trench. Each via penetrates the metal silicide barrier layer and is inserted into the source electrode. The trench is located only in the dielectric layer. Finally, a conductive layer is formed to fill the source contact hole to form a source electrode.

[0007] To make the above-mentioned objects, features, and advantages of the present invention more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. However, the following preferred embodiments and drawings are for reference and illustration only and are not intended to limit the present invention. Attached Figure Description

[0008] Figures 1 to 2C are schematic diagrams illustrating a method for fabricating an LDMOS according to a first preferred embodiment of the present invention; wherein:

[0009] Figure 2A is a side view drawn along the tangent AA' in Figure 2;

[0010] Figure 2B is a side view drawn along the tangent BB' in Figure 2;

[0011] Figure 2C is a side view drawn along the tangent CC' in Figure 2;

[0012] Figures 3 to 5A are schematic diagrams illustrating a method for fabricating an LDMOS according to a second preferred embodiment of the present invention; wherein:

[0013] Figure 4A is a side view drawn along the tangent DD' in Figure 4;

[0014] Figure 5A is a side view of Figure 5 drawn along the tangent EE'.

[0015] Explanation of main component symbols

[0016] 10: Semiconductor substrate

[0017] 12a: First gate electrode

[0018] 12b: Second gate electrode

[0019] 14a: First drain electrode

[0020] 14b: Second drain electrode

[0021] 16: Source

[0022] 18: Metal silicide barrier layer

[0023] 18a: Long strip outline

[0024] 18b: Long strip outline

[0025] 20: Trap Zone

[0026] 22:Matrix area

[0027] 24: Metal silicides

[0028] 26: Dielectric layer

[0029] 28: Source contact hole

[0030] 28a: Groove

[0031] 28b: Through hole

[0032] 30a: First drain contact hole

[0033] 30b: Second drain contact hole

[0034] 32a: Doped region

[0035] 32b: Doped region

[0036] 34: Source electrode

[0037] 34a: Source contact region

[0038] 34b: Bolt

[0039] 36a: First drain electrode

[0040] 36b: Second drain electrode

[0041] 100:LDMOS

[0042] 200:LDMOS

[0043] D1: First Depth

[0044] D2: Second Depth

[0045] D3: Third Depth

[0046] S: Interval Detailed Implementation

[0047] Figures 1 to 2C illustrate a method for fabricating an LDMOS according to a first preferred embodiment of the present invention. Figure 2A is a side view drawn along tangent AA' in Figure 2. Figure 2B is a side view drawn along tangent BB' in Figure 2. Figure 2C is a side view drawn along tangent CC' in Figure 2.

[0048] As shown in Figure 1, a semiconductor substrate 10 is first provided. A first gate electrode 12a and a second gate electrode 12b are disposed on the semiconductor substrate 10. The first gate electrode 12a and the second gate electrode 12b may each include a capping layer (not shown) and a gate dielectric layer (not shown). A first drain 14a and a source 16 are located in the semiconductor substrate 10 on both sides of the first gate electrode 12a. The source 16 is located between the first gate electrode 12a and the second gate electrode 12b. A second drain 14b is disposed on the side of the second gate electrode 12b opposite to the source 16. Then, a metal silicide barrier layer 18 is formed to cover the source electrode 16. It is worth noting that the metal silicide barrier layer 18 at the source electrode 16 includes multiple elongated contours 18a / 18b, with a gap S between each elongated contour 18a / 18b, so that the source electrode 16 is not completely covered by the metal silicide barrier layer 18, and part of the semiconductor substrate 10 is exposed from the gap S, while the first drain electrode 14a and the second drain electrode 14b are not covered by the metal silicide barrier layer 18 at all. In addition, please refer to Figure 2A. A well region 20 is disposed in the semiconductor substrate 10, and a substrate region 22 is disposed in the well region 20. There is a first depth D1 between the bottom surface of the substrate region 22 and the upper surface of the semiconductor substrate 10, and there is a second depth D2 between the bottom surface of the well region 20 and the upper surface of the semiconductor substrate 10. The second depth D2 is greater than the first depth D1, that is, the bottom surface of the well region 20 is deeper than the bottom surface of the substrate region 22.

[0049] Next, as shown in Figures 2, 2A, 2B, and 2C, a metal silicide fabrication process is performed to form metal silicide 24 on the source 16, the first drain 14a, and the second drain 14b, forming a dielectric layer 26 covering the semiconductor substrate 10. For simplicity, the dielectric layer 26 is omitted in Figure 2. Then, the dielectric layer 26, the metal silicide barrier layer 18, and the source 16 are etched to form a source contact hole 28 located in the dielectric layer 28 directly above the source 16 and extending into the source 16. The source contact hole 28 includes a trench 28a and multiple vias 28b. Each via 28b is connected to the trench 28a, and each via 28a penetrates the metal silicide barrier layer 18 and inserts into the source 16. The trench 28a is located only in the dielectric layer 26.

[0050] When forming the aforementioned trench 28a, the dielectric layer 26 on the first drain 14a and the second drain 14b is etched together in the same etching step to form a first drain contact hole 30a and a second drain contact hole 30b. The first drain contact hole 30a exposes the metal silicide 24 on the first drain 14a, and the second drain contact hole 30b exposes the metal silicide 24 on the second drain 14b. When the first drain contact hole 30a, the second drain contact hole 30b and the trench 28a are formed... After the dielectric layer 26 is formed, that is, after the dielectric layer 26 is penetrated by the first drain contact hole 30a, the second drain contact hole 30b, and the trench 28a, the etchant is changed to continue etching the metal silicide barrier layer 18 on the source electrode 16 and the semiconductor substrate 10 below the metal silicide barrier layer 18, so as to form several vias 28b in the metal silicide barrier layer 18 and the semiconductor substrate 10 at the source electrode 16 to insert into the source electrode 16. In the figure, the vias 28b and the trench 28a are separated by dashed lines. After the vias 28b are completed, an ion doping process is performed to form a doped region 32b in the well region 20 below each via 28b.

[0051] According to another preferred embodiment of the present invention, the dielectric layer 28, the metal silicide barrier layer 18 and the semiconductor substrate 10 may be etched sequentially to form several vias 28b at the source electrode 16, and then the dielectric layer 26 may be etched again to form a trench 28a in the dielectric layer 26 above the source electrode 16, a first drain contact hole 30a above the first drain electrode 14a and a second drain contact hole 30b above the second drain electrode 14b.

[0052] Next, a conductive layer is formed and filled into the source contact hole 28, the first drain contact hole 30a, and the second drain contact hole 30b. The conductive layer filled into the source contact hole 28 serves as the source electrode 34. Multiple vias 34b are formed in the conductive layer within each via 28b of the source contact hole 28. A source contact region 34a is formed in the conductive layer within the trench 28a of the source contact hole 28. The source contact region 34a is connected to each via 34b, but the vias 34b do not contact each other. Furthermore, the conductive layer in the first drain contact hole 30a serves as a first drain electrode 36a, and the conductive layer in the second drain contact hole 30b serves as a second drain electrode 36b. Thus, the LDMOS 100 of the present invention is completed.

[0053] The structure of an LDMOS fabricated using the first preferred embodiment of the present invention will be described below with reference to Figures 2, 2A, 2B, and 2C. As shown in Figures 2, 2A, 2B, and 2C, a laterally double-diffused metal-oxide-semiconductor field-effect transistor 100 includes a semiconductor substrate 10, a well region 20 disposed in the semiconductor substrate 10, a substrate region 22 disposed in the well region 20, a first gate electrode 12a, and a second gate electrode 12b disposed on the semiconductor substrate 10. The first gate electrode 12a and the second gate electrode 12b may each include a capping layer (not shown) and a gate dielectric layer (not shown). A first drain 14a and a source 16 are located in the semiconductor substrate 10 on both sides of the first gate electrode 12a, and the source 16 is located in the semiconductor substrate 10 between the first gate electrode 12a and the second gate electrode 12b. A second drain 14b is disposed on the side of the second gate electrode 12b opposite to the source 16. Furthermore, a first depth D1 exists between the bottom surface of the substrate region 22 and the upper surface of the semiconductor substrate 10, and a second depth D2 exists between the bottom surface of the well region 22 and the upper surface of the semiconductor substrate 10. The second depth D2 is greater than the first depth D1, meaning the bottom surface of the well region 20 is deeper than the bottom surface of the substrate region 22. The semiconductor substrate 10 is of a first conductivity type, the well region 20 is of a second conductivity type, the substrate region 22 is of a first conductivity type, the first drain 14a and the second drain 14b are both of the second conductivity type, and the source 16 is primarily a region of the second conductivity type, but a doped region 32a of the first conductivity type is also provided within the region of the second conductivity type. The first conductivity type and the second conductivity type are different. In this embodiment, the first conductivity type is preferably P-type, and the second conductivity type is preferably N-type. In different embodiments, the first conductivity type can be N-type, and the second conductivity type is preferably P-type.

[0054] A metal silicide 24 covers the source electrode 16, the first drain electrode 14a, and the second drain electrode 14b. Notably, a metal silicide barrier layer 18 is disposed on the source electrode 16. This barrier layer 18 comprises multiple elongated contours 18a / 18b, with a spacing S between each contour 18a / 18b (see Figure 1 for the positions of the contours 18a / 18b and the spacing S). Therefore, the metal silicide 24 covers the spacing S. No metal silicide barrier layer 18 is present on the first drain electrode 14a and the second drain electrode 14b; therefore, the metal silicide 24 completely covers both electrodes.

[0055] A source electrode 34 is disposed on one side of the first gate electrode 12a. The source electrode 34 includes a source contact region 34a and a plurality of plugs 34b, and the plurality of plugs 34b are connected to the source contact region 34a. Each plug 34b extends and is inserted into the semiconductor substrate 10 located at the source electrode 16. Specifically, each plug 34b penetrates the metal silicide barrier layer 18 and is inserted into the source electrode 16. The source contact region 34a is completely located on the metal silicide 24, that is, the metal silicide 24 is located between the source contact region 34a and the upper surface of the semiconductor substrate 10. In addition, the number of plugs 34b needs to be two or more. In the first preferred embodiment, three plugs 34b are used as an example, but the number of plugs 34b can be adjusted according to different needs. Furthermore, a third depth D3 exists between one end of each plug 34 and the upper surface of the semiconductor substrate 10. This third depth D3 must be at least equal to the aforementioned first depth D1, meaning the end of the plug 34b must be at least as deep as the bottom surface of the substrate region 22. In other embodiments, the third depth D3 may be greater than the first depth D1, meaning the end of the plug 34b is deeper than the bottom surface of the substrate region 22. Multiple doped regions 32b are located in the well region 20 below each plug 34b, and each doped region 32b exhibits a first conductivity type. The multiple doped regions 32b do not contact each other.

[0056] A first drain electrode 36a is disposed on the opposite side of the first gate electrode 12a relative to the source electrode 34a, and the first drain electrode 36a contacts the metal silicide 24 on the first drain electrode 14a. A second drain electrode 36b is disposed on the opposite side of the second gate electrode 12b relative to the source electrode 34, and the second drain electrode 36b contacts the metal silicide 24 on the second drain electrode 14b. Neither the first drain electrode 36a nor the second drain electrode 36b penetrates the metal silicide 24 or inserts into the first drain electrode 14a or the second drain electrode 14b. The source electrode 34, the first drain electrode 36a, and the second drain electrode 36b may contain Cu, W, Al, Ti, Ta, TiN, WN, or other conductive materials.

[0057] Figures 3 to 5A illustrate a method for fabricating an LDMOS according to a second preferred embodiment of the present invention. Figure 4A is a side view drawn along tangent DD' in Figure 4. Figure 5A is a side view drawn along tangent EE' in Figure 5. Components having the same position and function in the second preferred embodiment will use the component designations from the first preferred embodiment, and identical parts will not be described again.

[0058] As shown in Figure 3, a method for fabricating a laterally double-diffused metal-oxide-semiconductor field-effect transistor includes providing a semiconductor substrate 10, with a first gate electrode 12a and a second gate electrode 12b disposed on the semiconductor substrate 10. Referring first to Figure 4A, a well region 20 is disposed in the semiconductor substrate 10, and a substrate region 22 is disposed in the well region 20. Referring again to Figure 3, a first drain 14a and a source 16 are located on both sides of the first gate electrode 12a in the semiconductor substrate 10, and the source 16 is located in the semiconductor substrate 10 between the first gate electrode 12a and the second gate electrode 12b. A second drain 14b is disposed on the side of the second gate electrode 12b opposite to the source electrode 16. Next, a metal silicide fabrication process is performed to form a metal silicide 24 covering the source electrode 16, the first drain electrode 14a, and the second drain electrode 14b.

[0059] As shown in Figures 4 and 4A, a dielectric layer 26 is formed to cover the first gate electrode 12a, the second gate electrode 12b, the first drain electrode 14a, the second drain electrode 14b, and the source electrode 16. Then, a first etching process is performed to etch the dielectric layer 26, the metal silicide layer 24, and the semiconductor substrate 10 to form a plurality of vias 28b that penetrate the dielectric layer 26 and the metal silicide layer 24 and are inserted into the source electrode 16. As shown in Figures 5 and 5A, a second etching process is performed to etch the dielectric layer 24 to form a trench 28a. A first drain contact hole 30a and a second drain contact hole 30b are provided. A trench 28a is located in the dielectric layer 26 directly above the source electrode 16, and the trench 28a and multiple vias 28b are connected to form a source contact hole 28. Part of the metal silicide 24 is exposed through the trench 28a. The first drain contact hole 30a and the second drain contact hole 30b are located on the first drain electrode 14a and the second drain electrode 14b, respectively, and the metal silicide 24 is exposed through the first drain contact hole 30a and the second drain contact hole 30b.

[0060] Next, an ion doping process is performed to form a doped region 32b in the well region 20 below each via 28b. Then, referring to FIG5A, a conductive layer is formed to fill the source contact hole 28, the first drain contact hole 30a, and the second drain contact hole 30b. The conductive layer in the source contact hole 28 constitutes a source electrode 34, and the source electrode 34 is connected to the metal silicide 24. The conductive layers in the first drain contact hole 30a and the second drain contact hole 30b respectively constitute a first drain electrode 36a and a second drain electrode 36b. At this point, the LDMOS 200 of the present invention is completed.

[0061] The structure of the LDMOS fabricated using the second preferred embodiment of the present invention will be described below with reference to Figures 2A, 2C, 5, and 5A. Components with the same position and function will use the component designations from the first preferred embodiment, and identical parts will not be repeated. The difference between the LDMOS 200 of the second preferred embodiment and the LDMOS 100 of the first preferred embodiment is that the LDMOS 200 of the second preferred embodiment does not have a metal silicide barrier layer. The positions and materials of the remaining components are the same as in the first preferred embodiment. Therefore, the only difference between the LDMOS 200 and the LDMOS 100 is the side view along tangent EE', which is shown separately in Figure 5A. Other side views, such as the side view along tangent FF', are the same as the side view of the LDMOS 100 along tangent AA' (see Figure 2A), while the side view along tangent GG' is the same as the side view of the LDMOS 100 along tangent CC' (see Figure 2C).

[0062] The source electrode 34 of the LDMOS 200 also includes a source contact region 34a and multiple plugs 34b, and the multiple plugs 34b are connected to the source contact region 34a. Each plug 34b extends and inserts into the semiconductor substrate 10 located at the source 16. In detail, because the LDMOS 200 does not have a metal silicide barrier layer, each plug 28b penetrates the metal silicide 24 and inserts into the source 16. The source contact region 34a is completely located on the metal silicide 24. That is to say, the metal silicide 24 is located between the source contact region 34a and the upper surface of the semiconductor substrate 10.

[0063] To increase the drain current in the linear region of an LDMOS transistor, the substrate is typically placed at a shallow depth. However, this can lead to charge accumulation on the semiconductor substrate, causing leakage current. This invention specifically inserts a portion of the source electrode into the source and extends it to the depth of contact with the substrate, thus avoiding leakage current. Furthermore, because only a few pins of the source electrode are inserted into the source, the drain current in the linear region is not reduced.

[0064] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention should be included within the scope of the present invention.

Claims

1. A laterally double-diffused metal-oxide-semiconductor field-effect transistor, characterized in that, It includes: a semiconductor substrate; a well region disposed in the semiconductor substrate; and a body region disposed in the well region. A first gate electrode is disposed on the semiconductor substrate; a source electrode is disposed on one side of the first gate electrode, wherein the source electrode is formed by filling a source contact hole with a conductive layer, wherein the source contact hole includes a trench and a plurality of vias, the plurality of vias are connected to the trench, the plurality of vias are inserted into the semiconductor substrate, and the trench is located only on the semiconductor substrate, the conductive layer in the trench forms a source contact region, and the conductive layer in the plurality of vias forms a plurality of plugs; And a first drain electrode, disposed on the other side of the first gate electrode opposite to the source electrode.

2. The laterally double-diffused metal-oxide-semiconductor field-effect transistor of claim 1, wherein the source contact region is completely disposed on the upper surface of the semiconductor substrate.

3. The laterally double-diffused metal-oxide-semiconductor field-effect transistor of claim 1, further comprising: a second gate electrode disposed on the semiconductor substrate, wherein the source electrode is located between the second gate electrode and the first gate electrode; and a second drain electrode disposed on the other side of the second gate electrode opposite to the source electrode.

4. The laterally double-diffused metal-oxide-semiconductor field-effect transistor of claim 1, wherein there is a first depth between the bottom surface of the substrate region and the upper surface of the semiconductor substrate, and a second depth between the bottom surface of the well region and the upper surface of the semiconductor substrate, the second depth being greater than the first depth.

5. The laterally double-diffused metal-oxide-semiconductor field-effect transistor of claim 4, wherein a third depth is provided between the end of each plug and the upper surface of the semiconductor substrate, the third depth being greater than the first depth.

6. The laterally double-diffused metal-oxide-semiconductor field-effect transistor of claim 4, wherein a third depth is provided between the end of each plug and the upper surface of the semiconductor substrate, the third depth being equal to the first depth.

7. The laterally double-diffused metal-oxide-semiconductor field-effect transistor of claim 1, further comprising a metal silicide disposed between the source contact region and the upper surface of the semiconductor substrate.

8. The laterally double-diffused metal-oxide-semiconductor field-effect transistor of claim 1, wherein the semiconductor substrate is a first conductivity type, the well region is a second conductivity type, the substrate region is a first conductivity type, and the first conductivity type and the second conductivity type are different.

9. The laterally double-diffused metal-oxide-semiconductor field-effect transistor of claim 8, further comprising a plurality of doped regions located in the well region below each of the plugs, wherein the plurality of doped regions are of a first conductivity type.

10. A method for fabricating a laterally double-diffused metal-oxide-semiconductor field-effect transistor, comprising: providing a semiconductor substrate, wherein a well region is disposed in the semiconductor substrate, a body region is disposed in the well region, a gate electrode is disposed on the semiconductor substrate, and a drain and a source electrode are located in the semiconductor substrate on both sides of the gate electrode; forming a metal silicide barrier layer covering the source electrode, wherein the metal silicide barrier layer includes a plurality of elongated contours; forming a dielectric layer covering the semiconductor substrate; etching the dielectric layer and the metal silicide barrier layer to form a source contact hole located directly above the source electrode, wherein the source contact hole includes a trench and a plurality of vias, the plurality of vias being connected to the trench, the plurality of vias penetrating the metal silicide barrier layer and inserting into the source electrode, the trench being located only in the dielectric layer; and forming a conductive layer filling the source contact hole to form a source electrode.

11. The method for fabricating a laterally double-diffused metal-oxide-semiconductor field-effect transistor as described in claim 10, wherein the source electrode includes a source contact region and a plurality of vias connected to the source contact region, each via being located in a via, and the source contact region being located in the trench.

12. The method for fabricating a laterally double-diffused metal-oxide-semiconductor field-effect transistor as claimed in claim 11, wherein there is a first depth between the bottom surface of the substrate region and the upper surface of the semiconductor substrate, and a second depth between the bottom surface of the well region and the upper surface of the semiconductor substrate, the second depth being greater than the first depth.

13. The method for fabricating a laterally double-diffused metal-oxide-semiconductor field-effect transistor as claimed in claim 12, wherein a third depth is provided between the end of each plug and the upper surface of the semiconductor substrate, the third depth being greater than the first depth.

14. The method for fabricating a laterally double-diffused metal-oxide-semiconductor field-effect transistor as claimed in claim 12, wherein a third depth is provided between the end of each plug and the upper surface of the semiconductor substrate, the third depth being equal to the first depth.

15. A method for fabricating a laterally double-diffused metal-oxide-semiconductor field-effect transistor, comprising: providing a semiconductor substrate, wherein a well region is disposed in the semiconductor substrate, a substrate region is disposed in the well region, a gate electrode is disposed on the semiconductor substrate, and a drain and a source electrode are located in the semiconductor substrate on both sides of the gate electrode; A metal silicide fabrication process is performed to form a metal silicide covering the source and drain electrodes; a dielectric layer is formed to cover the gate electrode, drain electrode, and source electrode. A first etching process is performed to etch the dielectric layer, the metal silicide, and the semiconductor substrate to form multiple vias that penetrate the metal silicide and insert into the source electrode. A second etching process is performed to etch the dielectric layer to form a trench in the dielectric layer directly above the source electrode, wherein the trench and the plurality of vias are connected to form a source electrode contact hole. A conductive layer is formed to fill the source contact hole to form a source electrode, and the source electrode is connected to the metal silicide.

16. The method for fabricating a laterally double-diffused metal-oxide-semiconductor field-effect transistor as described in claim 15, wherein the source electrode includes a source contact region and a plurality of vias connected to the source contact region, each via being located in a via, and the source contact region being located in the trench.

17. The method for fabricating a laterally double-diffused metal-oxide-semiconductor field-effect transistor as described in claim 16, wherein a first depth is formed between the bottom surface of the substrate region and the upper surface of the semiconductor substrate, and a second depth is formed between the bottom surface of the well region and the upper surface of the semiconductor substrate, the second depth being greater than the first depth.

18. The method for fabricating a laterally double-diffused metal-oxide-semiconductor field-effect transistor as claimed in claim 17, wherein a third depth is provided between the end of each plug and the upper surface of the semiconductor substrate, the third depth being greater than the first depth.

19. The method for fabricating a laterally double-diffused metal-oxide-semiconductor field-effect transistor as claimed in claim 17, wherein a third depth is provided between the end of each plug and the upper surface of the semiconductor substrate, the third depth being equal to the first depth.

20. The method for fabricating a laterally double-diffused metal-oxide-semiconductor field-effect transistor as described in claim 17, further comprising, after forming the plurality of vias, forming a plurality of doped regions located below each of the vias.

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