Non-volatile memory device

Abstract

Embodiments of the present application relate to a nonvolatile memory device. The present application addresses the problem of providing a nonvolatile memory device capable of high precision. The nonvolatile memory device of the embodiments has a plurality of transistors each being of a field effect type and having a gate electrode. The gate electrode includes a tunnel insulating film, a first collector film, an ion conductor film, a first electrode film, a second electrode film, and a second collector film. The tunnel insulating film covers a channel region. The first collector film is disposed on the opposite side of the channel region with respect to the tunnel insulating film. The ion conductor film is disposed between the tunnel insulating film and the first collector film. The first electrode film is disposed between the tunnel insulating film and the ion conductor film. The first electrode film is in contact with the ion conductor film. The second electrode film is disposed between the ion conductor film and the first collector film. The second electrode film is in contact with the ion conductor film. The second collector film is disposed between the tunnel insulating film and the second electrode film.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to a nonvolatile memory device. BACKGROUND

[0002] A deep learning technique using a neural network is known. In addition, a technique of performing deep learning using dedicated hardware is also under study. In addition, a neuromorphic neural network, that is, a brain-type neural network that imitates a human brain is known. The brain-type neural network is a neural network that imitates a human brain that operates with low power consumption and is highly resistant to errors. SUMMARY

[0003] The present application has been made to solve the problem of providing a nonvolatile memory device that can be highly accurate.

[0004] The nonvolatile memory device of the embodiment has a plurality of transistors each being of a field effect type and having a gate electrode. The gate electrode includes a tunnel insulating film, a first collector film, an ion conductor film, a first electrode film, a second electrode film, and a second collector film. The tunnel insulating film covers a channel region. The first collector film is disposed on the opposite side of the channel region with respect to the tunnel insulating film. The ion conductor film is disposed between the tunnel insulating film and the first collector film. The first electrode film is disposed between the tunnel insulating film and the ion conductor film. The first electrode film is in contact with the ion conductor film. The second electrode film is disposed between the ion conductor film and the first collector film. The second electrode film is in contact with the ion conductor film. The second collector film is disposed between the tunnel insulating film and the second electrode film.

[0005] According to the nonvolatile memory device of the above-described structure, it is possible to achieve high accuracy. BRIEF DESCRIPTION OF DRAWINGS

[0006] Figure 1 FIG. 1 is a diagram showing a transistor in the first embodiment.

[0007] Figure 2 FIG. 2 is a diagram showing a storage characteristic of analog information.

[0008] Figure 3A FIG. 3 is a diagram showing writing (discharging) to a transistor.

[0009] Figure 3B FIG. 4 is a diagram showing erasing (charging) to a transistor.

[0010] Figure 4A FIG. 5 is a diagram showing writing to a dual capacitor type transistor.

[0011] Figure 4B FIG. 6 is a diagram showing erasing to a dual capacitor type transistor.

[0012] Figure 5A is a diagram showing circuit connection to a transistor.

[0013] Figure 5B is a diagram showing a circuit symbol of a transistor.

[0014] Figure 6 is a diagram showing a readout characteristic of analog information.

[0015] Figure 7A is a diagram showing a manufacturing method of a nonvolatile storage device.

[0016] Figure 7B is a diagram showing a manufacturing method of a nonvolatile storage device.

[0017] Figure 7C is a diagram showing a manufacturing method of a nonvolatile storage device.

[0018] Figure 8A is a diagram showing a manufacturing method of a nonvolatile storage device.

[0019] Figure 8B is a diagram showing a manufacturing method of a nonvolatile storage device.

[0020] Figure 8C is a diagram showing a manufacturing method of a nonvolatile storage device.

[0021] Figure 9A is a diagram showing a manufacturing method of a nonvolatile storage device.

[0022] Figure 9B is a diagram showing a manufacturing method of a nonvolatile storage device.

[0023] Figure 9C is a diagram showing a manufacturing method of a nonvolatile storage device.

[0024] Figure 9D is a diagram showing a manufacturing method of a nonvolatile storage device.

[0025] Figure 10 is a diagram showing a transistor in a modification example of the first embodiment.

[0026] Figure 11 is a diagram showing a transistor in the second embodiment.

[0027] Figure 12A is a diagram showing a manufacturing method of a nonvolatile storage device in the third embodiment.

[0028] Figure 12B is a diagram showing a manufacturing method of a nonvolatile storage device.

[0029] Figure 12C is a view showing a manufacturing method of a nonvolatile storage device.

[0030] Figure 12D is a view showing a manufacturing method of a nonvolatile storage device.

[0031] Figure 13A is a view showing a manufacturing method of a nonvolatile storage device.

[0032] Figure 13B is a view showing a manufacturing method of a nonvolatile storage device.

[0033] Figure 13C is a view showing a manufacturing method of a nonvolatile storage device.

[0034] Figure 13D is a view showing a manufacturing method of a nonvolatile storage device.

[0035] Figure 14A is a view showing a manufacturing method of a nonvolatile storage device.

[0036] Figure 14B is a view showing a manufacturing method of a nonvolatile storage device.

[0037] Figure 14C is a view showing a manufacturing method of a nonvolatile storage device.

[0038] Figure 14D is a view showing a manufacturing method of a nonvolatile storage device.

[0039] Figure 15A is a view showing a manufacturing method of a nonvolatile storage device.

[0040] Figure 15B is a view showing a manufacturing method of a nonvolatile storage device.

[0041] Figure 15C is a view showing a manufacturing method of a nonvolatile storage device.

[0042] Figure 15D is a view showing a manufacturing method of a nonvolatile storage device.

[0043] Figure 16 is a view showing a transistor in the fourth embodiment.

[0044] Figure 17 is a cross-sectional view of a nonvolatile storage device in the fifth embodiment.

[0045] Figure 18 is a circuit diagram of a nonvolatile storage device.

[0046] Figure 19is a graph showing characteristics of a Schottky barrier diode.

[0047] Figure 20 is a graph showing a nonvolatile storage device of the sixth embodiment;

[0048] Figure 21 is a graph showing a synapse device.

[0049] Figure 22 is a circuit diagram showing a synapse weight device and a synaptic transmission device.

[0050] Figure 23 is a circuit diagram showing a nonvolatile storage device of the seventh embodiment;

[0051] Figure 24 is a circuit diagram showing a nonvolatile storage device of the eighth embodiment;

[0052] Explanation of Reference Numerals

[0053] 1, 201, 301, 401, 501, 501-1, 501-2, 801, 801(0,0) to 801(4,4) transistor

[0054] 2, 302, 502 source electrode

[0055] 3, 303, 503 drain electrode

[0056] 4, 204, 304, 404, 504, 504-1, 504-2 gate electrode

[0057] 5, 5i, 305, 305i tunnel insulating film

[0058] 6, 6i, 306 electrode film

[0059] 7, 7i, 307 ion conductor film

[0060] 8, 8i, 308 electrode film

[0061] 9, 9i, 309 collector film

[0062] 10 well region

[0063] 10a, 510a channel region

[0064] 13, 13i, 313 collector film

[0065] 71 weight storage element

[0066] 100, 200, 300, 400, 500, 600, 700, 800 nonvolatile storage device

[0067] 213 conductive film

[0068] 690 neural network

[0069] 720, 820 arithmetic system DETAILED DESCRIPTION

[0070] Hereinafter, an embodiment of a nonvolatile memory device of the present application will be described in detail with reference to the drawings.

[0071] (First Embodiment)

[0072] The nonvolatile memory device of the present embodiment can nonvolatilely store analog information, and can be applied to a neural network.

[0073] A deep learning technique using a neural network is known. In addition, a technique of performing deep learning using dedicated hardware is also under study. In addition, a neuromorphic neural network, that is, a brain-type neural network that imitates a human brain is known. The brain-type neural network is a neural network that imitates a human brain that operates with low power consumption and is highly resistant to errors.

[0074] In each unit included in the neural network, a product-sum operation (multiplication and accumulation) is performed. That is, in each unit, a plurality of input signals received from a unit of a previous stage are each multiplied by a coefficient, and the plurality of input signals multiplied by the coefficient are added. Further, in each unit, the value thus calculated is supplied to an activation function. Then, in each unit, an output value of the activation function is output.

[0075] However, a neural network device implemented with hardware preferably has a plurality of such units. Therefore, in the case where a neural network is implemented by hardware, it is desirable to implement the operation processing in each unit by a simple structure. In particular, a memory that stores a coefficient is desired to be a long-term and high-precision storage device.

[0076] In the field of brain-type neural networks, as a memory for synapses, structures of various nonvolatile memory devices that nonvolatilely store analog information, starting with ReRAM, have been proposed. For example, as nonvolatile memory devices, ReRAM, FeRAM, PCRAM, and the like are cited. These nonvolatile memory devices have a plurality of transistors, but have technical problems to be solved, such as a large variation in characteristics between the plurality of transistors, low storage precision, and large power consumption.

[0077] Therefore, in the present embodiment, each transistor in the nonvolatile memory device is configured in a field effect type, and a layer structure of a thin film 2-cell is included in a gate electrode thereof, thereby achieving high precision and low power consumption of the nonvolatile memory device.

[0078] Specifically, the nonvolatile memory device has a plurality of transistors each of which is configured of a field effect. In a gate electrode of the transistor, a layer structure (cell configuration) of a thin film 2-cell which is comparable to an all-solid battery is included. In the gate electrode, a plurality of films are laminated, and between a tunnel insulating film and a first collector film in a lamination direction, a second collector film, a first electrode film, an ion conductor film, and a second electrode film are included. The tunnel insulating film is disposed on a substrate. The first electrode film is disposed between the tunnel insulating film and the ion conductor film in the lamination direction, and contacts the ion conductor film. The second electrode film is disposed between the ion conductor film and the first collector film in the lamination direction, and contacts the ion conductor film. The second collector film is disposed between the tunnel insulating film and the second electrode film in the lamination direction. In the transistor, according to the case where electric charge is given and taken to and from the first electrode film from the substrate via the tunnel insulating film and the second collector film, ions move between the first electrode film and the second electrode film via the ion conductor film. The electromotive force of the thin film 2-cell varies according to the amount of the moving ions. Thus, the transistor can store continuous analog information using the cell electromotive force, and can express a synaptic weight with the analog information, and thus can express the synaptic weight with high precision. In addition, the transistor does not include a double capacitor structure in the gate electrode, and writing of information can be performed with a small voltage / current, and thus power consumption can be easily reduced. Thus, the nonvolatile memory device can be made highly precise, and low power consumption can be achieved.

[0079] In addition, the transistor can store continuous analog information using the cell electromotive force, and thus can reduce variation in characteristics, and can achieve sufficient storage time. In addition, readout of the analog information from the transistor is performed according to detection of an on-resistance corresponding to a drain current, and thus a nonvolatile memory device which is compatible with many neural network circuits using ReRAM can be provided.

[0080] The nonvolatile memory device 100 has, for example, a transistor 1 which can store analog information, and a control circuit (not shown) which controls the transistor 1. The transistor 1 can be configured as shown in FIG. 1. Figure 1 Figure 1 is a view showing the transistor 1.

[0081] The transistor 1 is a field effect transistor, and includes a source electrode 2, a drain electrode 3, and a gate electrode 4. For example, the source electrode 2 and the drain electrode 3 are disposed near a surface inside a substrate SB, and the gate electrode 4 is disposed on the substrate SB. An interlayer insulating film is disposed around the gate electrode 4 above the substrate SB, but in FIG. 1, the interlayer insulating film is omitted for simplicity of illustration. Figure 1

[0082] ​​The source electrode 2 and the gate electrode 4 are configured as semiconductor regions of a first conductivity type, and can be configured as semiconductor regions disposed near the surface of the substrate SB. The source electrode 2 and the gate electrode 4 are separated from each other with the well region 10 in the substrate SB interposed therebetween. The well region 10 is configured as a semiconductor region of a second conductivity type. The second conductivity type is the opposite conductivity type of the first conductivity type. The source electrode 2 and the drain electrode 3 contain impurities of the first conductivity type, and the well region 10 contains impurities of the second conductivity type. The concentration of the impurities of the first conductivity type in the source electrode 2 and the drain electrode 3 is higher than the concentration of the impurities of the second conductivity type in the well region 10. In the case where the first conductivity type is n-type, the impurities of the first conductivity type can be phosphorus, arsenic, or the like, which is a donor. In the case where the second conductivity type is p-type, the impurities of the second conductivity type can be boron or the like, which is an accepter.

[0083] The region between the source electrode 2 and the gate electrode 4 in the well region 10 in the direction along the surface of the substrate SB constitutes a channel region 10a. The channel region 10a is a region in which a channel should be formed when a voltage is applied to the gate electrode 4 and / or the well region 10.

[0084] The gate electrode 4 is disposed on the substrate SB at a position between the source electrode 2 and the drain electrode 3 in the planar direction, that is, mainly at a position covering the channel region 10a. The gate electrode 4 can also be configured to have a planar-direction processing dimension of about 100 nm. The gate electrode 4 is configured as a laminated film in which a plurality of films are laminated. For example, the gate electrode 4 is sequentially laminated with a tunnel insulating film 5, a collector film 13, an electrode film 6, an ion conductor film 7, an electrode film 8, and a collector film 9 from the substrate SB side.

[0085] The tunnel insulating film 5 is disposed at the most substrate-SB-side in the gate electrode 4, and covers the channel region 10a. In addition, in the present specification, "covering" is provided to include not only the case of covering entirely, but also the case of covering partially. The tunnel insulating film 5 is disposed between the substrate SB and the electrode film 6 in the lamination direction. The tunnel insulating film 5 can be formed of an insulating film such as a silicon oxide film. In the case where the tunnel insulating film 5 is formed of silicon oxide, the thickness thereof can also be configured to be about 8 nm. In the case where the tunnel insulating film 5 is formed of a film of another insulating material, the film thickness can also be configured to be about 8 nm in terms of the film thickness of a silicon oxide film. Thereby, it is possible to ensure the non-volatility of the electrons that should be accumulated in the electrode film 6.

[0086] The collector film 9 is disposed on the opposite side of the substrate SB with respect to the battery configuration BST. The collector film 9 can function as a control electrode to which a gate voltage is supplied. The collector film 9 can be formed of a material in which a conductive substance is a main component. The collector film 9 can be formed of an Au film, or a laminated film of Au / Ti.

[0087] The current collector film 13 is disposed on the substrate SB side with respect to the battery structure BST. The current collector film 13 can be formed of a material in which a conductive substance is a main component. The current collector film 9 can be formed of a metal such as Pt, Au, Li, or a nonmetal such as carbon, a conductive substance. The current collector film 9 can be formed of an Au film or a laminated film of Au / Ti.

[0088] Among the plurality of films laminated in the gate electrode 4, the electrode film 6, the ion conductor film 7, and the electrode film 8 function as a positive electrode, a solid electrolyte, and a negative electrode, respectively, of a full solid type secondary battery. That is, the electrode film (first electrode film) 6 functions as a positive electrode with respect to the ion conductor film 7. The electrode film (second electrode film) 8 functions as a negative electrode with respect to the ion conductor film 7. The films laminated with the electrode film 6, the ion conductor film 7, and the electrode film 8 constitute a battery structure of a positive electrode / solid electrolyte / negative electrode. The battery structure adopts, for example, a structure of a lithium battery.

[0089] The electrode film 6 is disposed between the tunnel insulating film 5 and the current collector film 9 in the laminating direction, and is disposed between the tunnel insulating film 5 and the ion conductor film 7 in the laminating direction. The electrode film 6 is in contact with a surface of the ion conductor film 7 on the substrate SB side. The electrode film 6 is formed of a material containing an ion that is supposed to be conducted through the ion conductor film 7, and, for example, in a case where the ion that is supposed to be conducted through the ion conductor film 7 is a lithium ion Li+, the electrode film 6 can be formed of Li 1-x CoO2. The thickness of the electrode film 6 can be about 1 nm. x is a composition parameter.

[0090] The electrode film 8 is disposed between the tunnel insulating film 5 and the current collector film 9 in the laminating direction, and is disposed between the ion conductor film 7 and the current collector film 9 in the laminating direction. The electrode film 8 is in contact with a surface of the ion conductor film 7 on the side opposite to the substrate SB. The electrode film 8 is formed of a material containing an ion that is supposed to be conducted through the ion conductor film 7, and, for example, in a case where the ion that is supposed to be conducted through the ion conductor film 7 is a lithium ion Li+, the electrode film 8 can be formed of Li x TiO2. The thickness of the electrode film 8 can be about 1 nm. x is a composition parameter, and is the same as the composition parameter x of the electrode film 6. That is, if Li+ moves from the electrode film 6 to the electrode film 8, the value of x increases in correspondence therewith. If Li+ moves from the electrode film 8 to the electrode film 6, the value of x decreases in correspondence therewith.

[0091] The ion conductor film 7 is disposed between the tunnel insulating film 5 and the current collector film 9 in the stacking direction, and is disposed between the electrode film 6 and the electrode film 8. The ion conductor film 7 is formed of a solid electrolyte capable of conducting the ion to be conducted, and can be formed of Li3PO4 in the case where the ion to be conducted is a lithium ion Li+. The thickness of the ion conductor film 7 can be about 20 nm. The ion conductor film 7 is a conductor with respect to the ion to be conducted, but is an insulator with respect to an electron. Thus, in the case where an electron is held from the substrate SB to the electrode film 6 via the tunnel insulating film 5, the electrode film 6 can nonvolatilely hold the electron.

[0092] In the transistor 1, by making the film thickness of the electrode film 6 and the film thickness of the electrode film 8 of the battery structure (electrode film 6 / ion conductor film 7 / electrode film 8) included in the gate electrode 4 thin, the amount of ion movement between the electrode film 6 and the electrode film 8 can be reduced for each unit gate voltage. For example, as shown in FIG. 6, the electrode film 6 is thinner than the ion conductor film 7, and the electrode film 8 is thinner than the ion conductor film 7. Thus, the change in the electromotive force of the battery can be reduced, and the analog information to be written can be made highly accurate. Figure 1

[0093] For example, in the case where the electrode film 6 is 1 nm (volume: 100 nm x 100 nm x 1 nm = 1 x 10 -17 cm 3 ) thick and is formed of Li 1-x CoO2, the molar volume of Li 1-x CoO2is 6.5 cm 3 Thus, the number of moles of the electrode film 6 is 1.54 x 10 -18 moles. In the case where the storage content is rewritten by a current pulse of a current value of 1.5 pA and a pulse width of 200 μs, the composition change Δχ of the electrode film 6 and the electromotive force change ΔV of the assumed Figure 2 characteristics are 0.002 and 0.004 V, respectively, which are extremely small. In order to change the battery voltage by about 0.01 to 0.1 V per one pulse (1.5 pA, 200 μs), the effective film thickness of the electrode film 6 (effective film thickness of the electrode film 8) can be made thin to 0.04 to 0.4 nm.

[0094] ​At this time, in the gate electrode 4 of transistor 1, the current collector film 13 is conductive, so the interface with the electrode film 6 can be used as an equipotential surface, and a contact potential difference can be formed at the interface with the electrode film 6. This contact potential difference can be formed such that the potential of the electrode film 6 is lower than the potential of the current collector film 13 relative to electrons. As a result, the spatial deviation of ion current and tunneling current between the ion conductor film 7 and the electrode film 6 can be reduced, and when electrons are introduced into the current collector film 13, they can be efficiently guided to the electrode film 6.

[0095] In addition, in order to ensure good adhesion between the current collector film 13 formed of metal or the like and the electrode film 6 formed of oxide or compound, for example, a multilayer film of Au / Cr or Au / Ti can be used instead of Au.

[0096] Figure 2 express Figure 1 The diagram illustrates the relationship between the composition parameter x and the electromotive force (EMF) of the secondary battery structure (electrode membrane 6 / ion conductor membrane 7 / electrode membrane 8). When lithium ions (Li+) move from electrode membrane 6 to ion conductor membrane 7 to electrode membrane 8 during charging, the composition parameter x increases, and the EMF increases. Conversely, when lithium ions (Li+) move from electrode membrane 8 to ion conductor membrane 7 to electrode membrane 6 during discharging, the composition parameter x decreases, and the EMF decreases.

[0097] like Figure 2 As shown, transistor 1 can store continuous analog information as the level of the battery electromotive force. The electromotive force of the battery structure, formed by the stacked membranes of electrode film 6, ion conductor film 7, and electrode film 8, changes through charging and discharging.

[0098] For example, transistor 1 performs an accompanying... Figure 3A The battery structure shown illustrates the write operation during the discharge process. Figure 3A The diagram illustrates the discharge of the battery structure (electrode film 6 / ion conductor film 7 / electrode film 8) by current flowing from the gate electrode 4 toward the semiconductor substrate SB. Figure 3A In this process, the planar dimension of the gate electrode 4 can also be configured to be approximately 100 nm. When a thermionic current of 1.5 pA flows through the tunnel insulating film 5, and the electromotive force of the battery is 2 V, the potentials of the current collector film 9 and the electrode film 8 relative to the semiconductor substrate SB are 4 V, and the potentials of the electrode film 6 and the current collector film 13 are 6 V.

[0099] At this point, transistor 1 can also be subjected to the following... Figure 5A The circuit connection is shown. In transistor 1, the source electrode 2 is connected to ground potential, and a specified voltage V is applied to the drain electrode 3. D A gate voltage V is applied to the current collector film 9 in the gate electrode 4.G A bias voltage V WELL . The ground potential, the prescribed voltage V D , the gate voltage V G , the bias voltage V WELL may be generated and supplied by the control circuit, respectively. The circuit symbol of the transistor 1 is expressed in the form of embedding the gate portion of the symbol of the transistor in the symbol of the battery as shown in Figure 5B . At this time, the circuit connection as shown in Figure 5A , if expressed by a symbol, becomes Figure 5B .

[0100] In the discharging operation as shown in Figure 3A , the bias voltage V WELL = 0 V is applied to the well region 10, and a prescribed voltage V G = 4 V is applied between the source electrode 2 and the drain electrode 3 in the state where the bias voltage V D = 4 V is applied to the collector film 9, and electrons are supplied to the channel region 10a. At this time, since the film other than the tunnel insulating film 5 in the gate electrode 4 is substantially a conductor, an electric field sufficient for the electrons to tunnel can be effectively applied to both ends of the tunnel insulating film 5 in the stacking direction. That is, in the transistor 1, for example, the gate voltage of 4 V is applied to the gate electrode 4, the battery construction is discharged by the movement of ions (for example, Li+) from the electrode film 8 to the electrode film 6 via the ion conductor film 7 to the electrode film 6, and the electrons that have tunneled the tunnel insulating film 5 from the channel region 10a are accumulated in the electrode film 6 via the collector film 13, and are written as analog information. At this time, the composition parameter x becomes small, and the electromotive force of the battery construction decreases. In Figure 3A , 4 V is exemplified as the gate voltage, but the gate voltage can be continuously changed around 4 V according to the analog information to be written.

[0101] Here, the film thickness of the electrode film 6 of the battery construction and the film thickness of the electrode film 8 can be made thin. For example, the electrode film 6 can be thinner than the ion conductor film 7, and the electrode film 8 can be thinner than the ion conductor film 7. Thereby, the amount of ion movement between the electrode film 6 and the electrode film 8 can be reduced per unit gate voltage, and the change in the electromotive force of the battery can be reduced. That is, the analog information to be written can be made more accurate.

[0102] In addition, from the standpoint of calling the electrode into which electrons flow an anode and calling the electrode from which electrons are emitted a cathode, in the discharging operation as shown in Figure 3A , the electrode film 8 as the positive electrode is sometimes called a cathode, and the electrode film 6 as the negative electrode is sometimes called an anode. Alternatively, from the standpoint of calling the electrode into which electrons flow during discharging an anode and calling the electrode from which electrons are emitted a cathode, in the discharging operation as shown in Figure 3A , the electrode film 8 as the positive electrode is sometimes called a cathode, and the electrode film 6 as the negative electrode is sometimes called an anode.

[0103] On the other hand, the dual-capacitor transistor 901 used in the flash memory performs, as Figure 4A The write action shown. Figure 4A In the process, the machining dimensions in the planar direction of the gate electrode 904 are... Figure 3A Similarly, it can be configured to be approximately 100 nm. In the gate electrode 904, a tunnel insulating film 905, a charge storage film 911, an interlayer insulating film 912, and a control electrode film 909 are sequentially stacked from the side closest to the substrate SB. The charge storage film 911 can be made of a metal or a conductor such as a semiconductor that has been imparted with conductivity, or it can be composed of a three-layer structure of silicon oxide film / silicon nitride film / silicon oxide film. In the dual capacitor type transistor 901, such as Figure 4A As shown, the gate voltage V under the condition of the same thermionic current flowing through it. G For example, if the thickness of the interlayer insulating film 912 is set to 16 nm, the voltage becomes approximately 20 V. That is, in Figure 4A In the write operation shown, a V is applied to the well region 10. WELL =0V, when a V is applied to the control electrode film 909 G A specified voltage V is applied between the source electrode 2 and the drain electrode 3 at a voltage of 20V. D Electrons are supplied to the channel region 10a. At this time, an interlayer insulating film 912 exists outside the tunnel insulating film 5 in the gate electrode 904, and the gate voltage V G The interlayer insulating film 912 and the tunnel insulating film 5 are divided at both ends in the stacking direction. Therefore, in order to apply an electric field sufficient to cause electron tunneling at both ends of the tunnel insulating film 5 in the stacking direction, a high voltage is applied to the control electrode film 909. That is, in the dual capacitor type transistor 901, for example, a gate voltage V of 20V is applied. G When applied to the gate electrode 4, electrons that have tunneled through the tunnel insulating film 905 from the channel region 10a are stored in the charge storage film 911 and information is written.

[0104] The gate voltage V during discharge of transistor 1 in this embodiment G (For example, about 4V) lower than the gate voltage V during writing of the dual capacitor transistor 901. G (For example, approximately 20V). The reason is that, in transistor 1, in order to confine electrons to the portion of the gate electrode 4 near the channel region 10a, an ion-conducting membrane 7 of a solid electrolyte is used instead of the interlayer insulating membrane 912. As mentioned above, the solid electrolyte is an insulator for electrons, but acts as a conductor with respect to ion current. Furthermore, a battery electromotive force (for example, approximately 2V) is present, causing the gate voltage V to... GThe voltage is reduced. As a result, compared with the dual capacitor type transistor 901, the transistor 1 in this embodiment can accumulate charge from the channel region 10a to the electrode film 6 through the tunnel insulating film 5 at a lower voltage.

[0105] In addition, transistor 1 performs accompanying... Figure 3B The erase action shown is part of the charging process. Figure 3B The diagram illustrates the charging of the battery structure (electrode film 6 / ion conductor film 7 / electrode film 8) by current flowing from the semiconductor substrate SB towards the gate electrode 4. Figure 3B In this case, the planar dimension of the gate electrode 4 can also be configured to be approximately 100 nm. When a 1.5 pA thermionic current flows through the tunnel insulating film 5, and the electromotive force of the battery is 2 V, the potential difference between the current collector film 9 and the electrode film 8 relative to the semiconductor substrate SB is (-4 V) - 4 V = -8 V, and the potential difference between the electrode film 6 and the current collector film 13 is (-2 V) - 4 V = -6 V. At this time, it is also possible to perform... Figure 5A The circuit connection is shown.

[0106] exist Figure 3B In the charging operation shown, a V is applied to the trap region 10. WELL =4V, a voltage of V was applied to the current collector film 9. G When the voltage is -4V, a specified voltage V is applied between the source electrode 2 and the drain electrode 3. D This allows the transistor to become capable of ejecting electrons from the channel region 10a. Since the film in the gate electrode 4, except for the tunnel insulating film 5, is essentially a conductor, an electric field sufficient to allow electron tunneling can be effectively applied across the tunnel insulating film 5 in the stacking direction. That is, in the transistor 1, for example, a gate voltage V is applied to the gate electrode 4. G = -4V, apply V to substrate SB WELL = 4V. Conversely, an erase voltage of 4V - (-4V) = 8V can be considered to be applied between the gate electrode 4 and the substrate SB. Thus, ions (e.g., Li+) move from the electrode film 6 to the electrode film 8 via the ion conductor film 7 to charge the battery structure, and electrons tunneling from the electrode film 6 through the tunnel insulating film 5 via the current collector film 13 are discharged into the channel region 10a, at least partially erasing the analog information. At this time, the composition parameter x increases, and the electromotive force increases. Figure 3B In the example, -4V is shown as the gate voltage, but the gate voltage can be continuously changed before and after -4V according to the analog information to be erased.

[0107] Furthermore, from the perspective of calling the electrode into which electrons flow in the anode and the electrode into which electrons are emitted the cathode, in Figure 3BIn the charging operation shown, sometimes the electrode film 8, which serves as the positive electrode, is called the anode, and the electrode film 6, which serves as the negative electrode, is called the cathode. Alternatively, from the perspective of fixedly calling the electrode into which electrons flow during discharge the anode, and fixedly calling the electrode from which electrons are released the cathode, in... Figure 3B In the charging operation shown, the electrode film 8, which serves as the positive electrode, is sometimes referred to as the cathode, and the electrode film 6, which serves as the negative electrode, is referred to as the anode.

[0108] On the other hand, the dual-capacitor transistor 901 used in the flash memory performs, as Figure 4B The erasure action is shown. In Figure 4B In the process, the machining dimensions in the planar direction of the gate electrode 904 are... Figure 3B Similarly, it can also be configured to be approximately 100nm. In the dual-capacitor transistor 901, such as... Figure 4B As shown, the erasure voltage under the same thermionic current is approximately 20V, for example, if the thickness of the interlayer insulating film 912 is set to 16nm. That is, in Figure 4B In the eraser operation shown, a V is applied to the trap region 10. WELL =20V, a voltage of V was applied to the control electrode film 909. G When the voltage is 0V, a specified voltage V is applied between the source electrode 2 and the drain electrode 3. D This allows electrons to be discharged from the channel region 10a. At this time, in the gate electrode 904, an interlayer insulating film 912 exists outside the tunnel insulating film 905, and the gate voltage V... G The voltage is divided between the two ends of the interlayer insulating film 912 and the two ends of the tunnel insulating film 905 in the stacking direction. Therefore, in order to apply an electric field sufficient to tunnel electrons through the tunnel insulating film 905 in the stacking direction, a high voltage is applied to the substrate SB. That is, in the dual-capacitor type transistor 901, for example, by applying an erase voltage of 20V to the substrate SB, electrons that have tunneled through the tunnel insulating film 905 from the charge storage film 911 are discharged into the channel region 10a, and the information is erased along with it.

[0109] The erase voltage during charging of transistor 1 in this embodiment (e.g., about 8V) is lower than the erase voltage during writing of dual-capacitor transistor 901 (e.g., about 20V). The reason for this is that in transistor 1, an ion-conducting membrane 7 of a solid electrolyte is used instead of the interlayer insulating membrane 912 to confine electrons near the channel region 10a. As described above, the solid electrolyte is an insulator for electrons but acts as a conductor with respect to ion current. Furthermore, the presence of a battery (electromotive force of about 2V) lowers the gate voltage. Therefore, compared to dual-capacitor transistor 901, in transistor 1 of this embodiment, charge extraction from the electrode membrane 6 via the current collector membrane 13 and through the tunnel insulating membrane 5 to the channel region 10a can be performed at a lower voltage.

[0110] In addition, transistor 1 performs as follows Figure 6 The readout operation is shown. The readout operation allows observation of the on-resistance of transistor 1. The on-resistance of transistor 1 can be observed by applying a gate voltage V to the collector film 9. G In this state, the control circuit (not shown) detects the cell current and other parameters by detecting the applied voltage between the source electrode 2 and the drain electrode 3.

[0111] At this point, it is possible to perform, such as Figure 5A The circuit connection shown can also be a gate voltage V G A lower voltage than that required to turn on transistor 1 during writing (e.g., around 1.5V). The specified voltage V D It can also be used to charge the data line to detect the cell current. The control circuit can detect the level of the cell current by the change in the data line potential caused by the cell current from the charging potential. The control circuit can determine the on-resistance of transistor 1 based on the detected level of the cell current.

[0112] For example, if the on-resistance of transistor 1 is set to R on The gate voltage applied to the current collector film 9 is set to V. G Set the threshold voltage of transistor 1 to V. T Then the on-resistance R on Compared to V G -V T Changes such as Figure 6 The single-dotted line is shown in the diagram. This change is approximately passed through the linear region of transistor 1's operation.

[0113] 1 / R on =(W / L)μC' ox (V G -V T (Equation 1)

[0114] Let it be represented by. On-resistance R on It can be estimated according to Equation 1. In Equation 1, W represents the gate width (e.g., 100 nm). L represents the gate length (e.g., 100 nm). μ represents the electron mobility in the channel region (e.g., 100 cm⁻¹). 2 / Vs). C' ox This represents the gate capacitance per unit area (e.g., 5 × 10⁻⁶). -3 F / m 2 V G This indicates that the gate voltage equals the battery electromotive force (e.g., 1.5–2.5V). T This represents the threshold voltage (e.g., 1V) of transistor 1.

[0115] In Figure 6 which the on-resistance R T = 1 V, V G -V T = 0.5 ~ 1.5 V, the case where the battery configuration is charged and discharged, the relationship with the gate voltage V on and the on-resistance R G . V G -V T = 0.5 V corresponds to the battery configuration charge level 0%, V G -V T = 1.0 V corresponds to the battery configuration charge level 50%, V G -V T = 1.5 V corresponds to the battery configuration charge level 100%.

[0116] For example, set to the composition parameter x = x 1.0 , V G -V T = 1.0 V, the battery configuration is charged 50% state. At this time, the control circuit can be applied to the collector film 9 in the state of the gate voltage V G between the source electrode 2 and the drain electrode 3 to read out the unit current applied to the detection, the on-resistance R on ≈ 21 kΩ. The control circuit can be recovered according to the on-resistance R on ≈ 21 kΩ corresponding to the value of the charge rate 50%.

[0117] The ion moves from the electrode film 8 to the electrode film 6 via the ion conductor film 7 to discharge, the composition parameter is x = x 0.5 (<x 1.0 ), V G -V T = 0.5 V, the battery configuration charge level becomes 0%. At this time, the control circuit can be applied to the collector film 9 in the state of the gate voltage V G between the source electrode 2 and the drain electrode 3 to read out the unit current applied to the detection, the on-resistance R on ≈ 39 kΩ. The control circuit can be recovered according to the on-resistance R on ≒ 39 kΩ corresponding to the value of the charge rate 0%.

[0118] When the ion moves from the electrode film 6 to the electrode film 8 via the ion conductor film 7 to charge, the composition parameter is x = x 1.5 (>x 1.0 ), V G -V T= 1.5 V, the charge level of the battery structure becomes 100%. At this time, the control circuit can detect the cell current read out by applying a prescribed voltage between the source electrode 2 and the drain electrode 3 in a state where the gate voltage V G is applied to the collector film 9, and calculate the on-resistance R on ≈ 13 kΩ. The control circuit can restore the value corresponding to the charge rate 100% based on the on-resistance R on ≈ 13 kΩ.

[0119] In addition, the method of writing and erasing accompanying charging and discharging is not limited to the method of Figure 3A and Figure 3B . By adjusting the prescribed voltage V D , the electrons can be accelerated between the source electrode 2 and the drain electrode 3, and thus the voltage V G applied to the gate electrode 4 can be further reduced. The method of reading out is not limited to the method of Figure 6 . Any one of various characteristics obtained by causing the transistor 1 to operate in a nonlinear region can be used. In addition, in the above-described example, the case where the transistor 1 is an N-type transistor is described, but the transistor 1 can be a P-type transistor.

[0120] In addition, in Figure 1-3B , Figure 5A-6 , a case where SiO2 having a thickness of 8 nm is used as the tunnel insulating film 5 is exemplified, but the thickness of the tunnel insulating film 5 can be appropriately selected within a range of 1 to 100 nm in consideration of the writing voltage, the number of writing times, the storage time, and the like. In addition, MgO, HfO x , AlO x , or the like can be used as the oxide film of the tunnel insulating film 5 within a range of a thickness of 1 to 100 nm.

[0121] In addition, as the ion conductor film 7, a film using a solid electrolyte Li3PO4 having a thickness of 20 nm is exemplified, but the solid electrolyte Li3PO4 can be used within a range of a thickness of 10 to 1000 nm in consideration of the film formation property, the film quality, and the like. The ion conductor film 7 can include any solid electrolyte. As the ion conductor film 7, in addition to the solid electrolyte Li3PO4, among oxide solid electrolytes, a perovskite-type La 0.51 Li 0.34 TiO 2.94 , a NASICON-type Li 1.3 Al 0.3 Ti 1.7 (PO4)3, a garnet-type solid electrolyte Li7La3Zr2O 12 , and an amorphous solid electrolyte Li 2.9 PO3.3 N 0.46 Li (LIPON), etc., can be used in sulfide solid electrolytes in the range of 10–1000 nm thickness. 10 GeP2S 12 Li 3.25 Ge 0.25 P 0.75 S4, etc.

[0122] Additionally, Li, the positive electrode material of a lithium battery, is used as an example of electrode film 6. 1-x The electrode film 6 may contain at least one of the following: a CoO2 membrane, an alkali metal, or an alkaline earth metal. In addition to the illustrated materials, the electrode film 6 may also use Li. 1-x NiO2, Li 1-x CrO2, Li 1-x MnO2, Li 1-x Mn2O4, Li x V2O5, Li x TiS2, Li 1-x FePO4 and other materials.

[0123] Additionally, Li, a negative electrode material used in lithium batteries, is used as an example of electrode film 8. x The electrode film 8 may contain at least one of the following: an electron-ion mixed conductor, an alkali metal, or an alkaline earth metal. In addition to the illustrated materials, the electrode film 8 may also use metallic Li, Li... x Al, Li x NiO, Li x V2O5, Li x TiS2, Li x FePO4, Li 4-x Ti5O 12 Materials, etc.

[0124] Furthermore, when using a magnesium battery structure (electrode membrane 6 / ion conductor membrane 7 / electrode membrane 8), the solid electrolyte MgSc2Se4 can be used as the ion conductor membrane 7. As the electrode membrane 6, Mg, the positive electrode material of a magnesium battery, can be used. 1-x FeSiO4. Mg, the negative electrode material of a magnesium battery, can be used as the electrode film 8. As the current collector film 9, to ensure good adhesion between the metal electrode and the positive and negative electrodes of the oxide / compound, multilayer films such as Au / Cr and Au / Ti can be used instead of Au.

[0125] Next, use Figure 7A-9D Specific processing examples will be explained. Figure 7A-9D This is an example of how transistor 1 is manufactured.

[0126] First, the element separation structure 11 is formed on the substrate SB. The element separation structure 11 can be formed of an STI (Shallow Trench Isolation) type structure. The substrate SB can be formed of a semiconductor such as silicon. In the case of the STI type, a trench is formed on the substrate SB by RIE or the like, and an insulating film such as a silicon oxide film is buried in the trench by a CVD method or the like, whereby the element separation structure 11 can be formed. Thus, the element formation region AA in which the transistor 1 should be formed is ensured between the element separation structures 11 in the substrate SB. Figure 7A

[0127] Next, in the entire element formation region AA, an impurity of a second conductivity type is introduced by an ion implantation method or the like, and a well region 10 is formed. In the case where the second conductivity type is a p type, the impurity of the second conductivity type is an accepter such as boron, and the well region 10 can also be a P type well region. Figure 7B In addition, the well region 10 can also be shared with other transistors 1, other transistors, which are formed adjacently on the same substrate. In this case, an impurity of a first conductivity type is introduced in the entire region in which the well region 10 is common.

[0128] Then, as needed, an impurity for a channel is introduced (for example, ion implantation) to the channel region 10al near the surface in the element formation region AA. Figure 7C In addition, the impurity introduction can not necessarily be performed. Thereafter, annealing is performed by a method such as RTA (Rapid Thermal Anneal) or the like, and the impurities of the well region 10 and the channel region 10al are activated. The impurity for the channel is an impurity of the first conductivity type, and is introduced at a lower concentration than the impurity of the first conductivity type introduced into the source electrode 2, 3 formed later. In the case where the first conductivity type is an n type, the impurity of the first conductivity type can also be a donor such as phosphorus or arsenic.

[0129] Then, in the element formation region AA, a tunnel insulating film 5i, a collector film 13i, an electrode film 6i, an ion conductor film 7i, an electrode film 8i, and a collector film 9i are sequentially formed and laminated. Figure 8A These films can each be a single layer film, or can be a multilayer film. The method of film formation can use a standard semiconductor process method such as CVD or sputtering. The tunnel insulating film 5i can be formed of a material in which silicon oxide is a main component, or can be formed of a material in which another oxide is a main component. The collector film 13i can also be formed of a material in which a conductive substance such as metal or carbon is a main component. The electrode film 6i can also be formed of a material containing an ion that should be conducted (for example, Li 1-x ​CoO2). The ion conductor film 7i can also be formed of a material in which a solid electrolyte (e.g., Li3PO4) capable of conducting ions to be conducted is the main component. The electrode film 8i can also be formed of a material containing a material (e.g., Li x TiO2). The current collector film 9i can also be formed of a material in which a metal or the like is the main component of an electrically conductive substance.

[0130] Above the current collector film 9i, a resist pattern (not shown) selectively covering the region in which the gate electrode 4 is to be formed is formed by photolithography or the like. Using the resist pattern as a mask, the gate electrode 4 is formed by, for example, etching or polishing or the like. Figure 8B In the gate electrode 4, the tunnel insulating film 5, the current collector film 13, the electrode film 6, the ion conductor film 7, the electrode film 8, and the current collector film 9 are stacked in this order from the substrate SB side. The stacked structure of the electrode film 6, the ion conductor film 7, and the electrode film 8 forms a cell structure. If the resist pattern remains on the current collector film 9, it is removed with a chemical liquid such as an acid.

[0131] After the gate electrode 4 is formed, a gate sidewall film 12 can also be formed for the purpose of protecting the side surface of the gate electrode 4 by an oxide or a nitride that is chemically stable. Figure 8C The gate sidewall film 12 can be formed by a standard MOSFET process. For example, after the gate electrode 4 is formed, an insulating film such as an oxide film or a nitride film is formed on the entire surface of the element formation region AA, and anisotropic etching is performed in the direction perpendicular to the surface of the substrate SB. Thus, the insulating film can be processed so as to remain as the gate sidewall film 12 for the side surface of the gate electrode 4.

[0132] Then, the source electrode 2 / drain electrode 3 is formed at a position adjacent to the gate electrode 4 and the gate sidewall film 12 in the well region 10.

[0133] For example, the formation of the source electrode 2 / drain electrode 3 can be performed by introducing an impurity of the first conductivity type into the well region 10 using an ion implantation method or the like with the gate electrode 4 and the gate sidewall film 12 as a mask. Figure 9A In the case where the first conductivity type is n-type, the impurity of the first conductivity type can be a donor such as phosphorus or arsenic. Thereafter, annealing is performed to activate the impurities of the source electrode 2 and the drain electrode 3. The activation can be, for example, a method such as RTA (Rapid Thermal Anneal) or various methods such as microwave annealing in order to suppress the heat load to a minimum.

[0134] Alternatively, the formation of the source electrode 2 and the drain electrode 3 can be performed as follows. The region that should become the source electrode and the drain electrode in the element formation region AA is dug by etching, polishing, or the like, and a source electrode material and a drain electrode material having high conductivity are buried by selective epitaxial growth or the like. Figure 9B

[0135] Alternatively, the formation of the source electrode 2 and the drain electrode 3 can be performed using a silicide process or the like. In the case where the substrate SB is formed of silicon, a metal film that covers the well region 10 and the gate electrode 4 is formed in the element formation region AA, and annealing is performed to form the source electrode 2 and the drain electrode 3 as a metal silicide layer in the well region 10 ( Figure 9C ). Then, the remaining metal is removed with a liquid medicine such as an acid. At this time, if the uppermost collector film 9 of the gate electrode 4 is made of a silicon thin film to which conductivity is imparted, a metal silicide layer 9a is formed in the uppermost portion of the collector film 9, and the collector film 9 can be protected from the liquid medicine such as an acid. After the formation of the metal silicide layer, in order to reduce the contact resistance between the metal silicide layer (the source electrode 2 and the drain electrode 3) and the silicon region (the well region 10), an impurity of the first conductivity type (for example, arsenic, phosphorus, sulfur, or the like, a donor) can be introduced by an ion implantation method or the like, and a segregation layer 2a, 3a is formed at the interface between the metal silicide layer and the silicon region ( Figure 9D ). In this case, the activation of the ions can be performed at a lower temperature than usual. The segregation layer 2a, 3a is disposed at the bottom surface on the substrate SB back surface side of the source electrode 2 and the drain electrode 3 and at the side surface on the gate electrode 4 side.

[0136] Further, regarding the manufacturing method of the transistor 1, the description has been given assuming that the transistor 1 is an N-type transistor, but the transistor 1 can be made into a P-type transistor by replacing the acceptor with a donor, replacing the donor with an acceptor, and switching the film formation order of the electrode film 6i and the electrode film 8i.

[0137] As described above, in the present embodiment, each transistor 1 in the nonvolatile memory device 100 is configured by a field effect type, and a layer structure (electrode film 6 / ion conductor film 7 / electrode film 8) of a thin film 2-cell battery is included in the gate electrode 4. Thus, the transistor 1 can store continuous analog information using the battery electromotive force, and can express the information with high precision. For example, in the case where the nonvolatile memory device 100 is applied to a brain-type neural network, the synaptic weight can be expressed with high precision by storing the analog information of the transistor 1. In addition, the transistor 1 does not include a double capacitor structure in the gate electrode, and the writing of information can be performed with a small voltage / current, so the power consumption can be easily reduced. Thus, the nonvolatile memory device 100 can be made highly precise, and low power consumption can be achieved.

[0138] ​Furthermore, the non-volatile memory device 100 can also be applied to general-purpose memory devices other than brain-like neural networks. The non-volatile memory device 100 can also have a memory cell array in which multiple transistors 1 are arranged in two dimensions as multiple memory cells and peripheral circuitry for controlling the memory cell array.

[0139] Alternatively, the non-volatile storage device 900 can also be as follows: Figure 10 As shown, the stacking order of electrode films 6 and 8 is swapped in the gate electrode 904 of each transistor 901. Figure 10 This diagram illustrates the transistor 901 in a modified example of the first embodiment. The gate electrode 904 is constructed by sequentially stacking a tunnel insulating film 5, a current collector film 13, an electrode film 8, an ion conductor film 7, an electrode film 6, and a current collector film 9 from the substrate SB side. The electrode film 8 functions as the negative electrode of the all-solid-state secondary battery, and the electrode film 6 functions as the positive electrode of the all-solid-state secondary battery, as is the case in the first embodiment. That is, the electrode film (first electrode film) 8 functions as the negative electrode relative to the ion conductor film 7, and the electrode film (second electrode film) 6 functions as the positive electrode relative to the ion conductor film 7. In the gate electrode 904, the battery structure BST' is constructed from the substrate SB side by sequentially stacking a negative electrode / solid electrolyte / positive electrode.

[0140] In this case, the correspondence between the charging / discharging operation of the battery structure BST' and the writing / erasing operation of the transistor 901 is the opposite of that in the first embodiment.

[0141] If a gate voltage (e.g., 4V) for writing is applied to the current collector film 9, ions (e.g., Li+) move from the electrode film 6 to the electrode film 8 via the ion conductor film 7, charging the battery structure. Electrons that tunnel through the tunnel insulating film 5 from the channel region 10a are stored in the electrode film 8 via the current collector film 13, and analog information is written. At this time, the composition parameter x increases, and the electromotive force of the battery structure increases.

[0142] If a trap voltage (e.g., 4V) for erasing is applied to trap region 10 and a gate voltage (e.g., -4V) for erasing is applied to current collector film 9, ions (e.g., Li+) move from electrode film 8 through ion conductor film 7 to electrode film 6, thus discharging the battery structure. Electrons that tunnel through tunnel insulating film 5 from electrode film 8 via current collector film 13 are discharged into channel region 10a, and the analog information is at least partially erased. At this time, the composition parameter x decreases, and the electromotive force decreases.

[0143] Additionally, the readout operation can be considered in relation to the change in the on-resistance of transistor 1. Figure 6 It tends to proceed in a left-right reversal manner. For example, let the constituent parameter be x = x 1.0 V G- V T = 1.0 V, the battery configuration is in a state of being charged by 50%. At this time, ions move from the electrode film 8 to the electrode film 6 via the ion conductor film 7 to perform discharging, and the composition parameter is x = x 0.5 (< x 1.0 ) when V G - V T = 1.5 V, the charge level of the battery configuration becomes 0%. Ions move from the electrode film 6 to the electrode film 8 via the ion conductor film 7 to perform charging, and the composition parameter is x = x 1.5 (> x 1.0 ) when V G - V T = 0.5 V, the charge level of the battery configuration becomes 100%.

[0144] With such a configuration, the transistor 1 can also store continuous analog information using the electromotive force of the battery, and can express the information with high precision.

[0145] (Second Embodiment)

[0146] Next, the nonvolatile memory device of the second embodiment will be described. Hereinafter, the description will be made focusing on the different parts from the first embodiment.

[0147] In the second embodiment, a structure in which the electrode film 206 has both the function of the electrode film and the function of the current collector film in the gate electrode 204 of each transistor 201 is exemplified.

[0148] Specifically, as shown in FIG. 6, the gate electrode 204 of each transistor 1 of the nonvolatile memory device 200 has the electrode film 206 instead of the electrode film 6 and the current collector film 13 (refer to FIG. 5). The region 206a of the electrode film 206 that contacts the ion conductor film 7 functions as the positive electrode in the battery configuration BST, and the region 206b that contacts the tunnel insulating film 5 functions as the current collector for the battery configuration BST. The electrode film 206 can be formed of a material in which Li is a main component, for example. Figure 11 Figure 1 At this time, in the gate electrode 204 of the transistor 201, the region 206b has conductivity, and thus it is possible to make the interface with the region 206a an equipotential surface and to form a contact potential difference at the interface with the region 206a. The contact potential difference can be formed such that the potential of the region 206a is lower than the potential of the region 206b with respect to electrons. Thereby, it is possible to reduce the spatial deviation of the ion current and the tunnel current between the ion conductor film 7 and the region 206a, and in the case where electrons are introduced to the region 206b, it is possible to efficiently guide the electrons to the region 206a.

[0149] At this time, in the gate electrode 204 of the transistor 201, the region 206b has conductivity, and thus it is possible to make the interface with the region 206a an equipotential surface and to form a contact potential difference at the interface with the region 206a. The contact potential difference can be formed such that the potential of the region 206a is lower than the potential of the region 206b with respect to electrons. Thereby, it is possible to reduce the spatial deviation of the ion current and the tunnel current between the ion conductor film 7 and the region 206a, and in the case where electrons are introduced to the region 206b, it is possible to efficiently guide the electrons to the region 206a.

[0150] ​As described above, in the second embodiment, the electrode film 206 functions as both an electrode film and a current collector film in the gate electrode 204 of each transistor 1 of the nonvolatile memory device 200. According to such a structure, the transistor 1 can also store continuous analog information using a battery electromotive force, and can express information with high precision.

[0151] (Third Embodiment)

[0152] Next, the nonvolatile memory device of the third embodiment will be described. Hereinafter, the description will be focused on the points different from the first and second embodiments.

[0153] In the third embodiment, each transistor 301 in the nonvolatile memory device 300 is configured of a thin film transistor structure. In the transistor 301, the source electrode 2, the drain electrode 3, and the well region 10 (see FIG. 1) are configured on the substrate SBl as a source electrode 302, a drain electrode 303, and a semiconductor film 310 which are thinned. Figure 1

[0154] At this time, the manufacturing method of the transistor 301 is as shown in FIGS. 32 to 36, and differs from the first embodiment in the following points. Figure 12A-15D Figure 12A Figure 12C Figure 13A Figure 13C Figure 14A Figure 14C Figure 15A Figure 15C FIGS. 32 to 36 are cross-sectional views showing the manufacturing method of the transistor 301. Figure 12B Figure 12D Figure 13B Figure 13D Figure 14B Figure 14D Figure 15B Figure 15D FIGS. 32 to 36 are cross-sectional views showing the manufacturing method of the transistor 301. Figure 12B Figure 12D Figure 13B Figure 13D Figure 14B Figure 14D Figure 15B Figure 15D FIGS. 32 to 36 are cross-sectional views showing the manufacturing method of the transistor 301. Figure 12A Figure 12C Figure 13A Figure 13C Figure 14A Figure 14C Figure 15A Figure 15C FIGS. 32 to 36 are cross-sectional views showing the manufacturing method of the transistor 301. ​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​

[0155] A current collector film 309i (not shown) is formed on the substrate SB1. The current collector film 309i can be formed from a material primarily composed of metals such as Au. The current collector film 309i is patterned by photolithography into, for example, a roughly rectangular shape when viewed from above. Figure 12A , 12B Here, the surface of substrate SB1 is designed to have low conductivity so that it does not cause electrical interference with other components after the components are formed.

[0156] Next, electrode film 308i, ion conductor film 307i, electrode film 306i, and current collector film 313i (not shown) are sequentially formed and stacked using CVD or sputtering methods. Electrode film 308i can also be made of a material containing ions to be conducted (e.g., Li). x TiO2) film. The ion conductor film 307i can also be formed using a material whose main component is a solid electrolyte (e.g., Li3PO4) capable of conducting the ions to be conducted. The electrode film 306i can also be formed using a material containing the ions to be conducted (e.g., Li... 1-x CoO2) film. The current collector film 313i can also be formed from materials primarily composed of metals such as Au or conductive materials such as carbon. The stacked film of electrode film 308i, ion conductor film 307i, electrode film 306i, and current collector film 313i is patterned by photolithography into a stacked film of electrode film 308, ion conductor film 307, electrode film 306, and current collector film 313. Figure 12C , 12D ).

[0157] The stacked films of electrode film 308, ion conductor film 307, and electrode film 306 constitute the battery structure BST. The stacked films of electrode film 308, ion conductor film 307, electrode film 306, and current collector film 313 are patterned in a rectangular shape, for example, when viewed from above, such that a portion overlaps with the current collector film 309 when viewed from a direction perpendicular to the surface of the substrate SB1. The current collector film 309 and electrode film 308 are electrically connected by contact at their overlapping portions.

[0158] Subsequently, a tunnel insulating film 305i was formed using CVD and other methods. Figure 13A , 13B The tunnel insulating film 305i can be formed from a material mainly composed of silicon oxide or from a material mainly composed of other oxides. The tunnel insulating film 305i covers the exposed surface of the current collector film 309, the surface of the current collector film 313, and the surface of the substrate SB1.

[0159] Further, a semiconductor film 310i is formed by a CVD method or the like so as to cover the laminated film of the current collector film 309, the battery structure BST, the current collector film 313, and the tunnel insulating film 305i Figure 13C , 13D ). The semiconductor film 310i is a semiconductor film which should become the channel region 10a. The semiconductor film 310 is processed into a prescribed shape (for example, a substantially rectangular shape in plan view) by a photolithography and etching method or the like Figure 14A , 14B ). The semiconductor film 310 is processed into a shape which locally covers the battery structure (the electrode film 308 / the ion conductor film 307 / the electrode film 306) with the tunnel insulating film 305 and the current collector film 313 interposed therebetween, for example. Further, a semiconductor film which should become the source electrode and the drain electrode is formed. This semiconductor film is processed into the source electrode 302 and the drain electrode 303 by a photolithography and etching method or the like. The source electrode 302 and the drain electrode 303 are processed into a shape which locally covers the semiconductor film 310 (for example, a substantially rectangular shape in plan view), respectively. The source electrode 302 and the drain electrode 303 are patterned at positions which contact both ends in the long direction of the semiconductor film 310 and sandwich the battery structure with the tunnel insulating film 305 interposed therebetween Figure 14C , 14D ). The region between the source electrode 302 and the drain electrode 303 in the semiconductor film 310 becomes the channel region 10a. On the other hand, with respect to the current collector film 309, a contact hole 3051 is formed by partially removing the tunnel insulating film which does not overlap the battery structure (the electrode film 308 / the ion conductor film 307 / the electrode film 306) ( Figure 15A , 15B ), so as to expose a part of the surface of the current collector film 309. A gate contact electrode 314 is formed by embedding a conductive substance in the contact hole 3051 ( Figure 15C , 15D ). Thus, the transistor 301 having the gate electrode 304 which is laminated by the current collector film 309, the electrode film 308, the ion conductor film 307, the electrode film 306, the current collector film 313, and the tunnel insulating film 305 is constituted by a thin film transistor structure.

[0160] As described above, in the third embodiment, each transistor 301 in the nonvolatile memory device 300 is constituted by a thin film transistor structure. The gate electrode 304 of each transistor 301 includes the battery structure (the electrode film 308 / the ion conductor film 307 / the electrode film 306). According to such a structure, the transistor 301 can also store continuous analog information using a battery electromotive force, and can express information with high precision. In addition, since the transistor 301 can perform information writing with a small voltage / current, power consumption can be easily reduced.

[0161] (Fourth Embodiment)

[0162] Next, the non-volatile storage device of the fourth embodiment will be described. Hereinafter, the description will focus on the parts that differ from the first to third embodiments.

[0163] In the fourth embodiment, high precision storage voltage control is achieved by multiplying the battery structure BST in the gate electrode 404 of each transistor 401 of the non-volatile storage device 400.

[0164] In each transistor 401 of the non-volatile memory device 400, such as Figure 16 As shown, gate electrode 404 is formed by periodically and repeatedly stacking unit structures UST-1 to UST-4 above tunnel insulating film 5 and current collector film 13. Figure 16 The example illustrates a unit structure UST with four stacking cycles, but it can also have two, three, or more than five cycles. Each unit structure UST has an electrode film 6, an ion conductor film 7, an electrode film 8, and a current collector film 9 stacked sequentially from the substrate SB side. That is, each unit structure UST has a battery structure BST and a current collector film 9 stacked sequentially from the substrate SB side. The unit structure UST at the bottom of the gate electrode 404 ( Figure 16 In the middle, a current collector membrane 13 is disposed between the unit structure UST-1 and the tunnel insulating membrane 5.

[0165] In the gate electrode 404, multiple cell structures BSTs are equivalently connected in series between the tunnel insulating film 5 and the uppermost current collector film 9. Therefore, even if the electromotive force of each cell structure BST is small, a large overall electromotive force can be obtained. In the gate electrode 404, the storage voltage can be adjusted according to the electromotive force of each cycle, thus enabling high-precision write voltage. In addition, by setting it as a multi-cycle structure, the deviation of each cycle can be averaged, thereby reducing the impact of electromotive force deviation of the cell structure BSTs overall.

[0166] Furthermore, in the gate electrode 404, since the current collector film 9 of the unit structure UST-1 to UST-3 is conductive, the interface with the electrode film 6 of the upper unit structure UST can be used as an equipotential surface, and a contact potential difference can be formed at the interface with the electrode film 6 of the upper unit structure UST. This contact potential difference can be formed such that the potential of the electrode film 6 is lower than the potential of the current collector film 9 relative to electrons. As a result, the spatial deviation of ion current and tunneling current between the ion conductor film 7 and the electrode film 6 can be reduced, and when electrons are introduced into the current collector film 9, these electrons can be efficiently guided to the electrode film 6 of the upper unit structure UST.

[0167] Similarly, since the current collector film 13 is conductive, the interface with the electrode film 6 of the unit structure UST-1 can be made into an equipotential surface, and a contact potential difference can be formed at the interface with the electrode film 6 of the unit structure UST-1. This contact potential difference can be formed such that the potential of the electrode film 6 is lower than the potential of the current collector film 13 relative to electrons. As a result, the spatial deviation of ion current and tunneling current between the ion conductor film 7 and the electrode film 6 can be reduced, and when electrons are introduced into the current collector film 13, these electrons can be efficiently guided to the electrode film 6 of the unit structure UST-1.

[0168] As described above, in the fourth embodiment, the battery structure BST is multilayered in the gate electrode 404 of each transistor 401 of the non-volatile memory device 400. This reduces the overall impact of electromotive force deviation in the battery structure BST and enables more precise control of the storage voltage of each transistor 401.

[0169] (Fifth Implementation)

[0170] Next, the fifth embodiment will describe the non-volatile storage device. Hereinafter, the description will focus on the parts that differ from the first to fourth embodiments.

[0171] In the fifth embodiment, as a configuration example of the non-volatile memory device 500, a structure is illustrated in which Schottky barrier diodes SD-1 to SD-4 are disposed on the opposite side of the gate electrode 404 relative to the channel region 510a in transistors 501-1 and 501-2.

[0172] Non-volatile storage devices 500 Figure 17 As shown, a wiring layer M2, a plug layer V3, another wiring layer M3, a gate electrode layer M3-4, and a wiring layer M4 are sequentially stacked on top of a substrate (not shown). Wiring layer M2 includes conductive films 513-516. Plug layer V3 includes conductive plugs 517-520. Wiring layer M3 includes semiconductor films 510-1 and 510-2. Gate electrode layer M3-4 includes gate electrodes 404-1 and 504-2. Wiring layer M4 has semiconductor films 521 and 522. Figure 17 This is a cross-sectional view showing a non-volatile storage device 500. Figure 17 For the sake of simplicity, the interlayer insulating film has been omitted in the illustration.

[0173] The conductive films 513 to 516 are electrically insulated from each other with the interlayer insulating film. The conductive films 513 to 516 are each formed of a conductive substance such as a metal, and can be formed of, for example, a laminated film of a Ti film / Al film. The upper surfaces of the conductive films 513, 514, 515, and 516 are connected to the lower ends of the conductive plugs 517, 518, 519, and 520, and are electrically connected to the conductive plugs 517, 518, 519, and 520. The conductive films 513 and 516 are supplied with a prescribed voltage Vread, and the conductive films 514 and 515 are supplied with a ground potential.

[0174] The conductive plugs 517 to 520 are electrically insulated from each other with the interlayer insulating film. The conductive plugs 517 to 520 are each formed of a conductive substance such as a metal, and can be formed of, for example, a film in which W is a main component. The upper ends of the conductive plugs 517 and 518 are connected to the semiconductor film 510-1, and are electrically connected to the semiconductor film 510-1. The upper ends of the conductive plugs 519 and 520 are connected to the semiconductor film 510-2, and are electrically connected to the semiconductor film 510-2.

[0175] The vicinity of the junction interface of the semiconductor film 510-1 with the upper end of the conductive plug 517 constitutes a Schottky barrier diode SD-1. The Schottky barrier diode SD-1 is disposed on the opposite side of the gate electrode 504-1 with respect to the channel region 510a in the transistor 501-1. The Schottky barrier diode SD-1 takes the direction from the conductive plug 517 toward the semiconductor film 510-1 as a forward direction.

[0176] The vicinity of the junction interface of the semiconductor film 510-1 with the upper end of the conductive plug 518 constitutes a Schottky barrier diode SD-2. The Schottky barrier diode SD-2 is disposed on the opposite side of the gate electrode 504-1 with respect to the channel region 510a in the transistor 501-1. The Schottky barrier diode SD-2 takes the direction from the conductive plug 518 toward the semiconductor film 510-1 as a forward direction.

[0177] The vicinity of the junction interface of the semiconductor film 510-2 with the upper end of the conductive plug 519 constitutes a Schottky barrier diode SD-3. The Schottky barrier diode SD-3 is disposed on the opposite side of the gate electrode 504-2 with respect to the channel region 510a in the transistor 501-2. The Schottky barrier diode SD-3 takes the direction from the conductive plug 519 toward the semiconductor film 510-2 as a forward direction.

[0178] A region near the junction interface of the semiconductor film 510-2 and the upper end of the conductive plug 520 constitutes a Schottky barrier diode SD-4. The Schottky barrier diode SD-4 is arranged on the opposite side of the gate electrode 504-2 with respect to the channel region 510a in the transistor 501-2. The Schottky barrier diode SD-4 takes the direction from the conductive plug 520 toward the semiconductor film 510-2 as the forward direction.

[0179] The semiconductor films 510-1, 510-2 are electrically insulated from each other via the interlayer insulating film. The semiconductor films 510-1, 510-2 are each formed of a semiconductor to which conductivity is imparted. The semiconductor films 510-1, 510-2 are each formed of, for example, a semiconductor such as silicon, and a region other than the source region 502 and the drain region 503 contains an impurity of the second conductivity type. In the case where the second conductivity type is the p type, the impurity of the second conductivity type can be an accepter such as boron.

[0180] The semiconductor film 510-1 extends in the planar direction and connects a plurality of the conductive plugs 517, 518 in parallel. The upper surface of the semiconductor film 510-1 is connected to the gate electrode 404-1. The semiconductor film 510-1 has a channel region 510a at a position close to the gate electrode 404-1, and has a source region 502 and a drain region 503 in proximity to the channel region 510a. A structure including the gate electrode 404-1, the channel region 510a, the source region 502, and the drain region 503 constitutes a transistor 501-1. The source region 502 and the drain region 503 contain an impurity of the first conductivity type at a higher concentration than that of an impurity of the second conductivity type in a region other than the source region 502 and the drain region 503. In the case where the first conductivity type is the n type, the impurity of the first conductivity type can also be a donor such as phosphorus or arsenic.

[0181] The semiconductor film 510-2 extends in the planar direction and connects a plurality of the conductive plugs 519, 520 in parallel. The upper surface of the semiconductor film 510-2 is connected to the gate electrode 404-2. The semiconductor film 510-2 has a channel region 510a at a position close to the gate electrode 404-2, and has a source region 502 and a drain region 503 in proximity to the channel region 510a. A structure including the gate electrode 404-2, the channel region 510a, the source region 502, and the drain region 503 constitutes a transistor 501-2. The source region 502 and the drain region 503 contain an impurity of the first conductivity type at a higher concentration than that of an impurity of the second conductivity type in a region other than the source region 502 and the drain region 503. In the case where the first conductivity type is the n type, the impurity of the first conductivity type can also be a donor such as phosphorus or arsenic.

[0182] The gate electrodes 404-1, 504-2 have the same layer structure as the gate electrode 4 of the first embodiment. Each of the gate electrodes 404 has the tunnel insulating film 5, the collector film 13, the electrode film 6, the ion conductor film 7, the electrode film 8, and the collector film 9 stacked in this order from the semiconductor film 510 side. The tunnel insulating film 5 covers the upper surface of the semiconductor film 510. The stacked films of the electrode film 6, the ion conductor film 7, and the electrode film 8 constitute the battery structure BST. The collector film 9 of the gate electrode 404-1, 504-2 is in contact with the lower surface of the semiconductor film 521, 522, respectively.

[0183] The semiconductor films 521, 522 are electrically insulated from each other with the interlayer insulating film. The semiconductor films 521, 522 are each formed of a semiconductor to which conductivity is imparted. The semiconductor films 521, 522 are each formed of, for example, a semiconductor (e.g., silicon) containing an impurity of a second conductivity type. In the case where the second conductivity type is a p-type, the impurity of the second conductivity type can be an acceptor such as boron. The semiconductor film 521 is supplied with a voltage corresponding to the weight w, and the semiconductor film 522 is supplied with a voltage corresponding to the weight w.

[0184] The equivalent circuit of the structure of Figure 17 may be configured as Figure 18 . Figure 18 is a circuit diagram representing the nonvolatile memory device 500. As shown in Figure 18 , the nonvolatile memory device 500 has a first constant current source 82, a second constant current source 84, and a crossbar switch 38. The first constant current source 82 has a transistor 501-1, a Schottky barrier diode 80-1, and a resistive element 81-1. The second constant current source 84 has a transistor 501-2, a Schottky barrier diode 80-2, and a resistive element 81-2.

[0185] Figure 17 The Schottky barrier diodes SD-1, SD-4 shown in are each applied with a forward bias, and function as the resistive elements 81-1, 81-2, respectively. The Schottky barrier diodes SD-2, SD-3 are each applied with a reverse bias, and function as the Schottky barrier diodes 80-1, 80-2 that can equivalently become constant current sources, respectively.

[0186] Each Schottky barrier diode 80 utilizes a Schottky barrier diode created through the junction of a metal and a semiconductor. The Schottky barrier diode 80-1 included in the first constant current source 82 is connected in such a way that a reverse bias is applied between the positive output terminal 56 of the cross switch 38 and a reference potential (e.g., ground potential). Furthermore, the Schottky barrier diode 80-2 included in the second constant current source 84 is connected in such a way that a reverse bias is applied between the negative output terminal 58 of the cross switch 38 and a reference potential (e.g., ground potential). For example, when the power supply voltage (Vdd) is higher than the reference potential, the cathode of the Schottky barrier diode 80 is connected to either the positive output terminal 56 or the negative output terminal 58, and the anode is connected to the reference potential.

[0187] Schottky barrier diode 80, for example, has Figure 19 The voltage-current characteristics are shown. Figure 6 The Schottky barrier diode 80 shown is reverse-biased, allowing thermionic current to flow from the cathode to the anode. Compared to a PN junction diode, the Schottky barrier diode 80 has a larger leakage current flowing in the reverse direction, but its leakage current changes less with respect to the reverse voltage. Therefore, the Schottky barrier diode 80 is connected with a reverse bias, thereby allowing a relatively small constant current to flow. That is, the Schottky barrier diode 80, connected with a reverse bias, can be used as a constant current source carrying a constant current.

[0188] Furthermore, in this embodiment, the Schottky barrier diode 80 has a gate terminal. The gate terminal is a terminal used to apply a reverse bias voltage to the substrate. The magnitude of the leakage current of the Schottky barrier diode 80 varies depending on the height of the Schottky barrier between the metal and the semiconductor. The height of the Schottky barrier of the Schottky barrier diode 80 varies depending on the change in the reverse bias voltage applied to the gate terminal. Therefore, when the Schottky barrier diode 80 is used as a constant current source by being connected in a manner that applies a reverse bias voltage, the amount of current flowing through it can vary according to the change in the reverse bias voltage.

[0189] Transistor 501-1 is supplied with weight w, and transistor 501-2 is supplied with weight w, which is then inverted by the INV logic of the inverter, resulting in weight w. — .

[0190] Transistor 501-1 will use the gate voltage V corresponding to the weight w. G Applied to the gate electrode 404, and the gate voltage V G The corresponding on-resistance Ron is shown between the source electrode 502 and the drain electrode 503 (see reference). Figure 6 Correspondingly, the specified voltage Vread is divided by the resistance value of resistor element 81-1 and the on-resistance Ron of transistor 501-1, resulting in the voltage V.D is applied to the gate terminal of the Schottky barrier diode 80-1, and the amount of current of the Schottky barrier diode 80-1 as a constant current source is adjusted.

[0191] Similarly, the transistor 501-2 applies a gate voltage V corresponding to the weight w — to the gate electrode 404 G , and an on-resistance Ron corresponding to the gate voltage V G appears between the source electrode 502 and the drain electrode 503 (see Figure 18 ). Accordingly, a voltage V obtained by dividing a prescribed voltage Vread by the resistance value of the resistance element 81-2 and the on-resistance Ron of the transistor 501-2 D is applied to the gate terminal of the Schottky barrier diode 80-2, and the amount of current of the Schottky barrier diode 80-2 as a constant current source is adjusted.

[0192] For example, in the first constant current source 82, when a voltage V D = first voltage value (V1) is applied to the gate terminal according to the weight w = w1, the Schottky barrier diode 80 conducts a current of a first current value (I1). Therefore, when the first voltage value (V1) is applied to the gate terminal, the Schottky barrier diode 80 can suck out a current of the first current value (I1) from the positive output terminal 56 of the crossbar switch 38.

[0193] At this time, in the second constant current source 84, when a voltage V — = w2 is applied to the gate terminal according to the weight w D = second voltage value (V2), the Schottky barrier diode 80 conducts a current of a second current value (I2). w2 is a value obtained by logically inverting w1. For example, w1 = 0 and w2 = 1. Therefore, when the second voltage value (V2) is applied to the gate terminal, the Schottky barrier diode 80 can suck out a current of the second current value (I2) from the negative output terminal 58 of the crossbar switch 38.

[0194] In addition, in the first constant current source 82, when a voltage V D = second voltage value (V2) is applied to the gate terminal according to the weight w = w2, the Schottky barrier diode 80 conducts a current of a second current value (I2). Therefore, when the second voltage value (V2) is applied to the gate terminal, the Schottky barrier diode 80 can suck out a current of the second current value (I2) from the negative output terminal 58 of the crossbar switch 38.

[0195] At this time, in the second constant current source 84, when a voltage V — = w1 is applied to the gate terminal according to the weight w DWhen the voltage is equal to the first voltage value (V1), the Schottky barrier diode 80 conducts a current of the first current value (I1). Therefore, when the first voltage value (V1) is applied to the gate terminal, the Schottky barrier diode 80 can suck out a current of the first current value (I1) from the positive output terminal 56 of the crossbar switch 38.

[0196] That is, the transistor 501-1 of the first constant current source 82 and the transistor 501-2 of the second constant current source 84 perform logically inverted operations.

[0197] The first constant current source 82 and the second constant current source 84 can switch between the first state and the second state according to the value of the corresponding weight w. In the first state, the first constant current source 82 conducts a current of the first current value (I1) and the second constant current source 84 conducts a current of the second current value (I2). In the second state, the first constant current source 82 conducts a current of the second current value (I2) and the second constant current source 84 conducts a current of the first current value (I1). That is, Figure 20 The circuit can store and hold the value of the weight w as the first state and the second state.

[0198] As described above, in the fifth embodiment, the non-volatile storage device 500 is constituted by disposing Schottky barrier diodes SD-1 to SD-4 on the opposite side of the gate electrode 404 with respect to the channel region 510a in the transistors 501-1 and 501-2. With this structure, a circuit that can store and hold the value of the weight w as the first state and the second state can be realized.

[0199] (Sixth Embodiment)

[0200] Next, the non-volatile storage device of the sixth embodiment will be described. Hereinafter, the description will focus on the parts different from the first to fifth embodiments.

[0201] In the sixth embodiment, as a structural example of the non-volatile storage device 600, a structure of a neural network using the transistor 1 of the first embodiment is illustrated.

[0202] The non-volatile storage device 600 can be hardware-configured as Figure 1 The neural network 690 shown. The neural network 690 is a brain-type neural network. The neural network 690 has a plurality of neuron devices 91 and a plurality of synaptic devices 92. The plurality of synaptic devices 92 are arranged between the plurality of neuron devices 91. The neuron before each synaptic device 92 in the plurality of neuron devices 91 is designated as 91-1, and the neuron device after each synaptic device 92 is represented by 91-2. Each synaptic device 92 includes a transistor 1 (see Figure 21), the synaptic weight is stored in the transistor 1 as analog information. The synaptic weight has a value matching the strength of the relationship between the neuron device 91-1 and the neuron device 91-2.

[0203] When the internal potential of the neuron device 91-1 exceeds a predetermined fixed value, the signal is transmitted to the synapse device 92. The synapse device 92 generates a signal that causes the synaptic weight to act on the signal from the neuron device 91-1 and transmits it to the neuron device 91-2.

[0204] Figure 22 is a block diagram of the synapse device 92. The synapse device 92 has a synapse transmission device 921, a synaptic weight learning device 922, and a synaptic weight device 923. If a signal is generated in the neuron device 91-1, the signal a is sent to the synapse transmission device 921 and the synaptic weight learning device 922. In the synaptic weight learning device 922, if the signal a is received, the synaptic weight W is recalculated based on the information of the neuron device 91-1 or the neuron device 91-2, and is sent to the synaptic weight device 923. The synaptic weight device 923 has the transistor 1. The synaptic weight device 923 stores and holds the synaptic weight W in the transistor 1 based on the information from the synaptic weight learning device 922. The synapse transmission device 921, if it receives the signal a, acquires the synaptic weight W from the synaptic weight device 923, causes the synaptic weight W to act on the signal a (for example, multiplies the synaptic weight W), generates a signal b, and transmits it to the neuron device 91-2.

[0205] Figure 22 is a circuit diagram showing the synaptic weight device 923 and the synapse transmission device 921. The synaptic weight device 923 uses the transistor 1 as a synaptic weight holding function. The synapse transmission device 921 has a weight current element 62, an input switch 64, a capacitor 66, an output current element 68, a charge adjustment element 65, a first constant current element 63, and a second constant current element 61. The synaptic weight device 923 has a weight storage element 71, a switch 73, and a weight current setting element 72. The weight storage element 71 uses the transistor 1 to store the synaptic weight W.

[0206] The weight current element 62 flows a weight current (I W ) corresponding to the synaptic weight W corresponding to the resistance value held by the weight storage element 71 of the synaptic weight device 923. For example, the weight current element 62 flows a weight current (I W ) proportional to the synaptic weight W. In the case where the input switch 64 is in the on state, the weight current element 62 draws the weight current (I W ) from the node A to the reference potential (for example, the ground potential). In the case where the input switch 64 is in the off state, the weight current element 62 does not flow the weight current (IW (Set the weighted current to 0).

[0207] In this embodiment, the weighting current element 62 is a MOS-FET (Metal Oxide Semiconductor Field Effect Transistor). Figure 22 In the example, the weighted current element 62 is an N-channel MOS-FET.

[0208] As the weighted current element 62 of the MOSFET, a weighted voltage (V) is applied to the gate. W The drain is connected to node A. Furthermore, the weighting current element 62 of the MOS-FET is connected to the weighting voltage (V). W The weighted current (I) corresponding to the current quantity W It flows between the drain and the source.

[0209] Input switch 64 switches whether to enable or disable the weighting current (I) based on the binary input signal (Sin) output from the preceding neuron device 91-1. W The current flows to the weighting current element 62. For example, when the input signal (Sin) is 1, the input switch 64 causes the weighting current (I) to flow to the weighting current element 62. W ) flow. For example, input switch 64 does not cause the weighting current (I) to flow when the input signal (Sin) is 0. W ) flows through (i.e., the weighted current (I) W (Set to 0).

[0210] In this embodiment, the input switch 64 is a MOS-FET that performs the switching action. Figure 3B In this example, input switch 64 is an N-channel MOS-FET. As an input switch 64, which is a MOS-FET, an input signal (Sin) is applied to its gate, and its drain is connected to the source of the weighted current element 62, which is connected to a reference potential.

[0211] Furthermore, the input switch 64 of the MOS-FET becomes on when the input signal (Sin) is 1, and by grounding the source of the weighting current element 62, the weighting current (I) is increased. W The weighted current element 62 flows through the weighted current element 62. Furthermore, the input switch 64, acting as the MOS-FET, is in the off state when the input signal (Sin) is 0, thus disconnecting the source of the weighted current element 62 from ground and preventing the weighted current (I) from flowing through it. W The current flows through the weighted current element 62.

[0212] The capacitor 66 has a first terminal 66a and a second terminal 66b. The first terminal 66a of the capacitor 66 is connected to a power source potential (for example, V DD ) that generates a constant voltage. Such a capacitor 66 applies a constant voltage to the first terminal 66a. In addition, the capacitor 66 generates a capacitor voltage (V C ) at the second terminal 66b. The capacitor voltage (V C ) is a value obtained by subtracting the voltage generated by the capacitor 66 from the power source potential. The voltage generated by the capacitor 66 is a voltage obtained by dividing the amount of charge accumulated by the electrostatic capacitance.

[0213] The output switch 68 supplies an output current (I out ) to the neuron device 91-2 in the subsequent stage, in accordance with the capacitor voltage (V C ) generated at the second terminal 66b of the capacitor 66.

[0214] The synaptic weight device 923 holds the synaptic weight W decided by the synaptic weight learning device 922 in the weight storage element 71. The weight storage element 71 holds the synaptic weight W as a resistance value using the transistor 1.

[0215] The operation method at the time of resistance writing in the synaptic weight device 923 will be described. The transistor 1 applies a voltage of, for example, about 4 V as a substrate bias at the time of erasing (charging) (refer to Figure 23 ), and thus it is likely that the element is damaged if erasing (charging) is directly performed.

[0216] Therefore, in a case where the analog information corresponding to the learning result is erased (charged), first, the control signal S 922 and the synaptic weight W are transmitted from the synaptic weight learning device 922 to the synaptic weight device 923. The control signal S 922 becomes a non-active level at the time of updating the synaptic weight W by the weight storage element 71, and the switch 73 is turned off (OFF). The control signal S 922 becomes an active level at the time of not updating the synaptic weight W in the weight storage element 71, and the switch 73 is turned on. Thereby, it is possible to eliminate the influence of the weight current element 62 at the time of updating the synaptic weight W by the synaptic weight device 923.

[0217] After that, the substrate bias of the weight storage element 71 and the weight current setting element 72 is changed to a specified voltage, and the value (is discharged) required for writing (discharging) to the weight storage element 71 is written.

[0218] After the writing or erasing ends, the substrate bias of the weight storage element 71 and the weight current setting element 72 is changed again to the same value as the other substrate bias. The output of the synaptic weight device 923 can be supplied to the gate of the weight current element 62 of the synapse transmission device 921.

[0219] If the threshold voltage of switch 73 is set to V thre Then the gate voltage V of the weighting current element 72 of the synaptic weighting device 923 G The gate voltage Vg of the weighted current element 62 of the synaptic transmission device 921 will generate V G +V thre =V g The difference. Therefore, in the weighted storage element 71, by satisfying 0 < V G <V DD -V thre Gate voltage V range G The on-resistance value is set using transistor 1. This means that the weight storage element 71 can use transistor 1 to store and maintain the synaptic weight W as continuous analog information. Therefore, the synaptic weighting device 923 using this weight storage element 71 has a synaptic weight W setting range of V. thre <W<V DD来 Determined weighted current I W The action is performed.

[0220] As described above, in the sixth embodiment, the non-volatile memory device 600 is configured to use transistor 1 as a continuous network. This allows for the construction of a continuous network in transistor 1 that stores and maintains synaptic weights W as continuous analog information.

[0221] (Seventh Implementation)

[0222] Next, the non-volatile storage device of the seventh embodiment will be described. Hereinafter, the description will focus on the parts that differ from the first to sixth embodiments.

[0223] In the seventh embodiment, as a structural example of the non-volatile memory device 700, the structure of an arithmetic system that uses the transistor 1 of the first embodiment to perform nonlinear operations is illustrated.

[0224] The non-volatile storage device 700 is configured in hardware as follows Figure 1 The arithmetic system 720 is shown. The arithmetic system 720 performs nonlinear operations simulating neurons using a simple structure. The arithmetic system 720 includes a positive current source 732, a negative current source 734, a comparator 736, M cross switches 738, a clamping circuit 740, and a coefficient storage unit 742. The coefficient storage unit 742 includes transistor 1 (see reference). Figure 23 The coefficients are stored as analog information in transistor 1.

[0225] The positive-side current source 732 has a positive-side terminal 746. The positive-side current source 732 outputs a current from the positive-side terminal 746. Further, the positive-side current source 732 outputs a first voltage corresponding to a value of 1 / L (L is an integer of 2 or more) of the current output from the positive-side terminal 746. For example, the positive-side current source 732 outputs the first voltage in proportion to the value of 1 / L of the current output from the positive-side terminal 746. In the present embodiment, L = M. However, L can not be the same as M. In addition, in Figure 23 A plurality of positive-side terminals 746 are described in the present embodiment. However, Figure 23 The plurality of positive-side terminals 746 described in the present embodiment are electrically connected.

[0226] For example, the positive-side current source 732 has L first FETs 748. The L first FETs 748 are each a field effect transistor having the same characteristics. In the present embodiment, the L first FETs 748 are each a pMOS transistor having the same characteristics.

[0227] The gates of the L first FETs 748 are commonly connected, the sources are connected to a second reference potential, and the drains are connected to the gates and the positive-side terminal 746. The second reference potential is, for example, a power supply voltage (V DD ) of the positive side. That is, the L first FETs 748 are each diode-connected, the source is connected to the second reference potential (for example, V DD ), and the gate and the drain are connected to the positive-side terminal 746. Further, the positive-side current source 732 outputs the voltage of the positive-side terminal 746 (the voltage of the gate of the first FET 748) as the first voltage.

[0228] The negative-side current source 734 has a negative-side terminal 750. The negative-side current source 734 outputs a current from the negative-side terminal 750. Further, the negative-side current source 734 outputs a second voltage corresponding to a value of 1 / L of the current output from the negative-side terminal 750. For example, the negative-side current source 734 outputs the second voltage in proportion to the value of 1 / L of the current output from the negative-side terminal 750. In addition, in Figure 1 A plurality of negative-side terminals 750 are described in the present embodiment. However, the plurality of negative-side terminals 750 are electrically connected.

[0229] For example, the negative-side current source 734 has L second FETs 752. The L second FETs 752 are each a field effect transistor having the same characteristics as the first FET 748. In the present embodiment, the L second FETs 752 are each a pMOS transistor having the same characteristics as the first FET 748.

[0230] The gates of the L second FETs 752 are commonly connected, the sources are connected to the second reference potential, and the drains are connected to the gates and the negative-side terminal 750. That is, the L second FETs 752 are respectively connected in diode connection, the sources are connected to the second reference potential (for example, VDD), and the gates and the drains are connected to the negative-side terminal 750. Also, the negative-side current source 734 outputs the voltage of the negative-side terminal 750 (the voltage of the gate of the second FET 752) as the second voltage.

[0231] The comparison section 736 compares the magnitude of the first voltage output from the positive-side current source 732 and the second voltage output from the negative-side current source 734. Also, the comparison section 736 outputs an output signal (y) of a value corresponding to the comparison result of the first voltage and the second voltage. The comparison section 736 outputs an output signal of a first value (for example, -1) in the case where the first voltage is smaller than the second voltage, and outputs an output signal of a second value (for example, +1) in the case where the first voltage is equal to or larger than the second voltage. Alternatively, the comparison section 736 can output an output signal of the second value (for example, +1) in the case where the first voltage is smaller than the second voltage, and output an output signal of the first value (for example, -1) in the case where the first voltage is equal to or larger than the second voltage.

[0232] The M crossbars 738 are respectively provided in correspondence with the M input signals. In the present embodiment, the arithmetic system 720 has a first crossbar 738-1 to an Mth crossbar 738-M as the M crossbars 738. For example, the first crossbar 738-1 corresponds to the first input signal (xl), the second crossbar 738-2 corresponds to the second input signal (x2), and the Mth crossbar 738-M corresponds to the Mth input signal (xM).

[0233] The M crossbars 738 respectively have a positive-side inflow terminal 756, a negative-side inflow terminal 758, a first terminal 760, and a second terminal 762.

[0234] The M crossbars 738 respectively connect the first terminal 760 to either one of the positive-side inflow terminal 756 and the negative-side inflow terminal 758. Also, the M crossbars 738 respectively connect the second terminal 762 to the other of the positive-side inflow terminal 756 and the negative-side inflow terminal 758, which is not connected to the first terminal 760. The M crossbars 738 respectively switch which of the positive-side inflow terminal 756 or the negative-side inflow terminal 758 the first terminal 760 and the second terminal 762 are connected to, in accordance with the value of the corresponding input signal.

[0235] The clamp circuit 740 has M positive-side FET switches 766 corresponding to the M crossbars 738, respectively. In the present embodiment, the clamp circuit 740 has a first positive-side FET switch 766-1 to an Mth positive-side FET switch 766-M as the M positive-side FET switches 766. For example, the first positive-side FET switch 766-1 corresponds to the first crossbar 738-1, the second positive-side FET switch 766-2 corresponds to the second crossbar 738-2, and the Mth positive-side FET switch 766-M corresponds to the Mth crossbar 738-M.

[0236] The gate of each of the M positive-side FET switches 766 is connected to the clamp potential (V clmp ), the source is connected to the positive-side terminal 746, and the drain is connected to the positive-side inflow terminal 756 of the corresponding crossbar 738. Each of the M positive-side FET switches 766 is turned on between the source and the drain in the operation of the arithmetic system 720. Thus, the positive-side inflow terminal 756 of each of the M crossbars 738 is connected to the positive-side terminal 746 of the positive-side current source 732 in the operation of the arithmetic system 720, and the voltage is fixed to the clamp potential (V clmp ).

[0237] Further, the clamp circuit 740 has M negative-side FET switches 768 corresponding to the M crossbars 738, respectively. In the present embodiment, the clamp circuit 740 has a first negative-side FET switch 768-1 to an Mth negative-side FET switch 768-M as the M negative-side FET switches 768. For example, the first negative-side FET switch 768-1 corresponds to the first crossbar 738-1, the second negative-side FET switch 768-2 corresponds to the second crossbar 738-2, and the Mth negative-side FET switch 768-M corresponds to the Mth crossbar 738-M.

[0238] The gate of each of the M negative-side FET switches 768 is connected to the clamp potential (V clmp ), the source is connected to the negative-side terminal 750, and the drain is connected to the negative-side inflow terminal 758 of the corresponding crossbar 738. Each of the M negative-side FET switches 768 is turned on between the source and the drain in the operation of the arithmetic system 720. Thus, the negative-side inflow terminal 758 of each of the M crossbars 738 is connected to the negative-side terminal 750 of the negative-side current source 734 in the operation of the arithmetic system 720, and the voltage is fixed to the clamp potential (V clmp ).

[0239] The coefficient storage section 742 has M units 772 corresponding to the M coefficients respectively. In the present embodiment, the coefficient storage section 742 has a first unit 772-1 to an Mth unit 772-M as the M units 772. For example, the first unit 772-1 corresponds to the first coefficient (w1), the second unit 772-2 corresponds to the second coefficient (w2), and the Mth unit 772-M corresponds to the Mth coefficient (wM). M ) respectively. Further, the first coefficient (w1) corresponds to the first input signal (xl), the second coefficient (w2) corresponds to the second input signal (x2), and the Mth coefficient (wM) corresponds to the Mth input signal (xM). M ) respectively. Further, the first coefficient (w1) corresponds to the first input signal (xl), the second coefficient (w2) corresponds to the second input signal (x2), and the Mth coefficient (wM) corresponds to the Mth input signal (xM). M ) respectively. Further, the first coefficient (w1) corresponds to the first input signal (xl), the second coefficient (w2) corresponds to the second input signal (x2), and the Mth coefficient (wM) corresponds to the Mth input signal (xM).

[0240] The M units 772 respectively include a first transistor 774 and a second transistor 776. The drain of the first transistor 774 is connected to the first terminal 760 of the corresponding crossbar switch 738, and the source is connected to a first reference potential. The first reference potential is, for example, ground. The drain of the second transistor 776 is connected to the second terminal 762 of the corresponding crossbar switch 738, and the source is connected to the first reference potential.

[0241] The first transistor 774 and the second transistor 776 can each use the transistor 1 (refer to FIG. 1) described above. The first transistor 774 and the second transistor 776 are each capable of storing a coefficient as continuous analog information. Figure 24

[0242] The first transistor 774 and the second transistor 776 switch the size relationship of the resistance values in accordance with the value of the corresponding coefficient. For example, a setting section (not shown) receives the M coefficients before receiving the M input signals. Also, the setting section sets the size relationship of the resistance values of the first transistor 774 and the second transistor 776 included in the corresponding unit 772 in accordance with each of the M coefficients received.

[0243] For example, each of the plurality of units 772, in the case where the corresponding coefficient is +1, the first transistor 774 is set to a first resistance value, and the second transistor 776 is set to a second resistance value different from the first resistance value. Also, each of the plurality of units 772, in the case where the corresponding coefficient is -1, the first transistor 774 is set to the second resistance value, and the second transistor 776 is set to the first resistance value.

[0244] ​Furthermore, the M cross switches 738 switch the connection between the first terminal 760 and the second terminal 762 and the positive terminal 746 (positive inflow terminal 756) and the negative terminal 750 (negative inflow terminal 758) respectively, based on the value of the corresponding input signal.

[0245] For example, in the case of direct connection, each of the M cross switches 738 has its first terminal 760 connected to the positive terminal 746 (positive inflow terminal 756) and its second terminal 762 connected to the negative terminal 750 (negative inflow terminal 758). Alternatively, in the case of reverse connection, each of the M cross switches 738 has its first terminal 760 connected to the negative terminal 750 (negative inflow terminal 758) and its second terminal 762 connected to the positive terminal 746 (positive inflow terminal 756).

[0246] For example, each of the M cross switches 738 is directly connected when the corresponding input signal value is +1, and is reversed when the corresponding input signal value is -1.

[0247] Alternatively, each of the M cross switches 738 can be reversed when the corresponding input signal value is +1, and directly connected when the corresponding input signal value is -1.

[0248] As described above, in the seventh embodiment, the non-volatile memory device 700 is configured as an arithmetic system that performs nonlinear operations simulating neurons using the transistor 1 of the first embodiment. Therefore, an arithmetic system capable of storing coefficients as continuous analog information with high precision can be constructed.

[0249] (Eighth Implementation Method)

[0250] Next, the non-volatile storage device of the eighth embodiment will be described. Hereinafter, the description will focus on the parts that differ from the first to seventh embodiments.

[0251] In the eighth embodiment, as a non-volatile storage device 800, an example is shown of the structure of an arithmetic system that uses the transistor 1 of the first embodiment to perform product summation operations.

[0252] The non-volatile memory device 800 is hardware configured as Figure 1 The computing system 820 is shown as described. The computing system 820 performs calculations on multiple neurons in a certain layer of a neural network in parallel through product-sum operations. The computing system 820 utilizes multiple transistors 1 (see reference 1). Figure 1 The 820 arithmetic system uses a bar array structure to implement product summation. The arithmetic system 820 can perform operations other than product summation via digital circuits.

[0253] The arithmetic system 820 has a plurality of DA converters (DAC) 821-0 to 821-4, a crossbar array structure 822, and a plurality of AD converters (ADC) 823-0 to 823-4. The crossbar array structure 822 has a plurality of word lines WL0 to WL4, a plurality of bit lines BL0 to BL4, a plurality of source lines SL0 to SL4, and a plurality of transistors 801(0,0) to 801(4,4). Each of the word lines WL0 to WL4 extends in the row direction and is arranged in the column direction. Each of the bit lines BL0 to BL4 extends in the column direction and is arranged in the row direction. Each of the source lines SL0 to SL4 is disposed on the opposite side of the corresponding bit line BL with the transistor 801 therebetween, extends in the column direction, and is arranged in the row direction. Each of the transistors 801 uses the transistor 1 (refer to FIG. 1). ​ Each of the transistors 801(0,0) to 801(4,4) corresponds to the plurality of word lines WL0 to WL4, the plurality of bit lines BL0 to BL4, and the plurality of source lines SL0 to SL4, respectively.

[0254] In the crossbar array structure 822, the plurality of transistors 801(0,0) to 801(4,4) are disposed at positions where the plurality of word lines WL0 to WL4 and the plurality of bit lines BL0 to BL4 cross. The source electrode of each of the transistors 801 is connected to the corresponding source line SL, the gate electrode is connected to the corresponding word line WL, and the drain electrode is connected to the corresponding bit line BL. Each of the transistors 801(0,0) to 801(4,4) functions as a multiplication element that multiplies a received signal by a weight W 0，0 ~ W 4，4 corresponding to the weight W 0，0 ~ W 4，4 corresponding to the weight W

[0255] The plurality of DA converters 821-0 to 821-4 DA-convert the plurality of digital values D0 to D4 to generate a plurality of word line voltages X0 to X4, and supply the plurality of word line voltages X0 to X4 to the plurality of word lines WL0 to WL4. The plurality of word line voltages X0 to X4 are applied in parallel to the plurality of transistors 801(0,0) to 801(4,4). By multiplying the plurality of word line voltages X0 to X4 by the plurality of weights W 0，0 ~ W 4，4 and summing up per column, a plurality of bit line currents Y0 to Y4 are generated. The plurality of AD converters 823-0 to 823-4 AD-convert a plurality of bit line voltages corresponding to the plurality of bit line currents Y0 to Y4 to generate a plurality of digital values D0' to D4' and output them.

[0256] Among the plurality of transistors 801(0, 0) to 801(4, 4), a prescribed bias voltage is applied to the gate electrode and the well region in advance in accordance with the value of the weight W 0，0 4，4 . Thereby, the charge state of the battery configuration included in the gate electrode is set to the charge state corresponding to the value of the weight W 0，0 4，4 . The on-resistance value of the transistor can be set to the value corresponding to the charge state. The weight W 0，0 4，4 is set in advance to the charge state of the battery configuration of the transistors 801(0, 0) to 801(4, 4), and can be set as continuous analog information. That is, the arithmetic system 820 can be configured as an arithmetic system capable of learning the value of the weight W 0，0 4，4 with high precision.

[0257] As described above, in the eighth embodiment, as the nonvolatile memory device 800, an arithmetic system that performs the sum-of-products operation using the transistor 1 of the first embodiment is configured. Thereby, an arithmetic system capable of learning the value of the weight with high precision as continuous analog information can be configured.

[0258] In addition, the above-described embodiments can be summarized as the following technical solutions.

[0259] Technical Solution 1

[0260] A nonvolatile memory device includes: a plurality of transistors, each of which is a field effect type and has a gate electrode and a channel region,

[0261] the gate electrode includes:

[0262] a tunnel insulating film that covers the channel region;

[0263] a first collector film that is disposed on the opposite side of the channel region with respect to the tunnel insulating film;

[0264] an ion conductor film that is disposed between the tunnel insulating film and the first collector film;

[0265] a first electrode film that is disposed between the tunnel insulating film and the ion conductor film and contacts the ion conductor film;

[0266] a second electrode film that is disposed between the ion conductor film and the first collector film and contacts the ion conductor film; and

[0267] a second collector film that is disposed between the tunnel insulating film and the second electrode film. ​​​​

[0268] Technical Solution 2

[0269] The nonvolatile memory device according to Technical Solution 1,

[0270] The first electrode film functions as a positive electrode with respect to the ion conductor film,

[0271] The second electrode film functions as a negative electrode with respect to the ion conductor film.

[0272] Technical Solution 3

[0273] The nonvolatile memory device according to Technical Solution 1,

[0274] The first electrode film functions as a negative electrode with respect to the ion conductor film,

[0275] The second electrode film functions as a positive electrode with respect to the ion conductor film.

[0276] Technical Solution 4

[0277] The nonvolatile memory device according to Technical Solution 1,

[0278] The first electrode film is thinner than the ion conductor film,

[0279] The second electrode film is thinner than the ion conductor film.

[0280] Technical Solution 5

[0281] The nonvolatile memory device according to Technical Solution 1,

[0282] The gate electrode further includes:

[0283] A second ion conductor film disposed between the second electrode film and the first electrode film;

[0284] A third electrode film disposed between the second electrode film and the second ion conductor film and in contact with the second ion conductor film; and

[0285] A fourth electrode film disposed between the second ion conductor film and the first electrode film and in contact with the second ion conductor film.

[0286] Technical Solution 6

[0287] The nonvolatile memory device according to Technical Solution 1,

[0288] The first electrode film and the second electrode film each contain at least one of an electron-ion mixed conductor, an alkali metal, and an alkaline earth metal.

[0289] Technical solution 7

[0290] The nonvolatile memory device according to technical solution 1,

[0291] The first electrode film, the ion conductor film, and the second electrode film constitute a secondary battery.

[0292] Technical solution 8

[0293] The nonvolatile memory device according to technical solution 7,

[0294] The secondary battery is a lithium battery or a magnesium battery.

[0295] Technical solution 9

[0296] The nonvolatile memory device according to technical solution 7,

[0297] The nonvolatile memory device stores analog information as electromotive force of the secondary battery in the transistor.

[0298] Technical solution 10

[0299] The nonvolatile memory device according to technical solution 9,

[0300] The nonvolatile memory device accumulates charge from the channel region through the tunnel insulating film to the second electrode film and stores the analog information in the transistor.

[0301] Technical solution 11

[0302] The nonvolatile memory device according to technical solution 10,

[0303] The transistor further has a source electrode and a drain electrode, which are adjacent to the channel region on both sides along the tunnel insulating film,

[0304] The nonvolatile memory device observes a drain current flowing between the drain electrode and the source electrode and reads out the analog information from the transistor.

[0305] Technical solution 12

[0306] The nonvolatile memory device according to technical solution 11,

[0307] Further provided is a diode, which is disposed on the opposite side of the gate electrode with respect to the channel region in the transistor.

[0308] Technical solution 13

[0309] A nonvolatile memory device includes a plurality of transistors each being a field effect transistor and having a gate electrode and a channel region,

[0310] The gate electrode includes,

[0311] A tunnel insulating film covers the channel region.

[0312] A collector film is disposed on the opposite side of the channel region from the tunnel insulating film.

[0313] An ion conductor film is disposed between the tunnel insulating film and the collector film.

[0314] A first electrode film is disposed between the tunnel insulating film and the ion conductor film and in contact with the ion conductor film.

[0315] A second electrode film is disposed between the ion conductor film and the collector film and in contact with the ion conductor film.

[0316] Several embodiments of the present application have been described, but these embodiments are presented as examples and are not intended to limit the scope of the application. These new embodiments can be implemented in other various ways, and various omissions, substitutions, and changes can be made without departing from the scope of the application. These embodiments and modifications thereof are included within the scope or spirit of the application, and are included within the scope of the application as recited in the claims and equivalents thereof.

Claims

1. A non-volatile memory device comprising a plurality of transistors, each of the plurality of transistors being field-effect type and having a gate electrode and a channel region, the gate electrode comprising: A tunnel insulation film covers the trench area; A first current collector film is disposed on the opposite side of the trench region relative to the tunnel insulating film; An ion conductor membrane is disposed between the tunnel insulating membrane and the first current collector membrane; a first electrode membrane is disposed between the tunnel insulating membrane and the ion conductor membrane and is in contact with the ion conductor membrane. The second electrode membrane is disposed between the ion conductor membrane and the first current collector membrane and is in contact with the ion conductor membrane; A second current collector film is disposed between the tunnel insulating film and the second electrode film. The gate electrode includes an all-solid-state battery structure that can be charged and discharged according to the voltage applied between the first electrode film and the second electrode film, and the electromotive force is variable according to the charging and discharging state. Charging and discharging are carried out by allowing tunneling current to flow through the tunnel insulating film. Electrons that tunnel through the tunnel insulating film from the channel region are stored in the first electrode film after passing through the first current collector film, thereby discharging the all-solid-state battery structure.

2. The non-volatile storage device according to claim 1, wherein the first electrode film functions as the positive electrode relative to the ion conductor film, and the second electrode film functions as the negative electrode relative to the ion conductor film.

3. The non-volatile storage device according to claim 1, wherein the first electrode film functions as the negative electrode relative to the ion conductor film, and the second electrode film functions as the positive electrode relative to the ion conductor film.

4. The non-volatile memory device according to claim 1, wherein the first electrode film is thinner than the ion conductor film, and the second electrode film is thinner than the ion conductor film.

5. The non-volatile memory device according to claim 1, wherein the gate electrode further comprises: A second ion conductor membrane is disposed between the second electrode membrane and the first electrode membrane; The third electrode membrane is disposed between the second electrode membrane and the second ion conductor membrane, and is in contact with the second ion conductor membrane; A fourth electrode membrane is disposed between the second ion conductor membrane and the first electrode membrane, and is in contact with the second ion conductor membrane.

6. The non-volatile storage device according to claim 1, wherein the first electrode film and the second electrode film respectively comprise at least one of an electron-ion mixed conductor, an alkali metal, and an alkaline earth metal.

7. The non-volatile storage device according to claim 1, wherein the first electrode film, the ion conductor film, and the second electrode film constitute a secondary battery.

8. The non-volatile storage device according to claim 7, wherein the secondary battery is a lithium battery or a magnesium battery.

9. The non-volatile memory device according to claim 7, wherein the non-volatile memory device stores analog information as the electromotive force of the secondary battery in the transistor.

10. The non-volatile memory device according to claim 9, wherein the non-volatile memory device accumulates charge from the channel region through the tunnel insulating film to the second electrode film and stores the analog information in the transistor.

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