Display panel

Abstract

Embodiments of the present application provide a display panel, comprising: a substrate, a first flat layer is arranged on one side of the substrate, and a first via hole is arranged on the first flat layer; a first ITO layer, the first ITO layer is arranged on the side of the first flat layer away from the substrate; an anode, the anode is arranged on the side of the first ITO layer away from the first flat layer; wherein the first ITO layer is provided with a first groove, so that part of the anode is arranged in the first groove, and the projection of the first groove on the substrate at least partially coincides with the projection of the first via hole on the substrate. Embodiments of the present application set the first groove on the first ITO layer, so that part of the anode can be arranged in the first groove, and the projection of the first groove and the first via hole on the substrate at least partially coincides, which improves the problem of anode fracture caused by excessive stress impact during cleaning due to uneven first via hole.

Description

TECHNICAL FIELD

[0001] The present application relates to the display field, and particularly relates to a display panel. BACKGROUND

[0002] Compared with a liquid crystal display (LCD), an organic light-emitting diode (OLED) display has the advantages of thinness, lightness, wide viewing angle, active light-emitting, continuous adjustable light-emitting color, fast response speed, low energy consumption, low driving voltage, high light-emitting efficiency, flexible display and the like, and has attracted great attention from the industry and the scientific community.

[0003] However, in the manufacturing process of the existing OLED display panel, a via hole needs to be arranged on a planar layer, and the via hole is easy to cause the deposited metal film layer to be uneven, and thus leads to the situation that the anode is broken due to uneven stress distribution in the manufacturing process of the anode. SUMMARY

[0004] Embodiments of the present application provide a display panel, which can improve the problem of breakage of the OLED display panel in manufacturing the anode.

[0005] Embodiments of the present application provide a display panel, which comprises:

[0006] a substrate,

[0007] a first planar layer, which is arranged on one side of the substrate, and a first via hole is arranged on the first planar layer;

[0008] a first ITO layer, which is arranged on a side of the first planar layer away from the substrate;

[0009] an anode, which is arranged on a side of the first ITO layer away from the first planar layer;

[0010] wherein the first ITO layer is provided with a first groove, so that part of the anode is arranged in the first groove, and a projection of the first groove on the substrate at least partially overlaps a projection of the first via hole on the substrate.

[0011] Optionally, an area of the projection of the first groove on the substrate is greater than an area of the projection of the first via hole on the substrate.

[0012] Optionally, a groove depth of the first groove is less than a thickness of the first ITO layer.

[0013] Optionally, the display panel comprises a plurality of pixels and driving transistors, the pixels are arranged on a side of the anode away from the first planar layer, the anode comprises a sub-anode of a sub-pixel with the smallest volume in each of the pixels, the sub-anode comprises a main body and a connecting part, a projection of the main body on the substrate is located within a projection of the driving transistor on the substrate, a part of the projection of the driving transistor on the substrate is located outside a projection of the connecting part on the substrate, and the first groove is arranged at a position corresponding to the connecting part on the first ITO layer. Optionally, the display panel further comprises a second planar layer, the second planar layer is arranged on a side of the first planar layer away from the first ITO layer, the second planar layer is provided with a second via hole, and the first ITO layer is provided with a second groove, so that part of the anode is arranged in the second groove, and a projection of the second groove on the substrate at least partially overlaps a projection of the second via hole on the substrate.

[0014] Optionally, the display panel further comprises a third planar layer, the third planar layer is arranged on a side of the second planar layer away from the first ITO layer, the third planar layer is provided with a third via hole, and the first ITO layer is provided with a third groove, so that part of the anode is arranged in the third groove, and a projection of the third groove on the substrate at least partially overlaps a projection of the third via hole on the substrate.

[0015] Optionally, the display panel comprises a fourth planar layer, the fourth planar layer is arranged on a side of the third planar layer away from the first ITO layer, the fourth planar layer is provided with a fourth via hole, and the first ITO layer is provided with a fourth groove, so that part of the anode is arranged in the fourth groove, and a projection of the fourth groove on the substrate at least partially overlaps a projection of the fourth via hole on the substrate.

[0016] Optionally, the first groove, the second groove, the third groove and the fourth groove do not overlap.

[0017] Optionally, a groove depth of the first groove, a groove depth of the second groove, a groove depth of the third groove and a groove depth of the fourth groove are equal.

[0018] Optionally, the display panel further comprises a first metal layer and a second metal layer, the first metal layer is arranged on a side of the fourth planar layer away from the third planar layer, and the second metal layer is arranged between the fourth planar layer and the third planar layer.

[0019] Optionally, the display panel further comprises:

[0020] a second ITO layer disposed on one side of the second planar layer close to the first ITO layer;

[0021] a third ITO layer disposed on one side of the third planar layer close to the first ITO layer.

[0022] The display panel provided by the present application has the beneficial effects that: the display panel provided by the present application comprises a substrate and, sequentially disposed on one side of the substrate, a first planar layer, a first ITO layer and an anode, wherein the first planar layer is provided with a first via hole, and the first ITO layer is provided with a first groove, so that part of the anode is disposed in the first groove, and a projection of the first groove on the substrate at least partially overlaps a projection of the first via hole on the substrate. The first groove is disposed on the first ITO layer, so that the anode can be partially disposed in the first groove, and the situation that the anode is protruding is alleviated. The first groove and the first via hole at least partially overlap on the substrate, which better improves the problem that the anode is broken due to excessive stress impact during cleaning caused by the uneven first via hole, reduces crack propagation, and makes the pixel unit not appear display problems. BRIEF DESCRIPTION OF DRAWINGS

[0023] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0024] In order to more completely understand the present application and its beneficial effects, the following will be described with reference to the drawings. In the following description, the same reference numerals represent the same parts.

[0025] Figure 1 The first structure schematic diagram of the display panel provided by the present application.

[0026] Figure 2 The structure schematic diagram of the display panel provided by the present application. Figure 1 The structure schematic diagram of the display panel provided by the present application.

[0027] Figure 3 The second structure schematic diagram of the display panel provided by the present application.

[0028] Figure 4 The third structure schematic diagram of the display panel provided by the present application.

[0029] Figure 5 The flowchart of the manufacturing method of the display panel provided by the present application. DETAILED DESCRIPTION

[0030] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by a person of ordinary skill in the art without creative work fall within the protection scope of the present application.

[0031] In the description of the present application, it should be understood that the orientation or positional relationship indicated by the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise" and the like is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present application and simplifying the description, and does not indicate or imply that the indicated components or elements must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation of the present application. In addition, the terms "first", "second" are only for the purpose of description, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined with "first", "second" can explicitly or implicitly include one or more of the features. In the description of the present application, the meaning of "multiple" is two or more, unless otherwise explicitly and specifically limited.

[0032] The existing OLED display panel needs to set a via hole in the planar layer during the manufacturing process, and the via hole is easy to cause the deposited metal film layer to be uneven, resulting in a protrusion. In addition, the ITO layer trace under the anode is too thin, and the stress distribution is uneven due to the impact force during the cleaning process, which causes the ITO layer and the anode layer to split, and also causes the anode to break.

[0033] Therefore, in order to solve the above problems, the present application provides a display panel. The present application will be further described below in combination with the drawings and embodiments.

[0034] Please refer to Figure 1 , Figure 1A first structural schematic diagram of a display panel is provided in the embodiments of the present application. The embodiments of the present application provide a display panel 100, which comprises a substrate 110, a first planar layer 30, a first ITO layer 20 and an anode 10. The first planar layer 30 is arranged on one side of the substrate 110, and a first via hole 310 is arranged on the first planar layer 30. The first ITO layer 20 is arranged on a side of the first planar layer 30 away from the substrate 110. The anode 10 is arranged on a side of the first ITO layer 20 away from the first planar layer 30. The first ITO layer 20 is provided with a first groove 210, so that part of the anode 10 is arranged in the first groove 210, and a projection of the first groove 210 on the substrate 110 at least partially overlaps a projection of the first via hole 310 on the substrate 110.

[0035] It can be understood that the existing anode 10 appears to be convex because after the first via hole 310 is arranged on the first planar layer 30, part of the metal will be deposited when other metal film layers are arranged, so that the film layer deposited later will appear to be convex at the position corresponding to the first via hole 310, and thus the anode 10 will appear to be convex. Therefore, the embodiments of the present application arrange the first groove 210 on the first ITO layer 20, so that part of the anode 10 can be arranged in the first groove 210, thereby relieving the convexity of the anode 10, and the projection of the first groove 210 on the substrate 110 at least partially overlaps the projection of the first via hole 310 on the substrate 110, which better improves the convexity of the anode 10 caused by the first via hole 310, and solves the problem of breakage of the anode 10 in the manufacturing process.

[0036] The projection of the first groove 210 on the substrate 110 at least partially overlaps the projection of the first via hole 310 on the substrate 110, which is designed differently in different embodiments, and is specifically set according to actual conditions. For example, in some embodiments, the projection area of the first groove 210 on the substrate 110 can be greater than the projection area of the first via hole 310 on the substrate 110, so that the first groove 210 can accommodate part of the anode 10 to completely eliminate the existence of convexity. In some embodiments, under the condition that the first groove 210 can eliminate the convexity of the anode 10, the projection area of the first groove 210 on the substrate 110 can be completely overlapped with the projection area of the first via hole 310 on the substrate 110 to increase the connection area of the first ITO layer 20 and the anode 10. In other embodiments, when the metal substance deposited on the first via hole 310 is not much, that is, the convexity of the anode 10 is not large, under the condition that the first groove 210 can eliminate the convexity of the anode 10, the projection area of the first groove 210 on the substrate 110 can be less than the projection area of the first via hole 310 on the substrate 110 to increase the connection area of the first ITO layer 20 and the anode 10.

[0037] It can be understood that the groove depth of the first groove 210 is less than the thickness of the first ITO layer 20, that is, the first groove 210 is a blind hole, so as to avoid the anode 10 from being connected with the first flat layer 30 through the first groove 210.

[0038] Please continue to refer to Figure 2 , Figure 2 For Figure 1 The structure diagram of the first ITO layer provided with the first groove in the display panel is shown. In the display panel 100, in order to reduce the capacitance between the anode 10 and the driving transistor, the anode 10 is designed with a small tail, and the first ITO layer 20 wiring under the small tail 120 of the anode 10 is too thin, which may cause uneven stress distribution due to impact force in the cleaning process. Therefore, the first groove 210 provided on the first ITO layer 20 in the embodiment of the application is at the position corresponding to the small tail 120 of the anode 10, and the first groove 210 at least partially overlaps with the first via hole 310, so as to improve the uneven stress distribution, thereby solving the breaking between the anode 10 and the first ITO layer 20.

[0039] Specifically, the display panel 100 includes a plurality of pixels and driving transistors, the pixels are arranged on the side of the anode away from the first flat layer, the anode 10 includes a sub-anode of the smallest sub-pixel in each pixel, and the sub-anode includes a main body part and a connecting part (i.e. the small tail 120). Wherein, the orthographic projection of the main body part on the substrate is located in the orthographic projection of the driving transistor on the substrate, and part of the orthographic projection of the driving transistor on the substrate is located outside the orthographic projection of the connecting part (i.e. the small tail 120) on the substrate, that is, the main body part of the sub-anode is arranged above the driving transistor, and the connecting part (i.e. the small tail 120) of the sub-anode is arranged above part of the driving transistor. The first groove is arranged at the position corresponding to the connecting part (i.e. the small tail 120) of the first ITO layer.

[0040] Wherein, the shape of the connecting part (i.e. the small tail 120) can be a regular strip shape or a sheet shape, for example, a rectangular shape, and the shape of the connecting part (i.e. the small tail 120) can also be an irregular shape, which can be set according to actual conditions, and is not specifically limited here.

[0041] It should be noted that the smallest sub-pixel in each pixel can be the smallest sub-pixel of red, green and blue, for example, a G pixel, or the smallest sub-pixel of red, green, blue and white, or the smallest sub-pixel of red, green, blue and yellow, which can be set according to actual conditions, and is not specifically limited here.

[0042] It should be noted that the display panel 100 has a camera under panel (CUP) technology, the display panel 100 with the camera under panel has a CUP area and a normal display area, the CUP area is provided with an ITO trace and a PLN layer, and the normal display area is provided with the first ITO layer 20 and the anode 10. That is, the first ITO layer 20 provided with the first groove 210 in the present application is arranged in the normal display area.

[0043] Please continue to refer to Figure 3 and Figure 4 , Figure 3 The second structure schematic diagram of the display panel provided by the embodiment of the present application is shown in FIG. 2. Figure 4 The third structure schematic diagram of the display panel provided by the embodiment of the present application is shown in FIG. 3. The display panel 100 includes a second flat layer 50 and a second ITO layer 40, wherein the second flat layer 50 is arranged on the side of the first flat layer 30 away from the first ITO layer 20, and the second ITO layer 40 is arranged on the side of the second flat layer 50 close to the first ITO layer 20. In order to further improve the situation of the via hole being uneven, the second via hole 510 is arranged on the second flat layer 50, and the second groove 220 is arranged on the first ITO layer 20, so that part of the anode 10 is arranged in the second groove 220, and the projection of the second groove 220 on the substrate 110 at least partially overlaps the projection of the second via hole 510 on the substrate 110. By arranging the second groove 220 on the first ITO layer 20, the anode 10 can be partially arranged in the second groove 220, which relieves the situation of the anode 10 being raised, and the projection of the second groove 220 and the second via hole 510 on the substrate 110 at least partially overlaps, which better improves the situation of the anode 10 being raised due to the second via hole 510, and also solves the problem of the anode 10 being broken in the manufacturing process.

[0044] The display panel 100 further comprises a third planar layer 70 and a third ITO layer 60, the third ITO layer 60 is arranged on the side of the third planar layer 70 close to the first ITO layer 20, the third planar layer 70 is arranged on the side of the second planar layer 50 away from the first ITO layer 20, in order to further improve the uneven situation of the via hole, the third via hole 710 is arranged on the third planar layer 70, the third recess 230 is arranged on the first ITO layer 20, part of the anode 10 is arranged in the third recess 230, and the projection of the third recess 230 on the substrate 110 at least partially overlaps the projection of the third via hole 710 on the substrate 110. By arranging the third recess 230 on the first ITO layer 20, part of the anode 10 can be arranged in the third recess 230, the situation of the anode 10 protruding is alleviated, and the projection of the third recess 230 and the third via hole 710 on the substrate 110 at least partially overlaps, which better improves the situation of the anode 10 protruding due to the third via hole 710, and solves the problem of the anode 10 breaking during the manufacturing process.

[0045] The display panel 100 comprises a fourth planar layer 90, the fourth planar layer 90 is arranged on the side of the third planar layer 70 away from the first ITO layer 20, the fourth via hole 910 is arranged on the fourth planar layer 90, in order to further improve the uneven situation of the via hole, the fourth recess 240 is arranged on the first ITO layer 20, part of the anode 10 is arranged in the fourth recess 240, and the projection of the fourth recess 240 on the substrate 110 at least partially overlaps the projection of the fourth via hole 910 on the substrate 110. By arranging the fourth recess 240 on the first ITO layer 20, part of the anode 10 can be arranged in the fourth recess 240, the situation of the anode 10 protruding is alleviated, and the projection of the fourth recess 240 and the fourth via hole 910 on the substrate 110 at least partially overlaps, which better improves the situation of the anode 10 protruding due to the fourth via hole 910, and solves the problem of the anode 10 breaking during the manufacturing process.

[0046] The groove depth of the first groove 210, the groove depth of the second groove 220, the groove depth of the third groove 230, and the groove depth of the fourth groove 240 can be equal or not equal, and can be set according to actual conditions. For example, in some embodiments, the groove depth of the first groove 210, the groove depth of the second groove 220, the groove depth of the third groove 230, and the groove depth of the fourth groove 240 are equal, so that the first groove 210, the second groove 220, the third groove 230, and the fourth groove 240 can be prepared at the same time, thereby simplifying the process flow and saving costs. In some embodiments, the groove depth of the first groove 210, the groove depth of the second groove 220, the groove depth of the third groove 230, and the groove depth of the fourth groove 240 can be not equal, and can be designed according to the size of the first via hole 310, the size of the second via hole 510, the size of the third via hole 710, and the size of the fourth via hole 910, so as to accurately eliminate the protrusion of the anode 10 and prevent the problem of fracture between the anode 10 and the first ITO layer 20.

[0047] It should be noted that the groove depth of the second groove 220, the groove depth of the third groove 230, and the groove depth of the fourth groove 240 are all less than the thickness of the first ITO layer 20, that is, the second groove 220, the third groove 230, and the fourth groove 240 are all blind holes, so as to avoid the connection between the anode 10 and the first flat layer 30 through the first groove 210, the second groove 220, the third groove 230, or the fourth groove 240.

[0048] It can be understood that the first groove 210, the second groove 220, the third groove 230, and the fourth groove 240 do not overlap, because the first groove 210, the second groove 220, the third groove 230, and the fourth groove 240 are respectively arranged at different positions of the first ITO layer 20, that is, there are a first part for arranging the first groove 210, a second part for arranging the second groove 220, a third part for arranging the third groove 230, and a fourth part for arranging the fourth groove 240 on the first ITO layer 20, wherein the first part, the second part, the third part, and the fourth part are arranged apart from each other. Therefore, although the first groove 210, the second groove 220, the third groove 230, and the fourth groove 240 correspond to the positions of the first via hole 310, the second via hole 510, the third via hole 710, and the fourth via hole 910, even if the projections of the first via hole 310, the second via hole 510, the third via hole 710, and the fourth via hole 910 on the substrate 110 overlap on the first ITO layer, only grooves will appear at the positions corresponding to the via holes, and no grooves will appear at other positions. Therefore, when the projections of the first via hole 310, the second via hole 510, the third via hole 710, and the fourth via hole 910 on the substrate 110 overlap or do not overlap, the first groove 210, the second groove 220, the third groove 230, and the fourth groove 240 do not overlap.

[0049] It should be noted that the first groove 210, the second groove 220, the third groove 230 and the fourth groove 240 are all arranged below the small tail 120 of the anode 10 corresponding to the first ITO layer 20. By arranging the first groove 210, the second groove 220, the third groove 230 and the fourth groove 240 at this position, the protrusion of the anode 10 caused by the uneven via hole can be eliminated, and the situation that the first ITO layer 20 and the anode 10 are broken due to the uneven stress distribution caused by the impact force in the cleaning process can be avoided.

[0050] It should be noted that the depth of the first via hole 310, the depth of the second via hole 510, the depth of the third via hole 710 and the depth of the fourth via hole 910 can be equal or not equal. Specifically, the depth of the first via hole 310 is related to the thickness of the first flat layer 30, the depth of the second via hole 510 is related to the thickness of the second flat layer 50, the depth of the third via hole 710 is related to the thickness of the third flat layer 70, and the depth of the fourth via hole 910 is related to the thickness of the fourth flat layer 90. Therefore, the depth of the first via hole 310, the depth of the second via hole 510, the depth of the third via hole 710 and the depth of the fourth via hole 910 are set according to the actual situation, which is not limited here.

[0051] The display panel 100 further comprises a first metal layer 820 and a second metal layer 810, the first metal layer 820 is arranged on the side of the fourth flat layer 90 away from the third flat layer 70, and the second metal layer 810 is arranged between the fourth flat layer 90 and the third flat layer 70.

[0052] The display panel 100 further comprises a driving transistor, and the side of the partial region of the anode 10 covers the driving transistor, so as to reduce the parasitic capacitance formed by the anode 10 and the driving transistor.

[0053] The first ITO layer 20 is provided with the first groove 210, the second groove 220, the third groove 230 and the fourth groove 240, so that the anode 10 can be partially arranged in the first groove 210, the second groove 220, the third groove 230 and the fourth groove 240, thereby improving the situation that the anode 10 is protruded. In addition, the projection of the first via hole 310 on the substrate 110 and the projection of the first groove 210 on the substrate 110 are partially overlapped, the projection of the second via hole 510 on the substrate 110 and the projection of the second groove 220 on the substrate 110 are partially overlapped, the projection of the third via hole 710 on the substrate 110 and the projection of the third groove 230 on the substrate 110 are partially overlapped, and the projection of the fourth via hole 910 on the substrate 110 and the projection of the fourth groove 240 on the substrate 110 are partially overlapped, so that the protrusion of the anode 10 caused by the uneven via hole can be further eliminated, thereby avoiding the situation that the first ITO layer 20 and the anode 10 are broken due to the uneven stress distribution caused by the impact force in the cleaning process. Please continue to refer to Figure 5 , Figure 5 A flowchart of a manufacturing method of a display panel is provided in the embodiments of the present application. The embodiments of the present application also provide a manufacturing method of a display panel, and the display panel can be obtained by using the manufacturing method. The specific flow of the manufacturing method is as follows:

[0054] 101. A substrate is provided.

[0055] The substrate can be a flexible substrate or a glass substrate, which is specifically set according to the actual situation and is not specifically limited here.

[0056] 102. A first planar layer is arranged on one side of the substrate, and the first planar layer is provided with a first via hole.

[0057] In other embodiments, before the first planar layer is arranged on one side of the substrate, the following steps are further included:

[0058] First, a first metal layer is arranged on one side of the substrate.

[0059] Then, a fourth planar layer is arranged on the side of the first metal layer away from the substrate, and a fourth via hole is arranged on the fourth planar layer.

[0060] Then, a second metal layer is arranged on the side of the fourth planar layer away from the substrate.

[0061] Then, a third planar layer is arranged on the side of the second metal layer away from the substrate, and a third via hole is arranged on the third planar layer.

[0062] Then, a third ITO layer is arranged on the side of the third planar layer away from the substrate.

[0063] Then a second flat layer is arranged on the side of the third ITO layer away from the substrate, and a second via hole is arranged on the second flat layer.

[0064] Then a second ITO layer is arranged on the side of the second flat layer away from the substrate.

[0065] Then a first flat layer is arranged on the side of the second ITO layer away from the substrate, and a first via hole is arranged on the first flat layer.

[0066] The structure size and the correlation of the first via hole, the second via hole, the third via hole and the fourth via hole can be seen from the above, and will not be described here.

[0067] 103、The first ITO layer is arranged on the side of the first flat layer away from the substrate, and a first groove is arranged on the first ITO layer, and the projection of the first groove on the substrate at least partially overlaps the projection of the first via hole on the substrate.

[0068] It can be understood that in some other embodiments, a second groove corresponding to the second via hole, a third groove corresponding to the third via hole or a fourth groove corresponding to the fourth via hole is also arranged on the first flat layer. The specific arrangement can be seen from the above, and will not be described here.

[0069] 104、The anode is arranged on the side of the first ITO layer away from the first flat layer, and part of the anode is arranged in the first groove.

[0070] By arranging the first groove on the first ITO layer below the anode, and the orthographic projection of the first groove at least partially overlaps the orthographic projection of the first via hole, part of the anode can be arranged in the first groove, thereby the unevenness caused by the first via hole can be improved, and the stress distribution caused by the impact force in the cleaning process can be avoided, thereby the fracture of the first ITO layer 20 and the anode 10 can be avoided. In addition, in order to further improve this situation, a second groove corresponding to the second via hole, a third groove corresponding to the third via hole or a fourth groove corresponding to the fourth via hole can be arranged on the first ITO layer, so that the display effect of the display panel is better.

[0071] The display panel provided by the embodiments of the present application is described in detail above. In this paper, specific examples are applied to describe the principles and implementation modes of the present application, and the above embodiment description is only used to help understand the present application. Meanwhile, for those skilled in the art, according to the idea of the present application, the specific implementation mode and application range can be changed, and the above description should not be understood as a limitation of the present application.

Claims

1. A display panel, characterized in that, The display panel includes: substrate, A first planarization layer is disposed on one side of the substrate, and a first via is provided on the first planarization layer; A first ITO layer is disposed on the side of the first planarization layer away from the substrate; The anode is disposed on the side of the first ITO layer away from the first planarization layer; The first ITO layer is provided with a first groove so that a portion of the anode is disposed in the first groove, and the projection of the first groove on the substrate at least partially overlaps with the projection of the first via on the substrate.

2. The display panel according to claim 1, characterized in that, The projected area of ​​the first groove on the substrate is greater than the projected area of ​​the first via on the substrate.

3. The display panel according to claim 2, characterized in that, The depth of the first groove is less than the thickness of the first ITO layer.

4. The display panel according to claim 1, characterized in that, The display panel includes multiple pixels and driving transistors. The pixels are disposed on the side of the anode away from the first planarization layer. The anode includes a sub-anode of the smallest sub-pixel in each pixel. The sub-anode includes a main body and a connecting part. The orthographic projection of the main body on the substrate is located within the orthographic projection of the driving transistor on the substrate. The orthographic projection of the driving transistor on the substrate is located outside the orthographic projection of the connecting part on the substrate. The first groove is disposed in the first ITO layer at the position corresponding to the connecting part.

5. The display panel according to claim 4, characterized in that, The display panel further includes a second planarization layer, which is disposed on the side of the first planarization layer away from the first ITO layer. A second via is disposed on the second planarization layer, and a second groove is disposed on the first ITO layer, such that a portion of the anode is disposed in the second groove, and the projection of the second groove on the substrate at least partially overlaps with the projection of the second via on the substrate.

6. The display panel according to claim 5, characterized in that, The display panel further includes a third planarization layer, which is disposed on the side of the second planarization layer away from the first ITO layer. A third via is disposed on the third planarization layer, and a third groove is disposed on the first ITO layer, so that a portion of the anode is disposed in the third groove, and the projection of the third groove on the substrate at least partially overlaps with the projection of the third via on the substrate.

7. The display panel according to claim 6, characterized in that, The display panel includes a fourth planarization layer disposed on the side of the third planarization layer away from the first ITO layer. A fourth via is disposed on the fourth planarization layer, and a fourth groove is disposed on the first ITO layer, such that a portion of the anode is disposed in the fourth groove, and the projection of the fourth groove on the substrate at least partially overlaps with the projection of the fourth via on the substrate.

8. The display panel according to claim 7, characterized in that, The first groove, the second groove, the third groove, and the fourth groove do not overlap.

9. The display panel according to claim 7, characterized in that, The depths of the first groove, the second groove, the third groove, and the fourth groove are equal.

10. The display panel according to claim 7, characterized in that, The display panel further includes a first metal layer and a second metal layer, wherein the first metal layer is disposed on the side of the fourth planarization layer away from the third planarization layer, and the second metal layer is disposed between the fourth planarization layer and the third planarization layer.

11. The display panel according to claim 7, characterized in that, The display panel also includes: The second ITO layer is disposed on the side of the second planarization layer close to the first ITO layer; The third ITO layer is disposed on the side of the third planar layer close to the first ITO layer.

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