An Automatic Current Sharing Control Method Based on a Low-Voltage Ripple Interleaved Parallel High-Gain Converter

Abstract

In view of the problem that the low-voltage ripple interleaved parallel high-gain DC converter has a limited voltage gain range due to uneven current sharing under low duty cycle in the traditional interleaved parallel control method, an automatic current sharing control method based on the interleaved parallel high-gain DC converter is proposed. This control method is based on the ampere-second balance principle of the interleaved parallel phase switched capacitor. By changing the charging and discharging time of the intermediate boost capacitor, the magnitude of the inductor current of each phase is changed to achieve equal sharing of the inductor current of each phase. This current sharing control method does not introduce a new operating mode on the basis of the original circuit operating mode, and at the same time does not rely on current sensors for current sharing compensation feedback, nor does it require an increased control degree of freedom. Instead, on the basis of the traditional interleaved parallel control method, by adjusting the duty cycle and phase shift angle of each interleaved parallel phase, active current sharing of the interleaved parallel high-gain DC converter at low duty cycle is achieved, expanding the adjustable range of the input-output transformation ratio of the converter, enabling it to be applicable to wide input-output occasions, and is an economically feasible solution.

Description

Technical Field

[0001] The present invention belongs to the field of power electronics, and particularly relates to the application of current sharing control technology for interleaved parallel high-voltage gain DC-DC converters, especially in the field of converters for high-voltage and high-power electrical energy storage systems in the context of new energy power generation. Background Art

[0002] With the acceleration of the industrialization process in modern society, the demand for energy by humans is increasing day by day, and new energy power generation technologies using photovoltaic power generation and hydrogen energy power generation have been widely applied. However, photovoltaic and fuel cells usually obtain low-voltage and large-current direct current, which is difficult to be directly utilized and often needs to be boosted through a high-gain DC converter to obtain a voltage level that meets the load requirements. At the same time, in the battery energy storage system, a two-stage topology energy storage converter system is usually adopted. The maximum voltage gain of the traditional half-bridge bidirectional DC-DC converter is generally 4-5 times, which is difficult to meet the requirements of high-voltage and high-power level loads in industry. Therefore, the interleaved parallel technology is often used to parallel multiple power modules to meet the needs of high-power applications. However, due to the influence of non-ideal factors such as its structure and component manufacturing process in practice, the current sharing problem of each parallel phase occurs, resulting in an increase in the voltage stress of the converter and a reduction in the transmission efficiency. Therefore, in order to ensure the normal operation of the converter with an interleaved parallel structure, a suitable current sharing control method needs to be adopted to automatically balance the currents of the parallel phases of the converter and achieve automatic current sharing. To achieve equal sharing of the input currents of the interleaved parallel structure converter, relevant domestic and foreign researchers' research on the current sharing technology of interleaved parallel converters can be generally divided into two categories: droop method and active current sharing method. The droop method is an open-loop control, which has the advantages of being simple and easy to implement, but the current sharing effect is poor. The active current sharing method has a better current sharing effect, but the use of high-precision current sensors results in a high cost, and at the same time, the sensors need to be maintained and calibrated regularly. The current research hotspot is the active current sharing control technology without current sensors, but the existing current sharing control without current sensors often has the disadvantages of complex calculation and high equipment cost and is difficult to be applied in engineering. To sum up, there are still many technical problems to be solved in the existing current sharing control methods based on interleaved parallel converters in practical applications. Summary of the Invention

[0003] In order to overcome the problem that the input currents of each phase of the low-voltage ripple interleaved parallel high-voltage gain converter are not evenly distributed in the working range where the duty cycle is less than 2 / 3 by using traditional interleaved parallel control, resulting in a limited boost range of the converter, the present invention provides an automatic current sharing control method without any external auxiliary equipment for the problem that the current ratio range of the converter is narrow due to the uneven current of each phase in the low duty cycle range of the converter, so as to solve the problems in the related technologies.

[0004] The technical solution adopted by the present invention to solve its technical problems is as follows: In the uneven current sharing working range with a low duty cycle, by modifying the duty cycle and phase shift angle of the driving signal of a certain interleaved phase switching tube, the charging time and discharging time of the switching capacitor are adjusted, so that the current magnitude changes to achieve equal sharing, and the characteristic of the triple voltage gain of the circuit compared with the traditional boost converter is maintained. This current sharing control method is based on the duty cycle and phase shift angle of the driving signal of the converter switching tube, and does not require measuring the phase current value, so there is no need to additionally increase a current sensor.

[0005] The solution of the present invention is an automatic current sharing control method based on a low voltage ripple interleaved parallel high voltage gain converter. This method is applied to a three-phase series capacitor interleaved parallel DC converter with low voltage ripple interleaved parallel high voltage gain. Its circuit topology includes: phase A output inductor L1, phase A lower bridge arm switching tube S1, phase A upper bridge arm switching tube S2; phase B output inductor L2, phase B lower bridge arm switching tube S3, phase B upper bridge arm switching tube S4, switching capacitor C1, output filter capacitor C H1 ; phase C output inductor L3, phase C lower bridge arm switching tube S5, output filter capacitor C H2 ; and phase C upper bridge arm switching tube S6; In phase A, the positive pole of the power supply is connected to the inductor L1, and the other end of the inductor L1 is connected to the drain of the phase A lower bridge arm switching tube S1. The source of the lower bridge arm switching tube S1 is connected to the negative terminal of the power supply, and the gate is externally connected to the driving signal of S1. In addition, the common connection point of the phase A inductor L1 and the drain of the lower bridge arm switching tube S1 is connected to the source of the phase A upper bridge arm switching tube S2. The drain of the switching tube S2 is connected to the source of the phase B upper bridge arm switching tube S4. The drain of the upper bridge arm switching tube S4 is connected to the positive terminal of the output filter capacitor C H1 ; the negative terminal of the output filter capacitor C H1 is connected to the positive terminal of the output filter capacitor C H2 ; the negative terminal of the output filter capacitor C H2 is connected to the source of the phase C upper bridge arm switching tube S6, and the drain of the upper bridge arm switching tube S6 is connected to the negative terminal of the power supply; In phase B, the positive pole of the power supply is connected to the inductor L2, and the other end of the inductor L2 is connected to the drain of the phase B lower bridge arm switching tube S3. The source of the lower bridge arm switching tube S3 is connected to the negative terminal of the power supply. In addition, the common connection point of the phase B inductor L2 and the drain of the lower bridge arm switching tube S3 is connected to the negative terminal of the switching capacitor C1. The positive terminal of the switching capacitor C1 is connected to the common connection point of the source of the switching tube S2 (located in the phase A upper bridge arm) and the drain of the switching tube S4 (located in the phase B upper bridge arm); In phase C, the positive pole of the power supply is connected to the inductor L3, and the other end of the inductor L3 is connected to the drain of the phase C lower bridge arm switching tube S5. The source of the lower bridge arm switching tube S5 is connected to the negative terminal of the power supply. In addition, the common connection point of the phase C inductor L3 and the drain of the lower bridge arm switching tube S5 is connected to the common connection point of the negative terminal of the output filter capacitor C H1 and the positive terminal of the output filter capacitor C H2 ;

[0006] The described automatic current sharing control method based on a low-voltage ripple interleaved parallel high-gain converter includes:

[0007] Dividing four working intervals based on different duty cycles of the converter operation;

[0008] For the described working intervals, analyze the magnitudes of the interleaved parallel phase currents in the converter operation mode under traditional interleaved parallel control. By adjusting the duty cycles and phase-shift angles of the driving signals of the lower-bridge-arm switching tubes of each phase, further control the charging and discharging times of the interleaved parallel phase switching capacitors to ensure equal sharing of each phase current.

[0009] The described automatic current sharing control method based on a low-voltage ripple interleaved parallel high-gain converter divides the working intervals of the converter into four working intervals and adopts different current sharing control methods according to different operation modes of the converter at different duty cycles, namely working interval 1 (2 / 3 ≤ D < 1), working interval 2 (1 / 3 ≤ D < 2 / 3), working interval 3 (1 / 5 ≤ D < 1 / 3), and working interval 2 (1 / 3 ≤ D < 2 / 3), where D is the duty cycle.

[0010] The present invention belongs to the field of power electronics, and specifically relates to the application of current sharing control technology for interleaved parallel high-voltage gain DC-DC converters, especially in the technical field of converters for high-voltage high-power electrical energy storage systems in the context of new energy power generation.

[0011] For the current sharing control method corresponding to the division of each working interval of the converter, in working interval 1 (2 / 3 ≤ D < 1), the driving signals of converter switching tubes S1, S3, and S5 adopt PWM signals with a phase shift of 120° in sequence and a duty cycle of D. The driving signals of switching tubes S2, S4, and S6 are complementary to the driving signals of switching tubes S1, S3, and S5 and a dead time is set. At this time, the voltage gain range is: M ≥ 9.

[0012] For the current sharing control method corresponding to the division of each working interval of the converter, in working interval 1 (1 / 3 ≤ D < 2 / 3), the driving signals of converter switching tubes S1, S3, and S5 are staggered by 120° in sequence. The driving signal of switching tube S1 in phase A is a PWM signal with a duty cycle of D, and the driving signals of switching tubes S3 and S5 in phases B and C are PWM signals with a duty cycle of D / 2 + 1 / 3. The driving signals of switching tubes S2, S4, and S6 are complementary to the driving signals of switching tubes S1, S3, and S5 and a dead time is set. At this time, the voltage gain range is: 4.5 ≤ M < 9.

[0013] For the current sharing control method corresponding to each working interval division of the converter, in working interval 1 (1 / 5 ≤ D < 1 / 3), the phase shift angle of switch S1 of the converter is 0°, the PWM signal with a duty cycle of D, the phase shift angle of switch S3 in phase B is 2πD, the PWM signal with a duty cycle of 1 / 2, the phase shift angle of switch S5 in phase C is 2πD + π, the PWM signal with a duty cycle of D + 1 / 10. The drive signals of switches S2, S4, and S6 are complementary to the drive signals of switches S1, S3, and S5 and a dead time is set. The voltage gain range at this time is: 3.75 ≤ M < 4.5.

[0014] For the current sharing control method corresponding to each working interval division of the converter, in working interval 1 (0 < D < 1 / 5), the phase shift angle of switch S1 of the converter is 0°, the PWM signal with a duty cycle of D, the phase shift angle of switch S3 in phase B is 2πD + (1 / 5 - D)πD, the PWM signal with a duty cycle of 1 / 2, the phase shift angle of switch S5 in phase C is 240°, the fixed PWM signal with a duty cycle of 3 / 10. The drive signals of switches S2, S4, and S6 are complementary to the drive signals of switches S1, S3, and S5 and a dead time is set. The voltage gain range at this time is: M < 3.75.

[0015] For the current sharing control method corresponding to each working interval division, the converter realizes automatic current sharing in the full duty cycle working range, that is, the three-phase current of the converter is evenly divided. At the same time, the output voltage gain M of the converter is M = 3 / (1 - D).

[0016] Under the control method of the present invention, the charging and discharging time of the switched capacitors C1 in phases A and B is adjusted through the charge conservation of the capacitors. By changing the duty cycle and phase shift angle of the drive signals of the switches in phases A and B, the input current of phase A is made equal to the input current of phase B. Correspondingly, by changing the duty cycle and phase shift angle of the drive signal of the switch in phase C, the input currents of the three phases are evenly divided.

[0017] Compared with the prior art, the beneficial effects of the present invention are:

[0018] First, the control scheme operates in the original circuit working mode. The present invention only adjusts the duty cycle and phase shift angle of the drive signals of the converter switches, does not require additional control freedoms, does not require measuring the phase current value, and therefore does not require additional current sensors.

[0019] Second, the present invention realizes the equal division of the input currents of each phase in the low duty cycle working interval of 0 < D < 2 / 3 of the converter, maintains the output voltage 3-fold gain characteristic of the converter compared with the traditional boost converter, expands the input-output voltage ratio range of the converter, and thus expands the circuit stability and application range.

[0020] III. By adjusting the duty cycle of the driving signals of the switching tubes in phases B and C of the circuit or fixing the duty cycle to make the duty cycle larger, the losses of the switching tubes in phases B and C are reduced. Therefore, the circuit losses are reduced to a certain extent, and the working efficiency of the converter is improved. Description of the Drawings

[0021] The present invention will be further described below in conjunction with the drawings and specific embodiments:

[0022] Figure 1 is the circuit topology diagram of the low-voltage ripple interleaved parallel high-gain converter;

[0023] Figure 2 is the timing diagram of the low-voltage ripple interleaved parallel high-gain converter in the working range of 0 < D < 1 under traditional interleaved parallel control;

[0024] Figure 3 are the 8 working modes of the low-voltage ripple interleaved parallel high-gain converter;

[0025] Figure 4 is the timing diagram of the low-voltage ripple interleaved parallel high-gain converter in the working range of 0 < D < 2 / 3 under the current sharing control strategy; Figure 5 is the simulation waveform of the low-voltage ripple interleaved parallel high-gain converter and the working range of 0 < D < 1 under the traditional control method; Figure 6 is the simulation waveform of the low-voltage ripple interleaved parallel high-gain converter and the working range of 0 < D < 2 / 3 under the automatic current sharing control method; Specific Embodiments

[0026] The automatic current sharing control method based on the low-voltage ripple interleaved parallel high-gain converter of the present invention will be further described in detail below in conjunction with the drawings and specific embodiments.

[0027] The present invention provides an automatic current sharing control method based on a low-voltage ripple interleaved parallel high-gain converter. This method is applied to a three-phase series capacitor interleaved parallel DC converter with low-voltage ripple interleaved parallel high voltage gain, such as Figure 1 shown. The circuit topology of this converter includes: phase A output inductor L1, phase A lower bridge arm switching tube S1, phase A upper bridge arm switching tube S2; phase B output inductor L2, phase B lower bridge arm switching tube S3, phase B upper bridge arm switching tube S4, switching capacitor C1, output filter capacitor C H1 ; phase C output inductor L3, phase C lower bridge arm switching tube S5, output filter capacitor C H2; the upper-bridge-arm switch S6 of phase C; in phase A, the positive pole of the power supply is connected to the inductor L1, and the other end of the inductor L1 is connected to the drain of the lower-bridge-arm switch S1 of phase A. The source of the lower-bridge-arm switch S1 is connected to the negative terminal of the power supply, and the gate is externally connected to the driving signal of S1. In addition, at the common connection point of the inductor L1 of phase A and the drain of the lower-bridge-arm switch S1, the source of the upper-bridge-arm switch S2 of phase A is connected. The drain of the switch S2 is connected to the source of the upper-bridge-arm switch S4 of phase B, and the drain of the upper-bridge-arm switch S4 is connected to the positive terminal of the output filter capacitor C H1 ; the positive terminal of the output filter capacitor C H1 ; the negative terminal of the output filter capacitor C H2 ; the positive terminal of the output filter capacitor C H2 ; the negative terminal of the output filter capacitor C is connected to the source of the upper-bridge-arm switch S6 of phase C, and the drain of the upper-bridge-arm switch S6 is connected to the negative terminal of the power supply; in phase B, the positive pole of the power supply is connected to the inductor L2, and the other end of the inductor L2 is connected to the drain of the lower-bridge-arm switch S3 of phase B. The source of the lower-bridge-arm switch S3 is connected to the negative terminal of the power supply. In addition, at the common connection point of the inductor L2 of phase B and the drain of the lower-bridge-arm switch S3, the negative terminal of the switching capacitor C1 is connected, and the positive terminal of the switching capacitor C1 is connected to the common connection point of the source of the switch S2 (located in the upper bridge arm of phase A) and the drain of the switch S4 (located in the upper bridge arm of phase B); in phase C, the positive pole of the power supply is connected to the inductor L3, and the other end of the inductor L3 is connected to the drain of the lower-bridge-arm switch S5 of phase C. The source of the lower-bridge-arm switch S5 is connected to the negative terminal of the power supply. In addition, at the common connection point of the inductor L3 of phase C and the drain of the lower-bridge-arm switch S5, it is connected to the negative terminal of the output filter capacitor C H1 ; the negative terminal of the output filter capacitor C H2 ; the positive terminal of the output filter capacitor C

[0028] See Figure 2 ; Figure 3 ; Figure 4 Analyze the working modes of the above converter under the current sharing control strategy:

[0029] As Figure 2 shown, the three-phase low-voltage ripple interleaved parallel high-gain converter is divided into 3 working intervals according to different duty cycles under the traditional interleaved parallel control strategy, namely: working interval 1 (2 / 3 ≤ D < 1), working interval 2 (1 / 3 ≤ D < 2 / 3), and working interval 3 (0 < D < 1 / 3).

[0030] For working interval 1 (2 / 3 ≤ D < 1), the input currents of each parallel phase are automatically evenly divided. The voltage gain range of the converter at this time is: M ≥ 9. For this, no current sharing operation is required. Adopt the traditional interleaved parallel control method. As Figure 2 (1) shown, the driving signals of the switches of each phase are staggered by 120° in sequence, and the duty cycles are equal.

[0031] For working interval 2 (1 / 3 ≤ D < 2 / 3), asFigure 2 (2), Figure 3 As shown, the circuit has a total of 6 operating modes under the traditional interleaved parallel current sharing control timing:

[0032] (1) Mode 1, S1S3S5 = 101, as Figure 3 (3) shown, the control timing corresponds to Figure 2 (2) the t0 - t1 stage, with a time occupancy of (D - 1 / 3)T. The inductor L1 of phase A and the inductor L3 of phase C are directly connected to the power supply through switches S1 and S5. The inductors L1 and L3 are in the charging state, and the inductor L2 of phase B charges the switching capacitor C1 and the output capacitor C H1 charges the output capacitor C H1 and C H2 discharges to the load to achieve step-up.

[0033] (2) Mode 2, S1S3S5 = 100, as Figure 3 (8) shown, the control timing corresponds to Figure 2 (2) the t1 - t2 stage, with a time occupancy of (2 / 3 - D)T. The inductor L1 of phase A is directly connected to the power supply through switch S1. The inductor L1 is in the charging state, and the inductor L2 of phase B charges the switching capacitor C1 and the output capacitors C H1 and C H2 charges the inductor L3 of phase C to charge the output capacitor C H2 charges the output capacitor C H1 and C H2 discharges to the load to achieve step-up.

[0034] (3) Mode 3, S1S3S5 = 110, as Figure 3 (2) shown, the control timing corresponds to Figure 2 (2) the t2 - t3 stage, with a time occupancy of (D - 1 / 3)T. The inductor L1 of phase A and the inductor L2 of phase B are directly connected to the power supply through switches S1 and S3. The inductors L1 and L2 are in the charging state, and the inductor L3 of phase C charges the output C H2 charges the output capacitor C H1 and C H2 discharges to the load to achieve step-up.

[0035] (4) Mode 4, S1S3S5 = 010, as Figure 3 (7) shown, the control timing corresponds to Figure 2 (2) the t3 - t4 stage, with a time occupancy of (2 / 3 - D)T. The inductor L1 of phase A and the inductor L2 of phase B are directly connected to the power supply through switches S1 and S3. The inductors L1 and L2 are in the charging state, and the inductor L3 of phase C charges the output C H2 charges the output capacitor C H1 and C H2 discharges to the load to achieve step-up.

[0036] (5) Mode 5, S1S3S5 = 011, as shown in Figure 3 (6), the control timing corresponds to Figure 2 (2) in the t4 - t5 stage, the time occupied is (D - 1 / 3)T. The inductors L2 of phase B and L3 of phase C are directly connected to the power supply through switches S3 and S5, and the inductors L2 and L3 are in the charging state. The inductor L1 of phase A charges the switched capacitor C1, and the output capacitor C H1 、C H2 discharges to the load to achieve voltage boost.

[0037] (6) Mode 6, S1S3S5 = 001, as shown in Figure 3 (5), the control timing corresponds to Figure 2 (2) in the t5 - t6 stage, the time occupied is (2 / 3 - D)T. The inductor L3 of phase C is directly connected to the power supply through switch S5, and the inductor L3 is in the charging state. The inductor L1 of phase A charges the output C H1 、C H2 charges, the inductor L2 of phase B charges the switched capacitor C1, the output C H1 、C H2 charges, and the output capacitors C H1 、 C H2 discharge to the load to achieve voltage boost.

[0038] For the working range (1 / 3 ≤ D < 2 / 3), current sharing control is adopted. As shown in Figure 4 (1), the specific current sharing control strategy is as follows: The duty cycle of the lower - arm switch tube S1 of phase A is D, and the phase - shift angle is 0°. The duty cycle of the lower - arm switch tube S3 of phase B is D / 2 + 1 / 3, and the phase - shift angle is 120°. The duty cycle of the lower - arm switch tube S5 of phase C is D / 2 + 1 / 3, and the phase - shift angle is 240°. The corresponding upper - arm switches of each phase conduct complementarily. The working modes of the circuit here are:

[0039] (1) Mode 1, S1S3S5 = 101, the control timing corresponds to Figure 4 (1) in the t0 - t1 stage, the time occupied is (D / 2)T.

[0040] (2) Mode 2, S1S3S5 = 100, the control timing corresponds to Figure 4 (1) in the t1 - t2 stage, the time occupied is (1 / 3 - D / 2)T.

[0041] (3) Mode 3, S1S3S5 = 110, the control timing corresponds to Figure 4 (1) in the t2 - t3 stage, the time occupied is (D - 1 / 3)T.

[0042] (4) Mode 4, S1S3S5 = 010, the control timing corresponds toFigure 4 In the t3 - t4 stage of (1), the time taken is (2 / 3 - D)T.

[0043] (5) Mode 5, S1S3S5 = 011, the control timing corresponds to Figure 4 In the t4 - t5 stage of (1), the time taken is (D / 2)T.

[0044] (6) Mode 6, S1S3S5 = 001, the control timing corresponds to Figure 4 In the t5 - t6 stage of (1), the time taken is (1 / 3 - D / 2)T.

[0045] Under this current sharing control strategy, the charging and discharging times of the switching capacitor C1 are the same, ensuring that the input current I1 of phase A and the input current I2 of phase B are evenly divided. At the same time, from the charge balance of the circuit, when I1 = I2, since the action time of I3 is the same as the sum of the action times of I1 and I2, the current of each phase can be evenly divided. The voltage gain range in this working interval is: 4.5 ≤ M < 9.

[0046] For the working interval 3 (0 < D < 1 / 3), as Figure 2 (3), Figure 3 shown, the circuit has a total of 4 working modes under the traditional interleaved parallel current sharing control timing:

[0047] (1) Mode 1, S1S3S5 = 100, as Figure 3 (8) shown, the control timing corresponds to Figure 2 In the t0 - t1 stage of (3), the time taken is D. The inductor L1 of phase A is directly connected to the power supply through the switch S1, and the inductor L1 is in the charging state. The inductor L2 of phase B charges the switching capacitor C1 and the output capacitor C H1 , C H2 , and the inductor L3 of phase C charges the output capacitor C H2 . The output capacitors C H1 , C H2 discharge to the load to achieve step - up.

[0048] (2) Mode 2, S1S3S5 = 000, as Figure 3 (4) shown, the control timing corresponds to Figure 2 In the t1 - t2, t3 - t4, and t5 - t6 stages of (3), the total time taken is 1 - 3D. The inductor L1 of phase A discharges to the output capacitors C H1 , C H2 and supplies power to the load through the switches S2, S4, and S6. The inductor L2 of phase B charges the output capacitors C H1 , C H2 through the switches S4 and S6. The inductor L3 of phase C charges the output capacitor C H2During charging, the three-phase inductors L1, L2, and L3 are all in the discharging state. The output capacitors C H1 , C H2 discharge the load to achieve step-up.

[0049] (3) Mode 3, S1S3S5 = 010, as shown in Figure 3 (7), the control timing corresponds to Figure 2 the t2 - t3 stage in (3), and the occupied time is D. The B-phase inductor L2 is directly connected to the power supply through the switch S3, and the inductor L2 is in the charging state. The A-phase inductor L1 charges the switched capacitor C1, and the C-phase inductor L3 charges the output capacitor C H2 . The output capacitor C H1 , C H2 discharge the load to achieve step-up.

[0050] (4) Mode 4, S1S3S5 = 001, as shown in Figure 3 (5), the control timing corresponds to Figure 2 the t4 - t5 stage in (3), and the occupied time is D. The C-phase inductor L3 is directly connected to the power supply through the switch S5, and the inductor L3 is in the charging state. The A-phase inductor L1 charges the output capacitors C H1 , C H2 , the B-phase inductor L2 charges the switched capacitor C1 and the output capacitors C H1 , C H2 . The output capacitor C H1 , C H2 discharge the load to achieve step-up.

[0051] In the working interval 3 (0 < D < 1 / 3), current sharing control is adopted and needs to be further subdivided as follows:

[0052] For the working interval (1 / 5 ≤ D < 1 / 3), current sharing control is adopted. As shown in Figure 4 (2), the specific current sharing control strategy is: the duty cycle of the lower-arm switch tube S1 of the A-phase is D, the phase shift angle is 0°, the duty cycle of the lower-arm switch tube S3 of the B-phase is 1 / 2, the phase shift angle is 2πD, the duty cycle of the lower-arm switch tube S5 of the C-phase is D + 1 / 10, the phase shift angle is (2D + 1)π, and the corresponding upper-arm switches of each phase are complementary-conducted. The working modes of the circuit here are:

[0053] (1) Mode 1, S1S3S5 = 101, the control timing corresponds to Figure 4 the t0 - t1 stage in (2), and the occupied time is (2D - 2 / 5)T.

[0054] (2) Mode 2, S1S3S5 = 100, the control timing corresponds to Figure 4 the t1 - t2 stage in (2), and the occupied time is (2 / 5 - D)T.

[0055] (3) Mode 3, S1S3S5 = 010, and the control timing corresponds to Figure 4 the t2 - t3 stage in (2), and the time occupied is T / 2.

[0056] (4) Mode 4, S1S3S5 = 001, and the control timing corresponds to Figure 4 the t3 - t4 stage in (2), and the time occupied is (1 / 2 - D)T.

[0057] Under this current sharing control strategy, it is ensured that the charging and discharging times of the switching capacitor C1 are both 1 / 2, ensuring that the input current I1 of phase A and the input current I2 of phase B are evenly divided. At the same time, based on the charge balance of the circuit, the charging and discharging times of the inductor L3 of phase C are adjusted to ensure equality with the input inductor currents of phases AB, realizing the equal division of each phase current. The voltage gain range in this working interval is: 3.75 ≤ M < 4.5.

[0058] For the working interval (0 < D < 1 / 5), current sharing control is adopted, as Figure 4 shown in (3). The specific current sharing control strategy is as follows: The duty cycle of the lower - arm switch tube S1 of phase A is D, and the phase - shift angle is 0°. The duty cycle of the lower - arm switch tube S3 of phase B is 1 / 2, and the phase - shift angle is 2πD+(1 / 5 - D) / 2. The duty cycle of the lower - arm switch tube S5 of phase C is 1 / 3, and the phase - shift angle is 240°. The corresponding upper - arm switches of each phase conduct complementarily. The working modes of the circuit here are:

[0059] (1) Mode 1, S1S3S5 = 100, and the control timing corresponds to Figure 4 the t0 - t1 stage in (3), and the time occupied is DT.

[0060] (2) Mode 2, S1S3S5 = 000, and the control timing corresponds to Figure 4 the t1 - t2 and t3 - t4 stages in (3), and the time occupied is (1 / 5 - D)T.

[0061] (3) Mode 3, S1S3S5 = 010, and the control timing corresponds to Figure 4 the t2 - t3 stage in (3), and the time occupied is T / 2.

[0062] (4) Mode 4, S1S3S5 = 001, and the control timing corresponds to Figure 4 the t4 - t5 stage in (3), and the time occupied is 3T / 10.

[0063] Under this current sharing control strategy, it is ensured that the charging and discharging times of the switching capacitor C1 are both 1 / 2, ensuring that the input current I1 of phase A and the input current I2 of phase B are evenly divided. At the same time, based on the charge balance of the circuit, the charging and discharging times of the inductor L3 of phase C are adjusted to ensure equality with the input inductor currents of phases A and B, achieving equal division of currents in each phase. The voltage gain range in this operating interval is: M < 3.75.

[0064] Simulation analysis results:

[0065] Figure 5 、 Figure 6 is the simulation waveform of the switching period of the embodiment, and its circuit simulation parameters are: the input-side power supply voltage V in = 10V, the load resistance R L = 5Ω, the switching capacitor C1 = 660uF, the output capacitor C H1 = C H2 = 660uF, the inductors L1 = L2 = L3 = 1000uH. It can be Figure 6 seen that in the low duty cycle (0 < D < 2 / 3) operating range, the automatic current sharing control method can achieve equal division of currents in each phase. Figure 5 is the simulation waveform of the converter under traditional interleaved parallel control in the 0 < D < 1 operating range, Figure 5 (1), Figure 5 (2), Figure 5 (3) corresponding duty cycles are D = 0.7, D = 0.5, D = 0.3 respectively. In the 0 < D < 2 / 3 operating range, traditional interleaved parallel control cannot achieve equal division of currents in each phase and cannot achieve a 3-fold output voltage gain boost in the full duty cycle range. The corresponding output voltages are 99.7V, 50.4V, and 28.9V respectively. It can be Figure 6 known that in the low duty cycle (0 < D < 2 / 3) operating range, automatic current sharing effect of currents in each phase and a 3-fold output voltage gain boost in the full duty cycle range are achieved, Figure 6 (1), Figure 6 (2), Figure 6 (3) corresponding duty cycles are D = 0.5, D = 0.3, D = 0.1 respectively, and the corresponding output voltages are 60V, 42.7V, and 33.3V respectively.

[0066] In summary, the current sharing strategy proposed by the present invention can achieve equal sharing of phase currents in the low duty cycle range. This current sharing control method does not introduce a new operating mode based on the original circuit operating mode. At the same time, it does not rely on current sensors for current sharing compensation feedback, nor does it require an increased control degree of freedom. Based on the traditional interleaved parallel control method, by adjusting the duty cycle and phase shift angle of each interleaved parallel phase, active current sharing of the interleaved parallel high-gain DC converter at low duty cycles is achieved, expanding the adjustable range of the input-output voltage ratio of the converter, enabling it to be applicable to wide input-output scenarios, and is an efficient and low-cost solution.

[0067] The above are only embodiments of the present invention, and the present invention is not limited thereto. Any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention still belong to the protection scope of the technical solution of the present invention. For the interpretation of the content of the claims.

Claims

1. An automatic current sharing control method based on a low-voltage ripple interleaved parallel high-gain converter, characterized in that The method is applied to a three-phase series-capacitor interleaved DC converter with low-voltage ripple and interleaved parallel high-voltage gain. Its circuit topology includes: the output inductor L1 of phase A, the lower-arm switch S1 of phase A, and the upper-arm switch S2 of phase A; the output inductor L2 of phase B, the lower-arm switch S3 of phase B, the upper-arm switch S4 of phase B, the switching capacitor C1, and the output filter capacitor CH1; the output inductor L3 of phase C, the lower-arm switch S5 of phase C, the output filter capacitor CH2; and the upper-arm switch S6 of phase C. In phase A, the positive pole of the power supply is connected to the inductor L1, and the other end of the inductor L1 is connected to the drain of the lower-arm switch S1 of phase A. The source of the lower-arm switch S1 is connected to the negative end of the power supply, and the gate is externally connected to the driving signal of S1. In addition, the common connection point of the inductor L1 of phase A and the drain of the lower-arm switch S1 is connected to the source of the upper-arm switch S2 of phase A. The drain of the switch S2 is connected to the source of the upper-arm switch S4 of phase B. The drain of the upper-arm switch S4 is connected to the positive end of the output filter capacitor CH1. The negative end of the output filter capacitor CH1 is connected to the positive end of the output filter capacitor CH2. The negative end of the output filter capacitor CH2 is connected to the source of the upper-arm switch S6 of phase C. The drain of the upper-arm switch S6 is connected to the negative pole of the power supply. In phase B, the positive pole of the power supply is connected to the inductor L2, and the other end of the inductor L2 is connected to the drain of the lower-arm switch S3 of phase B. The source of the lower-arm switch S3 is connected to the negative end of the power supply. In addition, the common connection point of the inductor L2 of phase B and the drain of the lower-arm switch S3 is connected to the negative end of the switching capacitor C1. The positive end of the switching capacitor C1 is connected to the common connection point of the source of the switch S2 and the drain of the switch S4. In phase C, the positive pole of the power supply is connected to the inductor L3, and the other end of the inductor L3 is connected to the drain of the lower-arm switch S5 of phase C. The source of the lower-arm switch S5 is connected to the negative end of the power supply. In addition, the common connection point of the inductor L3 of phase C and the drain of the lower-arm switch S5 is connected to the common connection point of the negative end of the output filter capacitor CH1 and the positive end of the output filter capacitor CH2; The automatic current sharing control method based on a low-voltage ripple interleaved parallel high-gain converter includes: Dividing four working intervals based on different duty cycles of the converter; For the working intervals, analyzing the magnitudes of the interleaved parallel phase currents in the working modes of the converter under traditional interleaved parallel control, and controlling the charging and discharging times of the interleaved parallel phase switching capacitors by adjusting the duty cycle and phase-shift angle of the driving signals of the lower-arm switches of each phase to ensure equal sharing of each phase current.

2. An automatic current sharing control method for a low-voltage ripple interleaved parallel high-gain converter according to claim 1, characterized in that: According to the working modes corresponding to different duty cycles of the converter, dividing the working intervals of the converter into four working intervals and adopting different current sharing control methods. The specific division of the working intervals is as follows: ① When the preset duty cycle signal D of the converter switch is in the range of [2 / 3, 1), it corresponds to working interval 1; ② When the preset duty cycle signal D of the converter switch is in the range of [1 / 3, 2 / 3), it corresponds to working interval 2; ③ When the preset duty cycle signal D of the converter switch is in the range of [1 / 5, 1 / 3), it corresponds to working interval 3; ④When the preset duty cycle signal D of the converter switching tube is in (0, 1 / 5), it corresponds to the working interval 4.

3. An automatic current sharing control method for a low-voltage ripple interleaved parallel high-gain converter according to claim 2, characterized in that, When the preset duty cycle signal D of the converter switching tube is in [2 / 3, 1), it corresponds to the working interval 1. The driving signals of the converter switching tubes S1, S3, and S5 adopt PWM signals with a 120° staggered sequence in turn and a duty cycle of D. The driving signals of the switching tubes S2, S4, and S6 are complementary to the driving signals of the switching tubes S1, S3, and S5 and a dead time is set. At this time, the voltage gain range is: M ≥ 9.

4. An automatic current sharing control method for a low-voltage ripple interleaved parallel high-gain converter according to claim 2, characterized in that, When the preset duty cycle signal D of the converter switching tube is in [1 / 3, 2 / 3), it corresponds to the working interval 2. The driving signals of the converter switching tubes S1, S3, and S5 are in a 120° staggered sequence in turn. The switching tube S1 of phase A is a PWM signal with a duty cycle of D, and the switching tubes S3 and S5 of phase B and phase C are PWM signals with a duty cycle of D / 2 + 1 / 3. The driving signals of the switching tubes S2, S4, and S6 are complementary to the driving signals of the switching tubes S1, S3, and S5 and a dead time is set. At this time, the voltage gain range is: 4.5 ≤ M < 9.

5. An automatic current sharing control method for a low-voltage ripple interleaved parallel high-gain converter according to claim 2, characterized in that, When the preset duty cycle signal D of the converter switching tube is in [1 / 5, 1 / 3), it corresponds to the working interval 3. The phase shift angle of the switching tube S1 of the converter is 0°, and it is a PWM signal with a duty cycle of D. The phase shift angle of the switching tube S3 of phase B is 2πD, and it is a PWM signal with a duty cycle of 1 / 2. The switching tube S5 of phase C has a phase shift angle of 2πD + π and is a PWM signal with a duty cycle of D + 1 / 10. The driving signals of the switching tubes S2, S4, and S6 are complementary to the driving signals of the switching tubes S1, S3, and S5 and a dead time is set. At this time, the voltage gain range is: 3.75 ≤ M < 4.

5.

6. The automatic current sharing control method for a low-voltage ripple interleaved parallel high-gain converter according to claim 2, wherein When the preset duty cycle signal D of the converter switching tube is in (0, 1 / 5), it corresponds to the working interval 4. The phase shift angle of the switching tube S1 of the converter is 0°, and it is a PWM signal with a duty cycle of D. The phase shift angle of the switching tube S3 of phase B is 2πD + (1 / 5 - D)πD, and it is a PWM signal with a duty cycle of 1 / 2. The switching tube S5 of phase C has a phase shift angle of 240° and is a fixed PWM signal with a duty cycle of 3 / 10. The driving signals of the switching tubes S2, S4, and S6 are complementary to the driving signals of the switching tubes S1, S3, and S5 and a dead time is set. At this time, the voltage gain range is: M < 3.

75.

7. An automatic current sharing control method for a low-voltage ripple interleaved parallel high-gain converter according to claim 2, characterized in that The converter realizes automatic current sharing in the full duty cycle working range, that is, it realizes the equal division of the three-phase current of the converter. At the same time, the output voltage gain M of the converter is 3 / (1 - D).

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