Control circuit for improving transient response of a voltage reduction circuit

Abstract

The present disclosure relates to a control circuit for improving transient response of a buck circuit during load switching. The control circuit comprises: an upper transistor conduction control unit configured to obtain a delay mode control signal according to a first reference voltage and a feedback voltage of the buck circuit, and obtain an upper transistor conduction signal according to the delay mode control signal and a duty cycle of the buck circuit, so as to control an off time of an upper transistor; a lower transistor conduction control unit configured to obtain a lower transistor conduction signal according to the feedback voltage, a second reference voltage and the delay mode control signal, so as to control an on time of the upper transistor; and a control signal output unit connected with the upper transistor conduction control unit and the lower transistor conduction control unit, and configured to control the on and off of the upper transistor and a lower transistor of the buck circuit according to the upper transistor conduction signal and the lower transistor conduction signal. According to the present disclosure, the transient response of the buck circuit during load switching can be improved according to the duty cycle of the buck circuit.

Description

Technical Field

[0001] This disclosure generally relates to the field of power management technology. More specifically, this disclosure relates to control circuits for improving the load-switching transient response of buck converters. Background Technology

[0002] With the increasing demand for power, voltage converters have developed rapidly and are widely used in various electronic devices, daily lighting, and household appliances. Among them, the BUCK circuit is one of the most commonly used circuits. For the BUCK circuit, when the output switches from a light load (e.g., inductor current of 0A) to a heavy load (e.g., inductor current of 5A), the inductor current cannot increase in time, resulting in the average inductor current being less than the current required by the load, which leads to a drop in output voltage. The average inductor current takes a long time to recover, resulting in poor dynamic response.

[0003] However, existing technologies cannot effectively control the rapid recovery of inductor current. Summary of the Invention

[0004] In order to at least partially solve the technical problems mentioned in the background art, the present disclosure provides a control circuit for improving the load shedding transient response of a buck circuit.

[0005] This disclosure provides a control circuit for improving the transient response of a buck converter during load shedding. The buck converter includes an upper transistor and a lower transistor. The control circuit comprises: an upper transistor turn-on control unit, configured to obtain a delay mode control signal based on a first reference voltage and a feedback voltage of the buck converter, and to obtain an upper transistor turn-on signal based on the delay mode control signal and the duty cycle of the buck converter, thereby controlling the turn-off time of the upper transistor; a lower transistor turn-on control unit, connected to the upper transistor turn-on control unit, configured to obtain a lower transistor turn-on signal based on the feedback voltage, a second reference voltage, and the delay mode control signal, thereby controlling the turn-on time of the upper transistor; and a control signal output unit, connected to the upper transistor turn-on control unit and the lower transistor turn-on control unit, configured to receive the upper transistor turn-on signal and the lower transistor turn-on signal, and to output a switch control signal based on the upper transistor turn-on signal and the lower transistor turn-on signal to control the turn-on and turn-off of the upper and lower transistors of the buck converter.

[0006] According to an embodiment of this disclosure, the upper transistor turn-on control unit includes a comparator, a delay module, and an OR gate; wherein, the positive input terminal of the comparator receives the feedback voltage, the negative input terminal of the comparator receives a first reference voltage, and the output terminal of the comparator outputs the delay mode control signal generated based on the feedback voltage and the first reference voltage; the delay module is connected to the output terminal of the comparator and receives the delay mode control signal, and the delay module selects to enter a normal delay mode or a reduced delay mode according to the delay mode control signal; when the delay module selects to enter the reduced delay mode, it obtains a reduced delay signal according to the duty cycle; when the delay module selects the normal delay mode, it obtains a normal delay signal according to a first preset delay time; the OR gate is connected to the delay module and receives the reduced delay signal and the normal delay signal as inputs, and the output terminal of the OR gate outputs the upper transistor turn-on signal.

[0007] According to embodiments of this disclosure, the comparator includes a hysteresis comparator.

[0008] According to an embodiment of this disclosure, the first reference voltage includes an upper threshold voltage and a lower threshold voltage. When the feedback voltage is less than the lower threshold voltage, the delay mode control signal is at a high level, and when the feedback voltage is greater than the upper threshold voltage, the delay mode control signal is at a low level.

[0009] According to an embodiment of this disclosure, when the delay mode control signal is low, the delay module selects to enter the normal delay mode; when the delay mode control signal is high, the delay module selects to enter the reduced delay mode. The reduced delay signal includes a first delay signal and a second delay signal. When the delay module selects to enter the reduced delay mode, if the duty cycle is less than a preset value, the first delay signal is obtained according to a second preset delay time; if the duty cycle is greater than or equal to the preset value, the second delay signal is obtained according to a third preset delay time, wherein the third preset delay time is less than the second preset delay time, and the second preset delay time is less than the first preset delay time.

[0010] According to an embodiment of this disclosure, the lower MOSFET turn-on control unit includes an error amplifier, a charging module, a reference current generation module, and a comparator module. The error amplifier receives a second reference voltage at its non-inverting input terminal, receives a feedback voltage at its negative input terminal, and outputs a first voltage signal generated based on the second reference voltage and the feedback voltage. The charging module is connected to the output terminal of the comparator in the upper MOSFET turn-on control unit and receives a delay mode control signal. The charging module is also connected to the output terminal of the error amplifier and determines whether to charge the output terminal of the error amplifier based on the delay mode control signal to form a second voltage signal. The reference current generation module's input terminal is connected to the output terminal of the error amplifier and receives the second voltage signal. The reference current generation module's output terminal outputs a reference current signal generated based on the second voltage signal. The comparator module's input terminal is connected to the output terminal of the reference current generation module and receives the reference current signal. The comparator module receives an inductor current feedback signal from the buck circuit and obtains a lower MOSFET turn-on signal based on the reference current signal and the inductor current feedback signal.

[0011] According to an embodiment of this disclosure, when the delay module control signal corresponds to the reduced delay mode, the charging module charges the output of the error amplifier to form the second voltage signal; when the delay module control signal corresponds to the normal delay mode, the charging module does not charge the output of the error amplifier and uses the first voltage signal as the second voltage signal.

[0012] According to embodiments of this disclosure, the reference current signal is positively correlated with the second voltage signal.

[0013] According to an embodiment of this disclosure, when the current value of the inductor current feedback signal is equal to the current value of the reference current signal, the comparison module generates the lower transistor conduction signal.

[0014] According to an embodiment of this disclosure, the control signal output unit includes an RS flip-flop. The S terminal of the flip-flop is connected to the output terminal of the OR gate of the upper transistor conduction control unit and receives the upper transistor conduction signal. The R terminal of the flip-flop is connected to the output terminal of the comparator module of the lower transistor conduction control unit and receives the lower transistor conduction signal. The Q terminal of the flip-flop outputs the switch control signal.

[0015] The control circuit disclosed herein, which improves the transient response of the buck converter during load shedding, can reduce the turn-off time of the upper transistor and increase the conduction time by entering a reduced delay mode and utilizing the duty cycle. This accelerates the rise of the inductor current while avoiding output voltage oscillations caused by current overshoot. Attached Figure Description

[0016] The above and other objects, features, and advantages of exemplary embodiments of the present disclosure will become readily apparent upon reading the following detailed description with reference to the accompanying drawings. In the drawings, several embodiments of the present disclosure are illustrated by way of example and not limitation, and like or corresponding reference numerals denote like or corresponding parts, wherein:

[0017] Figure 1 This is a schematic diagram showing the equivalent circuit structure of the BUCK circuit in the prior art;

[0018] Figure 2 This is a schematic diagram showing the timing changes of inductor current and turn-on signal when the BUCK circuit in the prior art operates in DCM mode;

[0019] Figure 3 This is a schematic diagram showing the timing changes of inductor current and turn-on signal when the BUCK circuit in the prior art operates in CCM mode;

[0020] Figure 4 This is a schematic diagram showing the structure of a control circuit for a BUCK circuit in the prior art;

[0021] Figure 5 This is a schematic diagram illustrating the structure of a control circuit for improving the load-switching transient response of a buck circuit according to an embodiment of the present disclosure;

[0022] Figure 6 This is a schematic diagram of the circuit structure of the upper transistor turn-on control unit of the control circuit for improving the load shedding transient response of the buck circuit according to an embodiment of the present disclosure;

[0023] Figure 7 This is a schematic diagram of the circuit structure of the lower transistor turn-on control unit of the control circuit for improving the load shedding transient response of the buck circuit according to an embodiment of the present disclosure;

[0024] Figure 8 This is a timing diagram illustrating the inductor current response under the control of a control circuit that improves the transient response of a buck circuit during load shedding, according to an embodiment of this disclosure. Detailed Implementation

[0025] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0026] To facilitate understanding of the technical solutions disclosed herein, the embodiments of the prior art are described below in conjunction with the accompanying drawings.

[0027] Figure 1 This is a schematic diagram illustrating the equivalent circuit structure of a BUCK circuit in the prior art. A BUCK circuit, also known as a buck converter circuit, is one of the basic DC-DC circuits used for DC-DC step-down conversion. For example... Figure 1 As shown, the BUCK circuit includes an upper transistor S1 and a lower transistor S2 that switch between on and off modes, and also includes a current generator I. in power supply V in Inductor L, Capacitor C out and load resistance R out As the upper transistor S1 and the lower transistor S2 switch continuously, the circuit generates an output voltage V. out and inductor current I L .and Figure 1 The node SW is also shown.

[0028] Figure 2 This is a schematic diagram illustrating the timing changes of inductor current and turn-on signal in a prior art BUCK circuit operating in DCM mode. DCM mode refers to discontinuous conduction mode. Combined with... Figure 1 ,like Figure 2 As shown, when the BUCK circuit operates in DCM mode, the upper transistor S1 and the lower transistor S2 conduct discontinuously. Specifically, the upper transistor S1 first enters the conducting state under the action of the upper transistor turn-on signal HS, and the inductor current IL gradually increases. When the upper transistor turn-on time TON ends, the upper transistor S1 turns off, and the lower transistor S2 turns on under the action of the lower transistor turn-on signal LS, causing the inductor current to gradually decrease. When the inductor current IL decreases to 0, the lower transistor S2 turns off, but the upper transistor S1 does not immediately turn on, but waits until the upper transistor turn-off time TOFF ends before turning on again, causing the inductor current to increase again. Here, TON is the upper transistor turn-on time within a switching cycle, and TOFF is the upper transistor turn-off time within a switching cycle.

[0029] Figure 3 This is a schematic diagram illustrating the timing changes of inductor current and turn-on signal in a prior art BUCK circuit operating in CCM mode. CCM mode refers to continuous conduction mode. Combined with... Figure 1 ,like Figure 3As shown, when the BUCK circuit operates in CCM mode, the upper transistor S1 and the lower transistor S2 are continuously turned on. Specifically, the upper transistor S1 first enters the conducting state under the action of the upper transistor turn-on signal HS, and the inductor current IL gradually increases. When the upper transistor turn-on time TON ends, the upper transistor S1 turns off, and the lower transistor S2 turns on under the action of the lower transistor turn-on signal LS, causing the inductor current to gradually decrease. When the upper transistor turn-off time TOFF ends, the lower transistor S2 turns off, and the upper transistor S1 turns on again under the action of the upper transistor turn-on signal HS, causing the inductor current to increase again. Here, TON is the upper transistor turn-on time within a switching cycle, and TOFF is the upper transistor turn-off time within a switching cycle.

[0030] Figure 4 This is a schematic diagram illustrating the structure of a control circuit for a BUCK circuit in the prior art. For example... Figure 4 As shown, this control circuit is used to control the switching on and off of the upper and lower transistors. Specifically, the error amplifier can be based on a reference voltage V. REF The output voltage EAO is determined by the error of the feedback voltage FB fed back from the output of the BUCK circuit via a voltage feedback circuit. This voltage EAO positively influences the reference current I. REF The reference current and the inductor current I sampled by the current feedback circuit L By comparison, when the reference current equals the inductor current, a square wave signal is generated. This square wave signal can be used to form a PWM (Pulse Width Modulation) switching control signal that controls the upper and lower transistors to conduct alternately, thereby controlling the BUCK circuit. The switching circuit includes the BUCK circuit.

[0031] Through this control circuit, when the BUCK circuit output switches from a light load (e.g., IL=0A) to a heavy load (e.g., IL=5A), a series of reactions will occur in the following order: the output voltage of the BUCK circuit decreases, the feedback voltage FB decreases, and the reference voltage V... REF As the difference between the feedback voltage FB and the error amplifier increases, the output voltage EAO of the error amplifier increases, and the reference current I... REF Increase, peak inductor current I PEAK The upper transistor is turned off only when the inductor current equals the reference current, and then the inductor current decreases. Therefore, the increase in the reference current causes the peak value of the inductor current to increase compared with the original peak value. As a result, the average output inductor current increases, and the closed-loop feedback eventually restores the originally reduced output voltage VO to the rated value.

[0032] However, this closed-loop feedback requires time to react; only when the output voltage EAO of the error amplifier is fed back into the feedback loop to recover the output voltage VO will the peak inductor current I be reduced. PEAK The increase in load current cannot keep up with the increase in load current in time, resulting in a large undershoot of output voltage VO (the difference between the output voltage VO from the rated value to the drop point), a long recovery time, and poor dynamic response.

[0033] To rapidly increase inductor current, this disclosure provides a control circuit that improves the transient response of a buck converter during load shedding. The specific embodiments of this disclosure are described in detail below with reference to the accompanying drawings.

[0034] Figure 5 This is a schematic diagram illustrating the structure of a control circuit 1 for improving the load-cutting transient response of a buck circuit according to an embodiment of the present disclosure. The buck circuit is as follows: Figure 1 The BUCK circuit shown includes an upper transistor and a lower transistor. Figure 5 As shown, the control circuit 1 includes: an upper transistor turn-on control unit 10, used to obtain a delay mode control signal based on a first reference voltage and the feedback voltage of the buck circuit, and to obtain an upper transistor turn-on signal based on the delay mode control signal and the duty cycle of the buck circuit, so as to control the turn-off time of the upper transistor; a lower transistor turn-on control unit 20, connected to the upper transistor turn-on control unit 10, used to obtain a lower transistor turn-on signal based on the feedback voltage, the second reference voltage and the delay mode control signal, so as to control the turn-on time of the upper transistor; and a control signal output unit 30, connected to the upper transistor turn-on control unit 10 and the lower transistor turn-on control unit 20, used to receive the upper transistor turn-on signal and the lower transistor turn-on signal, and to output a switch control signal PWM based on the upper transistor turn-on signal and the lower transistor turn-on signal to control the turn-on and turn-off of the upper transistor and the lower transistor of the buck circuit.

[0035] Further, see Figure 6 , Figure 6 This is a schematic diagram of the circuit structure of the upper transistor turn-on control unit 10 of the control circuit for improving the transient response of a buck circuit during load shedding, according to an embodiment of this disclosure. Figure 6As shown, the upper tube conduction control unit 10 includes a comparator 101, a delay module 102, and an OR gate 103. The positive input terminal of the comparator 101 receives the feedback voltage FB, the negative input terminal of the comparator 101 receives the first reference voltage TURBO_REF, and the output terminal of the comparator 101 outputs the delay mode control signal TURBO generated according to the feedback voltage FB and the first reference voltage TURBO_REF. The delay module 102 is connected to the output terminal of the comparator 101 and receives the delay mode control signal TURBO. The delay module 102 selects to enter a normal delay mode or a reduced delay mode according to the delay mode control signal TURBO. When the delay module 102 selects to enter the reduced delay mode, it obtains a reduced delay signal according to the duty cycle. When the delay module 102 selects the normal delay mode, it obtains a normal delay signal TO according to a first preset delay time. The OR gate 103 is connected to the delay module 102 and receives the reduced delay signal and the normal delay signal TO as inputs, and the output of the OR gate 103 outputs the upper tube conduction signal S1ON.

[0036] Specifically, the first reference voltage includes an upper threshold voltage TURBO_REF_HIGH and a lower threshold voltage TURBO_REF_LOW. When the feedback voltage FB is less than the lower threshold voltage TURBO_REF_LOW, the delay mode control signal TURBO is high; when the feedback voltage FB is greater than the upper threshold voltage TURBO_REF_HIGH, the delay mode control signal TURBO is low. The comparator 101 can be a hysteresis comparator, thereby preventing malfunctions caused by jitter in the first reference voltage TURBO_REF. It is worth noting that the first reference voltage is a voltage preset by those skilled in the art based on actual conditions, that is, the upper threshold voltage TURBO_REF_HIGH and the lower threshold voltage TURBO_REF_LOW are voltages preset by those skilled in the art based on actual conditions.

[0037] According to an embodiment of this disclosure, when the delay mode control signal TURBO is low, the delay module 102 selects to enter the normal delay mode, and when the delay mode control signal TURBO is high, the delay module 102 selects to enter the reduced delay mode.

[0038] The reduced delay signal includes a first delay signal TD1 and a second delay signal TD2. When the delay module 102 selects to enter the reduced delay mode, if the duty cycle is less than a preset value, the first delay signal TD1 is obtained according to a second preset delay time. If the duty cycle is greater than or equal to the preset value, the second delay signal TD2 is obtained according to a third preset delay time. The third preset delay time is less than the second preset delay time, and the second preset delay time is less than the first preset delay time.

[0039] According to embodiments of this disclosure, the first preset delay time is the upper transistor turn-off time calculated by the loop of the control circuit, corresponding to... Figure 3 The TOFF signal is shown. After entering the normal delay mode, the delay module 102 waits for the first preset delay time count to end before sending the normal delay signal TO. After entering the delay mode, the delay module 102 determines whether the duty cycle of the buck circuit is less than a preset value. If the duty cycle is less than the preset value, the delay module 102 waits for the second preset delay time count to end before sending the first delay signal TD1, even if the first preset delay time count has not yet ended. If the duty cycle is greater than or equal to the preset value, the delay module 102 waits for the third preset delay time count to end before sending the second delay signal TD2, even if the first and second preset delay time counts have not yet ended. It is worth noting that regardless of whether the delay module enters the normal delay mode or the reduced delay mode, the first, second, and third preset delay times start counting simultaneously. Therefore, as soon as one delay time count ends, the OR gate receives the delay signal and sends the upper transistor turn-on signal, causing the lower transistor to turn off and the upper transistor to turn on.

[0040] According to embodiments of this disclosure, see Figure 1 The duty cycle of the buck circuit (system) shown can be obtained by comparing the average voltage at node SW with the supply voltage using a current mirror.

[0041] By entering the reduced delay mode, the turn-off time of the upper transistor is reduced, and the turn-on time is increased, thus accelerating the rise of the inductor current. Furthermore, the reduced delay mode has two different delay times. This is because when the system duty cycle is very small, i.e., less than a preset value, the inductor current rises rapidly but falls very slowly. Setting the second preset delay time longer can prevent current overshoot caused by an excessively short delay time, which could lead to output voltage oscillations. It is worth noting that those skilled in the art can set this preset value according to actual conditions.

[0042] Further, see Figure 7 , Figure 7This is a schematic diagram of the circuit structure of the lower transistor turn-on control unit 20, which is part of a control circuit for improving the transient response of a buck converter under load shedding according to an embodiment of this disclosure. The lower transistor turn-on control unit 20 includes an error amplifier 201, a charging module 202, a reference current generation module 203, and a comparator module 204. The positive input terminal of the error amplifier 201 receives the second reference voltage REF, the negative input terminal receives the feedback voltage FB, and the output terminal of the error amplifier 201 outputs a first voltage signal generated based on the second reference voltage REF and the feedback voltage FB. The charging module 202 is connected to the output terminal of the comparator 101 of the upper transistor turn-on control unit 10 and receives the delay mode control signal TURBO. The charging module 202 is also connected to the output terminal of the error amplifier 201 and determines whether to charge the output terminal of the error amplifier 201 based on the delay mode control signal TURBO to form a second voltage signal EAO. The input terminal of the reference current generation module 203 is connected to the output terminal of the error amplifier 201 and receives the second voltage signal EAO. The output terminal of the reference current generation module 203 outputs the reference current signal I generated according to the second voltage signal EAO. REF The input terminal of the comparison module 204 is connected to the output terminal of the reference current generation module 203 and receives the reference current signal I. REF The comparison module 204 receives the inductor current feedback signal from the buck circuit (BUCK circuit), and the comparison module 204 compares the reference current signal I. REF The lower transistor conduction signal S2ON is obtained from the inductor current feedback signal.

[0043] Specifically, when the delay module control signal TURBO corresponds to the reduced delay mode, the charging module 202 charges the output of the error amplifier 201 to form the second voltage signal EAO. When the delay module control signal TURBO corresponds to the normal delay mode, the charging module 202 does not charge the output of the error amplifier 201, and uses the first voltage signal as the second voltage signal EAO. The reference current signal I... REF It is positively correlated with the second voltage signal EAO. When the current value of the inductor current feedback signal is equal to the reference current signal I... REF When the current value is reached, the comparison module 204 generates the lower tube conduction signal S2ON.

[0044] According to embodiments of this disclosure, the charging module 202 may include a current source I that generates a constant current. CHARGEThe charging module 202 consists of a charging circuit composed of capacitors and resistors, and a switch (Smos) formed by a MOSFET. When the delay module control signal TURBO is high, corresponding to the reduced delay mode, the switch (Smos) in the charging module 202 is closed, and the current source can charge the output of the error amplifier 201. When the delay module control signal TURBO is low, corresponding to the normal delay mode, the switch (Smos) in the charging module 202 is open, and the current source does not charge the output of the error amplifier 201.

[0045] When the charging module 202 charges the output terminal of the error amplifier 201, the voltage at the output terminal increases, thereby increasing the reference current I generated by the reference current generation module. REF Increase. If the reference current I REF If the inductor current is increased, it will take longer for the inductor current in the comparator module 204 to equal the reference current. This means the comparator module will take longer to generate the lower transistor turn-on signal to turn off the upper transistor and turn on the lower transistor, thus extending the conduction time of the upper transistor. Therefore, the peak inductor current and the average inductor current can be larger, allowing the output voltage of the buck circuit to recover to its rated value more quickly.

[0046] According to an embodiment of this disclosure, the control signal output unit 30 includes an RS flip-flop. The S terminal of the flip-flop is connected to the output terminal of the OR gate 103 of the upper transistor turn-on control unit 10 and receives the upper transistor turn-on signal S1ON. The R terminal of the flip-flop is connected to the output terminal of the comparator module 204 of the lower transistor turn-on control unit 20 and receives the lower transistor turn-on signal S2ON. The Q terminal of the flip-flop outputs the switching control signal PWM. Therefore, when the flip-flop receives the upper transistor turn-on signal S1ON, the generated switching control signal causes the lower transistor to turn off and the upper transistor to turn on. When the flip-flop receives the lower transistor turn-on signal S2ON, the generated switching control signal causes the upper transistor to turn off and the lower transistor to turn on.

[0047] See Figure 8 , Figure 8 This is a timing diagram illustrating the inductor current response under the control of a control circuit that improves the transient response of a buck circuit during load shedding, according to an embodiment of this disclosure. Figure 8As shown, when the output of the buck circuit switches from light load to heavy load, the output voltage Vout of the buck circuit decreases, thereby reducing the feedback voltage FB. When the feedback voltage FB is less than the lower threshold voltage TURBO_REF_LOW, the delay module in the upper MOSFET turn-on control unit of the control circuit will enter the reduced delay mode, thereby reducing the turn-off time of the upper MOSFET, turning it on earlier, and allowing the inductor current IL to rise in time. Meanwhile, the charging module in the lower MOSFET turn-on control unit charges the output of the error amplifier in the reduced delay mode, thereby increasing the output voltage EAO, increasing the turn-on time of the upper MOSFET, and further accelerating the rise of the inductor current IL. Furthermore, when the feedback voltage FB is greater than the upper threshold voltage TURBO_REF_HIGH, the inductor current is large enough to enter the normal delay mode. In addition, by utilizing the duty cycle, the delay time in the delay mode can be made different, thus avoiding current overshoot caused by the rapid rise and slow fall of the inductor current when the duty cycle is extremely small, which could lead to output voltage oscillation.

[0048] The embodiments of this disclosure have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this disclosure. The description of the above embodiments is only for the purpose of helping to understand the methods and core ideas of this disclosure. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this disclosure. Therefore, the content of this specification should not be construed as a limitation of this disclosure.

[0049] It should be understood that the terms "first" and "second," etc., in the claims, specification, and drawings of this disclosure are used to distinguish different objects, not to describe a specific order. The terms "comprising" and "including" as used in the specification and claims of this disclosure indicate the presence of the described features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or collections thereof.

[0050] It should also be understood that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this disclosure. As used in this disclosure and claims, the singular forms “a,” “an,” and “the” are intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used in this disclosure and claims refers to any combination and all possible combinations of one or more of the associated listed items, and includes such combinations.

[0051] The embodiments of this disclosure have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this disclosure. The descriptions of the embodiments above are only for the purpose of helping to understand the methods and core ideas of this disclosure. Furthermore, any changes or modifications made by those skilled in the art based on the ideas of this disclosure, and on the specific implementation methods and application scope of this disclosure, are all within the scope of protection of this disclosure. Therefore, the content of this specification should not be construed as a limitation of this disclosure.

Claims

1. A control circuit for improving the load transient response of a step-down circuit, said step-down circuit comprising an upper transistor and a lower transistor, characterized in that, The control circuit comprises: an upper tube conduction control unit configured to obtain a delay mode control signal according to a first reference voltage and a feedback voltage of the step-down circuit, and obtain an upper tube conduction signal according to the delay mode control signal and a duty cycle of the step-down circuit to control an off time of the upper tube; a lower tube conduction control unit connected with the upper tube conduction control unit and configured to obtain a lower tube conduction signal according to the feedback voltage, a second reference voltage and the delay mode control signal to control an on time of the upper tube; a control signal output unit connected with the upper tube conduction control unit and the lower tube conduction control unit and configured to receive the upper tube conduction signal and the lower tube conduction signal, and output a switch control signal according to the upper tube conduction signal and the lower tube conduction signal to control the on and off of the upper tube and the lower tube of the step-down circuit.

2. The control circuit for improving the load transient response of a voltage reduction circuit as defined in claim 1, wherein The upper tube conduction control unit comprises a comparator, a delay module and an OR gate; wherein the positive phase input end of the comparator receives the feedback voltage, the negative phase input end of the comparator receives the first reference voltage, and the output end of the comparator outputs the delay mode control signal generated according to the feedback voltage and the first reference voltage; the delay module is connected with the output end of the comparator and receives the delay mode control signal, and the delay module selects to enter a normal delay mode or a reduced delay mode according to the delay mode control signal, when the delay module selects to enter the reduced delay mode, a reduced delay signal is obtained according to the duty cycle, and when the delay module selects the normal delay mode, a normal delay signal is obtained according to a first preset delay time; the OR gate is connected with the delay module and receives the reduced delay signal and the normal delay signal as inputs, and the output end of the OR gate outputs the upper tube conduction signal.

3. The control circuit for improving the load transient response of a voltage reduction circuit as defined in claim 2, wherein The comparator comprises a hysteretic comparator.

4. The control circuit for improving the load transient response of a voltage reduction circuit as defined in claim 2, wherein The first reference voltage comprises an upper threshold voltage and a lower threshold voltage, the delay mode control signal is high when the feedback voltage is less than the lower threshold voltage, and the delay mode control signal is low when the feedback voltage is greater than the upper threshold voltage.

5. The control circuit for improving the load transient response of the step-down circuit according to claim 4, wherein when the delay mode control signal is low, the delay module selects to enter the normal delay mode, and when the delay mode control signal is high, the delay module selects to enter the reduced delay mode, the reduced delay signal comprises a first delay signal and a second delay signal, when the delay module selects to enter the reduced delay mode, if the duty cycle is less than a preset value, the first delay signal is obtained according to a second preset delay time, if the duty cycle is greater than or equal to the preset value, the second delay signal is obtained according to a third preset delay time, wherein the third preset delay time is less than the second preset delay time, and the second preset delay time is less than the first preset delay time.

6. The control circuit for improving transient response of a buck circuit according to claim 5, wherein, the lower tube conduction control unit comprises an error amplifier, a charging module, a reference current generation module and a comparison module; wherein, the positive input terminal of the error amplifier receives the second reference voltage, the negative input terminal of the error amplifier receives the feedback voltage, and the output terminal of the error amplifier outputs a first voltage signal generated according to the second reference voltage and the feedback voltage; the charging module is connected with the output terminal of the comparator of the upper tube conduction control unit and receives the delay mode control signal, and the charging module is connected with the output terminal of the error amplifier and determines whether to charge the output terminal of the error amplifier according to the delay mode control signal to form a second voltage signal; the input terminal of the reference current generation module is connected with the output terminal of the error amplifier and receives the second voltage signal, and the output terminal of the reference current generation module outputs a reference current signal generated according to the second voltage signal; the input terminal of the comparison module is connected with the output terminal of the reference current generation module and receives the reference current signal, the comparison module receives an inductor current feedback signal of the buck circuit, and the comparison module obtains a lower tube conduction signal according to the reference current signal and the inductor current feedback signal.

7. The control circuit for improving transient response of a buck circuit according to claim 6, wherein, when the delay module control signal corresponds to the reduced delay mode, the charging module charges the output terminal of the error amplifier to form the second voltage signal, when the delay module control signal corresponds to the normal delay mode, the charging module does not charge the output terminal of the error amplifier, and the first voltage signal is taken as the second voltage signal.

8. The control circuit for improving the load transient response of a voltage reduction circuit as recited in claim 7, wherein the reference current signal is positively correlated with the second voltage signal.

9. The control circuit for improving transient response of a buck circuit according to claim 8, wherein, when the current value of the inductor current feedback signal is equal to the current value of the reference current signal, the comparison module generates the lower tube conduction signal.

10. The control circuit for improving the load transient response of a voltage reduction circuit as recited in claim 8, wherein the control signal output unit comprises an RS flip-flop, the S terminal of the flip-flop is connected with the output terminal of the OR gate of the upper tube conduction control unit and receives the upper tube conduction signal, the R terminal of the flip-flop is connected with the output terminal of the comparison module of the lower tube conduction control unit and receives the lower tube conduction signal, and the Q terminal of the flip-flop outputs the switch control signal.

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