Adaptive slope compensation circuit for dc-dc converter based on acot control mode

Abstract

Embodiments of the present disclosure provide an adaptive ramp compensation circuit for a DC-DC converter based on an ACOT control mode, which includes a boost control circuit, a voltage clamping circuit, a pull-down control circuit, and an output circuit. The boost control circuit generates a boost control signal according to a first voltage signal and a clamping control signal, and provides the boost control signal to the output circuit via a first node. The voltage clamping circuit generates the clamping control signal and a voltage holding signal according to an output signal output by the output circuit, a clamping voltage signal, and a second voltage signal, provides the clamping control signal to the boost control circuit, and provides the voltage holding signal to the output circuit via the first node. The pull-down control circuit pulls down the output signal under control of a fixed on-time control signal of the DC-DC converter. The output circuit generates a ramp signal as the output signal under control of the boost control signal, holds a voltage of the output signal under control of the voltage holding signal, and outputs the output signal.

Description

Technical Field

[0001] Embodiments of this disclosure relate to the field of integrated circuit technology, and more specifically, to an adaptive slope compensation circuit for a DC-DC converter based on ACOT control mode, and a DC-DC converter based on ACOT control mode. Background Technology

[0002] DC-DC converters are commonly used in various electronic devices to convert DC voltage. DC-DC converters include buck converters and boost converters. Buck converters convert higher DC voltages to lower DC voltages, while boost converters convert lower DC voltages to higher DC voltages. Currently, adaptive constant on-time (ACOT) control is commonly used in DC-DC converters to improve power supply response speed. However, this control method, due to its inherent limitations, requires an output capacitor with a relatively large equivalent series resistance (ESR) to maintain the stability of the DC-DC converter. Summary of the Invention

[0003] The embodiments described herein provide an adaptive ramp compensation circuit for a DC-DC converter based on ACOT control mode, and a DC-DC converter based on ACOT control mode.

[0004] According to a first aspect of this disclosure, an adaptive ramp compensation circuit for a DC-DC converter based on ACOT control mode is provided. The adaptive ramp compensation circuit includes: a boost control circuit, a voltage clamping circuit, a pull-down control circuit, and an output circuit. The boost control circuit is configured to generate a boost control signal based on a first voltage signal from a first voltage terminal and a clamping control signal from the voltage clamping circuit, and provide the boost control signal to the output circuit via a first node. The voltage clamping circuit is configured to generate a clamping control signal and a voltage holding signal based on an output signal output from the output circuit, a clamping voltage signal from a clamping voltage terminal, and a second voltage signal from a second voltage terminal, provide the clamping control signal to the boost control circuit via a second node, and provide the voltage holding signal to the output circuit via the first node. The pull-down control circuit is configured to pull down the output signal output by the output circuit under the control of a fixed on-time control signal of the DC-DC converter. The output circuit is configured to generate a ramp signal as an output signal under the control of the boost control signal, hold the voltage of the output signal under the control of the voltage holding signal, and output the output signal from the output terminal.

[0005] In some embodiments of this disclosure, the boost control circuit includes: a first voltage-controlled switch. A first terminal of the first voltage-controlled switch is coupled to a first voltage terminal. A second terminal of the first voltage-controlled switch is coupled to a first node. A controlled input terminal of the first voltage-controlled switch is coupled to a second node.

[0006] In some embodiments of this disclosure, the voltage clamping circuit includes a first comparator and a second voltage-controlled switch. A first input terminal of the first comparator is coupled to its output terminal. A second input terminal of the first comparator is coupled to a clamping voltage terminal. A first output terminal of the first comparator is coupled to a controlled input terminal of the second voltage-controlled switch. A second output terminal of the first comparator is coupled to a second node. A first terminal of the second voltage-controlled switch is coupled to a second voltage terminal. A second terminal of the second voltage-controlled switch is coupled to a first node.

[0007] In some embodiments of this disclosure, the voltage clamping circuit further includes a first resistor and a second resistor. A first terminal of the first resistor is coupled to a third voltage terminal. A second terminal of the first resistor is coupled to the clamping voltage terminal and the first terminal of the second resistor. A second terminal of the second resistor is coupled to a second voltage terminal.

[0008] In some embodiments of this disclosure, the first resistor and / or the second resistor are arranged outside the package of the DC-DC converter.

[0009] In some embodiments of this disclosure, the pull-down control circuit includes a third voltage-controlled switch and a third resistor. A first terminal of the third voltage-controlled switch is coupled to an output terminal. A second terminal of the third voltage-controlled switch is coupled to a first terminal of the third resistor. The controlled input terminal of the third voltage-controlled switch is provided with a fixed on-time control signal for a DC-DC converter. The second terminal of the third resistor is coupled to a second voltage terminal.

[0010] In some embodiments of this disclosure, the output circuit includes a voltage-controlled current source and a first capacitor. The first input terminal of the voltage-controlled current source is coupled to a first node. The second input terminal of the voltage-controlled current source is coupled to a second voltage terminal. The first output terminal of the voltage-controlled current source is coupled to a second terminal and a second voltage terminal of the first capacitor. The second output terminal of the voltage-controlled current source is coupled to a first terminal and an output terminal of the first capacitor.

[0011] In some embodiments of this disclosure, the first capacitor is arranged outside the package of the DC-DC converter.

[0012] According to a second aspect of this disclosure, an adaptive slope compensation circuit for a DC-DC converter based on ACOT control mode is provided. The adaptive slope compensation circuit includes: a first voltage-controlled switch, a second voltage-controlled switch, a third voltage-controlled switch, a first comparator, a first capacitor, a first resistor, a second resistor, a third resistor, and a voltage-controlled current source. A first terminal of the first voltage-controlled switch is coupled to a first voltage terminal. A second terminal of the first voltage-controlled switch is coupled to a first input terminal of the voltage-controlled current source. A controlled input terminal of the first voltage-controlled switch is coupled to a second output terminal of the first comparator. A first input terminal of the first comparator is coupled to the output terminal of the adaptive slope compensation circuit. A second input terminal of the first comparator is coupled to a second terminal of the first resistor and a first terminal of the second resistor. A first output terminal of the first comparator is coupled to a controlled input terminal of the second voltage-controlled switch. A first terminal of the second voltage-controlled switch is coupled to a second voltage terminal. A second terminal of the second voltage-controlled switch is coupled to a first input terminal of the voltage-controlled current source. A first terminal of the first resistor is coupled to a third voltage terminal. A second terminal of the second resistor is coupled to a second voltage terminal. A second input terminal of the voltage-controlled current source is coupled to a second voltage terminal. The first output terminal of the voltage-controlled current source is coupled to the second terminal of the first capacitor and the second voltage terminal. The second output terminal of the voltage-controlled current source is coupled to the first terminal and the output terminal of the first capacitor. The first terminal of the third voltage-controlled switch is coupled to the output terminal. The second terminal of the third voltage-controlled switch is coupled to the first terminal of the third resistor. The controlled input terminal of the third voltage-controlled switch is provided with a fixed on-time control signal for the DC-DC converter. The second terminal of the third resistor is coupled to the second voltage terminal.

[0013] According to a third aspect of this disclosure, a DC-DC converter based on ACOT control mode is provided. The DC-DC converter includes the adaptive ramp compensation circuit described in the first or second aspect of this disclosure. Attached Figure Description

[0014] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. It should be understood that the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure, wherein:

[0015] Figure 1 This is an exemplary circuit diagram of a DC-DC converter based on the ACOT control mode;

[0016] Figure 2 This is another exemplary circuit diagram of a DC-DC converter based on the ACOT control mode;

[0017] Figure 3 This is an exemplary circuit diagram of a DC-DC converter based on ACOT control mode according to an embodiment of the present disclosure;

[0018] Figure 4This is an exemplary block diagram of an adaptive slope compensation circuit according to an embodiment of the present disclosure;

[0019] Figure 5 This is an exemplary circuit diagram of an adaptive slope compensation circuit according to an embodiment of the present disclosure;

[0020] Figure 6 This is another exemplary circuit diagram of an adaptive slope compensation circuit according to embodiments of the present disclosure; and

[0021] Figures 7 to 10 It is used for Figure 3 The timing diagram shows some signals of the DC-DC converter.

[0022] In the accompanying diagram, markers with the same last two digits correspond to the same elements. It should be noted that the elements in the diagram are schematic and not drawn to scale. Detailed Implementation

[0023] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are also within the scope of protection of this disclosure.

[0024] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this subject matter pertains. It will be further understood that terms such as those defined in commonly used dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the specification and in the relevant art, and shall not be interpreted in an idealized or overly formal form unless otherwise explicitly defined herein. As used herein, the statement of “connecting” or “coupling” two or more parts together shall mean that these parts are directly joined together or joined through one or more intermediate components.

[0025] In all embodiments of this disclosure, since the source and drain (emitter and collector) of the transistor are symmetrical, and the conduction current directions between the source and drain (emitter and collector) of N-type and P-type transistors are opposite, the controlled middle terminal of the transistor is referred to as the control terminal, and the remaining two terminals of the transistor are referred to as the first terminal and the second terminal, respectively. The transistors used in the embodiments of this disclosure are primarily switching transistors. Furthermore, terms such as "first" and "second" are used only to distinguish one component (or part of a component) from another component (or another part of a component).

[0026] Figure 1 A DC-DC converter 100 is shown. Figure 1 In the example, an input voltage Vin is supplied to the input voltage terminal Vin. When the first switching transistor HS is turned on, the input voltage Vin is applied to the filter formed by the inductor L and the output capacitor Cout, and the input current flows through the inductor L to the output capacitor Cout and the resistor R. L .exist Figure 1 In this context, resistor Resr represents the equivalent series resistance of the output capacitor Cout. The output voltage Vout is coupled to the output capacitor Cout and resistor R. L Therefore, the output voltage Vout has ripple. Resistors R1 and R2 are placed between the output voltage Vout and ground as a voltage divider feedback circuit. The voltage signal on resistor R2 is fed back to the inverting input of error amplifier EA and the inverting input of PWM comparator 101 via node FB. The non-inverting input of error amplifier EA is provided with a reference voltage Vref. Since the output voltage Vout has ripple, the feedback voltage at node FB also has ripple. Error amplifier EA amplifies the difference between the feedback voltage and the reference voltage Vref. The non-inverting input of PWM comparator 101 is coupled to the output of error amplifier EA (i.e., node COMP). PWM comparator 101 generates a PWM signal based on the voltage at node COMP and the feedback voltage at node FB. The on-time timer generates a fixed on-time control signal based on the PWM signal, input voltage Vin, and output voltage Vout, and provides the fixed on-time control signal to the drive module via node DR. The fixed on-time control signal is used to control the alternating conduction of the first switching transistor HS and the second switching transistor LS. When the first switching transistor HS is turned on, the second switching transistor LS is turned off, and the voltage at node SW is equal to the input voltage Vin. When the second switching transistor LS is turned on, the first switching transistor HS is turned off.

[0027] exist Figure 1 In the DC-DC converter 100, ACOT control is used to improve the power supply's response speed. However, this control method requires a larger ripple in the feedback voltage used to generate the PWM signal (i.e., a larger equivalent series resistance Resr of capacitor Cout) to maintain the stability of the DC-DC converter 100. However, the ripple of the output voltage Vout is directly proportional to the magnitude of the equivalent series resistance Resr of capacitor Cout. A larger equivalent series resistance of capacitor Cout results in a larger ripple in the output voltage Vout, which can affect the operation of the load circuit.

[0028] Therefore, in practical applications, it is desirable for the output voltage Vout of the DC-DC converter 100 to have as little ripple as possible, while the feedback voltage used to generate the PWM signal should have as much ripple as possible.

[0029] Figure 2 Another DC-DC converter 200 is shown. Figure 2 In the DC-DC converter 200, Figure 1 Based on the DC-DC converter 100, an RC ripple injection circuit 220 is added. The RC ripple injection circuit 220 includes a resistor R RI Capacitor C RI And capacitor C3. The RC ripple injection circuit 220 can generate a ripple signal in phase with the output inductor current. This ripple signal is superimposed on the signal at node FB and then input to the inverting input of PWM comparator 101. By setting resistor R RI Capacitor C RI The value of capacitor C3 allows the ripple generated by the RC ripple injection circuit 220 to be larger than the ripple of the output voltage Vout. Therefore, the instability problem of the DC-DC converter 200 can be improved by eliminating the need for capacitor Cout with a large equivalent series resistance Resr in the DC-DC converter 200.

[0030] but Figure 2 The DC-DC converter 200 has the following three defects.

[0031] In the first aspect, the amount of ripple injected by the RC ripple injection circuit 220 is mismatched with the amount of ripple in the output voltage Vout of the DC-DC converter 200, which will affect the linear regulation and dynamic performance of the DC-DC converter 200.

[0032] Based on the working principle of the DC-DC converter, the ripple ΔV generated on the output capacitor Cout can be derived. ESR Satisfy the following equation (1):

[0033]

[0034] Where Resr represents the resistance value of the equivalent series resistance Resr, ΔIL represents the current increment on inductor L, D represents the duty cycle of the PWM signal, and D=Vout / Vin, Vin represents the input voltage, Vout represents the output voltage, T represents the period of the PWM signal, f represents the frequency of the PWM signal, L represents the inductance value of inductor L, and C represents the capacitance value of output capacitor Cout. According to the above formula (1), under the condition that the switching frequency of the first switching transistor HS and the output voltage Vout are fixed, when D<0.5, ΔV ESR It will decrease as the input voltage Vin increases.

[0035] Based on the working principle of the ripple injection circuit 220, the ripple amount ΔV injected at node FB can be derived. RC Satisfy the following equation (2):

[0036]

[0037] Where R represents the resistor R in the ripple injection circuit 220. R1 The resistance value, C represents the capacitor C in the ripple injection circuit 220. C1 The capacitance value, D represents the duty cycle of the PWM signal, T represents the period of the PWM signal, Vin represents the input voltage, and Vout represents the output voltage. According to the above formula (2), under the condition that the switching frequency of the first switching transistor HS and the output voltage Vout are fixed, ΔV RC It will increase as the input voltage Vin increases.

[0038] Therefore, under the condition of D<0.5, as the input voltage Vin changes, the RC ripple injection amount generated by the RC ripple injection circuit 220 cannot well characterize the ripple change trend of the output voltage, thus affecting the load regulation rate.

[0039] Secondly, when the DC-DC converter 200 is operating in discontinuous conduction (DCM) mode, when both the first switching transistor HS and the second switching transistor LS are turned off, the voltage at node FB will fluctuate with the voltage at node SW, which may cause the period of the PWM signal to be unstable.

[0040] Thirdly, if the RC ripple injection circuit 220 is integrated inside the package (chip package) of the DC-DC converter 200, once the parameters of the components inside the RC ripple injection circuit 220 are selected, they cannot be changed. It is difficult to be compatible with input voltages with a large range of variation. At the same time, it is not convenient for engineers using the chip to use external adjustment circuits to modify the above parameters according to the actual application situation.

[0041] Embodiments of this disclosure propose a DC-DC converter based on ACOT control mode, which incorporates an adaptive ramp compensation circuit to help maintain the stability of the PWM signal generated by the PWM comparator. Figure 3 An exemplary circuit diagram of a DC-DC converter 300 based on an ACOT control mode according to an embodiment of the present disclosure is shown. The DC-DC converter 300 may include: a drive module, a first switching transistor HS, a second switching transistor LS, an inductor L, an output capacitor Cout, an equivalent series resistance Resr of the output capacitor Cout, and a resistor R. LResistor R1, Resistor R2, Capacitor C C The circuit includes an error amplifier EA, a PWM comparator 101, an on-time timer, an adder, and an adaptive slope compensation circuit 310.

[0042] The drive module is coupled to the output of the on-time timer, the control electrode of the first switching transistor HS, and the control electrode of the second switching transistor LS. The drive module controls the on and off states of the first and second switching transistors HS and LS based on the fixed on-time control signal output by the on-time timer. When the fixed on-time control signal is high, the first switching transistor HS is on, and the second switching transistor LS is off. At this time, node SW is at a high level.

[0043] The first terminal of the first switching transistor HS is coupled to the input voltage terminal Vin, the second terminal of the first switching transistor HS is coupled to the first terminal of the inductor L, and the control terminal of the first switching transistor HS is coupled to the drive module. The first terminal of the second switching transistor LS is coupled to the first terminal of the inductor L, the second terminal of the second switching transistor LS is grounded, and the control terminal of the second switching transistor LS is coupled to the drive module.

[0044] The second terminal of inductor L is coupled to the output voltage terminal Vout. The first terminal of the equivalent series resistance Resr is coupled to the output voltage terminal Vout, and the second terminal of the equivalent series resistance Resr is coupled to the first terminal of the output capacitor Cout. The second terminal of the output capacitor Cout is grounded. Resistor R L The first terminal is coupled to the output voltage terminal Vout, and the resistor R L The second terminal of resistor R1 is grounded. The first terminal of resistor R1 is coupled to the output voltage terminal Vout, and the second terminal of resistor R1 is coupled to node FB. The first terminal of resistor R2 is coupled to node FB, and the second terminal of resistor R2 is grounded.

[0045] The non-inverting input of the error amplifier is coupled to the reference voltage Vref, the inverting input is coupled to node FB, and the output is coupled to the first input of the adder. The second input of the adder is coupled to the adaptive slope compensation circuit 310, and the output of the adder is coupled to the non-inverting input of the PWM comparator 101 via node Sum. The inverting input of the PWM comparator 101 is coupled to node FB. The output of the PWM comparator 101 is coupled to the on-time timer.

[0046] The on-time timer is coupled to the input voltage terminal Vin and the output voltage terminal Vout. Based on the PWM signal, the input voltage Vin, and the output voltage Vout, it generates a fixed on-time control signal, which is then provided to the drive module via node DR. The fixed on-time control signal is used to control the alternating conduction of the first switching transistor HS and the second switching transistor LS. When the first switching transistor HS is on, the second switching transistor LS is off. When the second switching transistor LS is on, the first switching transistor HS is off.

[0047] The adaptive ramp compensation circuit 310 is configured such that, under steady-state conditions, when the fixed on-time control signal is low (at which point node SW is also low), the adaptive ramp compensation circuit 310 starts generating a ramp signal. Once the voltage of this ramp signal reaches the clamping voltage, the ramp signal stops rising. When the fixed on-time control signal is high (at which point node SW is also high), the ramp signal is pulled down to 0V. The adaptive ramp compensation circuit 310 is also configured such that, under dynamic conditions, when the fixed on-time control signal is low (at which point node SW is also low), the adaptive ramp compensation circuit 310 starts generating a ramp signal. Before the voltage of this ramp signal reaches the clamping voltage but the fixed on-time control signal is already high (at which point node SW is already high), the ramp signal is pulled down to 0V and held. This allows the ramp signal to reflect the voltage changes at node FB as accurately as possible.

[0048] Figure 4 It shows Figure 3 A schematic block diagram of the adaptive ramp compensation circuit 310 in the DC-DC converter 300 shown. Figure 4 As shown, the adaptive slope compensation circuit 310 includes: a boost control circuit 311, a voltage clamping circuit 312, a pull-down control circuit 313, and an output circuit 314.

[0049] The boost control circuit 311 can be coupled to a first voltage terminal V1, a voltage clamping circuit 312, and an output circuit 314. The boost control circuit 311 can be configured to generate a boost control signal based on a first voltage signal V1 from the first voltage terminal V1 and a clamping control signal from the voltage clamping circuit 312, and provide the boost control signal to the output circuit 314 via a first node N1.

[0050] The voltage clamping circuit 312 can be coupled to the output terminal Ramp, the second voltage terminal V2, the clamping voltage terminal Vd of the adaptive slope compensation circuit 310, the boost control circuit 311, and the output circuit 314. The voltage clamping circuit 312 can be configured to generate a clamping control signal and a voltage holding signal based on the output signal Ramp output from the output circuit 314, the clamping voltage signal Vd from the clamping voltage terminal Vd (in this context, the amplitude of the clamping voltage signal can be referred to as the clamping voltage), and the second voltage signal V2 from the second voltage terminal V2. It provides the clamping control signal to the boost control circuit 311 via the second node N2 and the voltage holding signal to the output circuit 314 via the first node N1. In some embodiments of this disclosure, the voltage clamping circuit 312 generates the clamping control signal when the voltage of the output signal Ramp is less than the voltage of the clamping voltage Vd; and generates the voltage holding signal when the voltage of the output signal Ramp is equal to or greater than the voltage of the clamping voltage Vd.

[0051] Pull-down control circuit 313 can be coupled to the output of the on-time timer of DC-DC converter 300 (i.e., node DR) and output circuit 314. The on-time timer can output a fixed on-time control signal from its output. Pull-down control circuit 313 can be configured to pull down the output signal Ramp output by output circuit 314 under the control of the fixed on-time control signal of DC-DC converter. In some embodiments of this disclosure, when the fixed on-time control signal is high (at which time the voltage of node SW is also high), the voltage of output signal Ramp is pulled down to 0V.

[0052] Output circuit 314 is coupled to boost control circuit 311, voltage clamping circuit 312, pull-down control circuit 313, and output terminal Ramp. Output circuit 314 is configured to generate a ramp signal as an output signal under the control of a boost control signal, maintain the voltage of the output signal under the control of a voltage holding signal, and output the output signal Ramp from output terminal Ramp. In some embodiments of this disclosure, the voltage of output signal Ramp rises at a certain slope under the control of the boost control signal. When the voltage of output signal Ramp reaches the clamping voltage Vd, the voltage of output signal Ramp stops rising under the control of the clamping signal. When the fixed on-time control signal is high (at which time the voltage of node SW is also high), the voltage of output signal Ramp is pulled down to 0V.

[0053] The embodiments of this disclosure maintain the stability of the DC-DC converter by adding an adaptive slope compensation circuit 310 to the DC-DC converter based on the ACOT control mode. Therefore, the equivalent series resistance Resr of the output capacitor Cout in the DC-DC converter according to the embodiments of this disclosure can be 0Ω. In addition, the adaptive slope compensation circuit 310 can respond quickly to the switching cycle of the voltage at node SW, compensating for the slow response of the error amplifier EA.

[0054] Figure 5 An exemplary circuit diagram of an adaptive ramp compensation circuit 310 for a DC-DC converter based on ACOT control mode, according to an embodiment of the present disclosure, is shown. Figure 5 As shown, the boost control circuit 311 may include: a first voltage-controlled switch S1. The first terminal of the first voltage-controlled switch S1 is coupled to a first voltage terminal V1. The second terminal of the first voltage-controlled switch S1 is coupled to a first node N1. The controlled input terminal of the first voltage-controlled switch S1 is coupled to a first node N2.

[0055] The voltage clamping circuit 312 may include: a first comparator U1 and a second voltage-controlled switch S2. The non-inverting input of the first comparator U1 is coupled to the output Ramp. The inverting input of the first comparator U1 is coupled to the clamping voltage terminal Vd. The non-inverting output of the first comparator U1 is coupled to the controlled input of the second voltage-controlled switch S2. The inverting output of the first comparator U1 is coupled to a second node N2. The first terminal of the second voltage-controlled switch S2 is coupled to a second voltage terminal V2. The second terminal of the second voltage-controlled switch S2 is coupled to a first node N1.

[0056] The pull-down control circuit 313 may include a third voltage-controlled switch S3 and a third resistor r3. The first terminal of the third voltage-controlled switch S3 is coupled to the output terminal Ramp. The second terminal of the third voltage-controlled switch S3 is coupled to the first terminal of the third resistor r3. The controlled input terminal of the third voltage-controlled switch S3 can be coupled to the output terminal of the on-time timer of the DC-DC converter, thereby providing a fixed on-time control signal for the DC-DC converter. The second terminal of the third resistor R3 is coupled to the second voltage terminal V2.

[0057] The output circuit 314 may include a voltage-controlled current source G1 and a first capacitor C1. The non-inverting input of the voltage-controlled current source G1 is coupled to a first node N1, the inverting input of the voltage-controlled current source G1 is coupled to a second voltage terminal V2, the first output of the voltage-controlled current source G1 is coupled to the second terminal of the first capacitor C1 and the second voltage terminal V2, and the second output of the voltage-controlled current source G1 is coupled to the first terminal of the first capacitor C1 and the output terminal Ramp.

[0058] exist Figure 5In the example, a high-voltage signal is input from the first voltage terminal V1, and the second voltage terminal V2 is grounded. Those skilled in the art will understand that, based on the above inventive concept... Figure 5 Any modifications to the circuit shown should also fall within the scope of this disclosure. In such modifications, the ports of the aforementioned components may also have... Figure 5 The examples shown have different configurations. For instance, the inverting input of the first comparator U1 can be coupled to the output Ramp. The non-inverting input of the first comparator U1 can be coupled to the clamping voltage Vd. In this case, the inverting output of the first comparator U1 is coupled to the controlled input of the second voltage-controlled switch S2. The non-inverting output of the first comparator U1 is coupled to the second node N2.

[0059] The following is combined Figure 5 Examples and Figures 7 to 10 The timing diagram is used to illustrate the operation of the adaptive slope compensation circuit 310 for a DC-DC converter based on ACOT control mode. Figures 7 to 9 The following waveforms are shown when the input voltage Vin is 12V and the load current I_Load is 0A, 6A and 12A respectively: output voltage Vout, voltage at node SW, voltage at node Sum, voltage at node Ramp, load current I_Load, current I_L of inductor L, voltage at node FB and voltage at node COMP. Figure 10 The following waveforms are shown when the input voltage Vin is 12V and the load current I_Load varies between 0 and 12A: output voltage Vout, voltage at node SW, voltage at node Sum, voltage at node Ramp, load current I_Load, inductor current I_L, voltage at node FB, and voltage at node COMP. Figures 7 to 10 In the example, the clamping voltage Vd is set to 50mV.

[0060] When node DR is high (i.e., node SW is high) (e.g.) Figure 7 At time t1, the third voltage-controlled switch S3 is closed, and the voltage at the output terminal Ramp is pulled down to ground through the third resistor r3.

[0061] Then, when the voltage of node DR just flips to a low level (i.e., node SW is at a low level) (e.g.) Figure 7At time t2, the voltage at the output terminal Ramp is lower than the clamping voltage Vd. The first comparator U1 outputs a low-level signal from its non-inverting output terminal, and the second voltage-controlled switch S2 opens. The first comparator U1 then outputs a high-level signal from its inverting output terminal, and the first voltage-controlled switch S1 closes. The high-level signal provided by the first voltage source V1 is supplied to the non-inverting input terminal of the voltage-controlled current source G1. The voltage-controlled current source G1 outputs a current signal from its second output terminal to charge the first capacitor C1. The voltage at the first terminal of the first capacitor C1 continuously increases, thus outputting a ramp signal (output signal Ramp) with a certain slope from the output terminal Ramp. When the voltage of the output signal Ramp is higher than the clamping voltage Vd (e.g., when...), the voltage at the output terminal Ramp increases. Figure 7 At time t3, the inverting output of the first comparator U1 outputs a low-level signal, the first voltage-controlled switch S1 opens, and the boost control signal is stopped from being supplied to the output circuit 314. Simultaneously, the non-inverting output of the first comparator U1 outputs a high-level signal, the second voltage-controlled switch S2 closes, and the low-level signal provided by the second voltage source V2 is supplied to the non-inverting input of the voltage-controlled current source G1. Thus, the second output of the voltage-controlled current source G1 stops charging the first capacitor C1. Since the second terminal of the first capacitor C1 is grounded, the voltage at the first terminal of the first capacitor C1 remains unchanged. Therefore, the voltage of the output signal Ramp remains unchanged.

[0062] When node DR is high again (i.e., node SW is high), the third voltage-controlled switch S3 closes, and the voltage at the output terminal Ramp is pulled down to ground through the third resistor r3. At this time, the first capacitor C1 discharges through the third resistor r3.

[0063] exist Figure 10 In the example, it can be observed that as the load current I_Load changes, at certain moments, the fixed on-time control signal is already at a high level (i.e., node SW is at a high level), but Ramp has not yet risen to the clamping voltage Vd before being pulled to ground under the control of the fixed on-time control signal. This allows the output signal Ramp of the adaptive slope compensation circuit 310 to reflect the voltage changes at node FB as much as possible.

[0064] Figure 6 Another exemplary circuit diagram of an adaptive ramp compensation circuit 310 for a DC-DC converter based on ACOT control mode, according to an embodiment of the present disclosure, is shown. Figure 6 The example shows the method for generating Figure 5The clamping voltage signal Vd is generated by a clamping voltage generation circuit 3121. The clamping voltage generation circuit 3121 may include a first resistor r1 and a second resistor r2. The first end of the first resistor r1 is coupled to a third voltage terminal V3, and the second end of the first resistor r1 is coupled to the clamping voltage terminal Vd and the first end of the second resistor r2. The second end of the second resistor r2 is coupled to a second voltage terminal V2. By adjusting the voltage value of the third voltage terminal V3 and the resistance values ​​of the first resistor r1 and the second resistor r2, the desired clamping voltage signal Vd can be obtained. In some embodiments of this disclosure, the third voltage terminal V3 may be coupled to a voltage source inside the DC-DC converter. The value of the first resistor r1 may be fixed, so that when the voltage value of the clamping voltage signal Vd needs to be adjusted, only the second resistor r2 can be replaced to obtain the desired clamping voltage signal Vd. The second resistor r2 may be arranged outside the package of the DC-DC converter to adjust the voltage value of the clamping voltage signal Vd. Alternatively, the value of the second resistor r2 can be fixed, so that when the clamping voltage signal Vd needs to be adjusted, only the first resistor r1 can be replaced to obtain the desired clamping voltage signal Vd. The first resistor r1 can be arranged outside the package of the DC-DC converter to adjust the voltage value of the clamping voltage signal Vd. Alternatively, both the first resistor r1 and the second resistor r2 can be arranged outside the package of the DC-DC converter. In this way, the voltage value of the clamping voltage signal Vd can be adjusted by adjusting the first resistor r1 and the second resistor r2.

[0065] Similarly, the capacitance of the first capacitor C1 affects the slope of the ramp signal. Therefore, the first capacitor C1 can be placed outside the package of the DC-DC converter. This way, when the slope of the ramp signal needs to be adjusted, the desired slope can be obtained by replacing the first capacitor C1.

[0066] In summary, the adaptive slope compensation circuit for a DC-DC converter based on ACOT control mode according to embodiments of this disclosure enables the DC-DC converter to operate stably with an equivalent series resistance of 0Ω for the output capacitor and exhibits a fast response speed. Furthermore, the slope and clamping voltage of the slope signal generated by this adaptive slope compensation circuit are adjustable to meet the requirements of the DC-DC converter in various application scenarios.

[0067] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of apparatuses and methods according to various embodiments of the present disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of an instruction containing one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions marked in the blocks may occur in a different order than those marked in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

[0068] Unless otherwise expressly indicated by the context, the singular form of words used herein and in the appended claims includes the plural form, and vice versa. Thus, when referring to the singular, the plural form of the corresponding term is generally included. Similarly, the terms “comprising” and “including” shall be interpreted as including rather than exclusively. Likewise, the terms “including” and “or” shall be interpreted as including unless such interpretation is expressly prohibited herein. Where the term “example” is used herein, particularly when it follows a set of terms, the “example” is merely exemplary and illustrative and should not be considered exclusive or extensive.

[0069] Further aspects and scope of adaptation become apparent from the description provided herein. It should be understood that various aspects of this application may be implemented individually or in combination with one or more other aspects. It should also be understood that the descriptions and specific embodiments herein are for illustrative purposes only and are not intended to limit the scope of this application.

[0070] Several embodiments of this disclosure have been described in detail above. However, it is obvious that those skilled in the art can make various modifications and variations to the embodiments of this disclosure without departing from the spirit and scope of this disclosure. The scope of protection of this disclosure is defined by the appended claims.

Claims

1. An adaptive slope compensation circuit for a DC-DC converter based on ACOT control mode, comprising: The circuit includes a boost control circuit, a voltage clamping circuit, a pull-down control circuit, and an output circuit. The boost control circuit is configured to generate a boost control signal based on a first voltage signal from a first voltage terminal and a clamping control signal from the voltage clamping circuit, and provide the boost control signal to the output circuit via a first node. The voltage clamping circuit is configured to: generate the clamping control signal and the voltage holding signal based on the output signal output by the output circuit, the clamping voltage signal from the clamping voltage terminal, and the second voltage signal from the second voltage terminal; provide the clamping control signal to the boost control circuit via the second node; and provide the voltage holding signal to the output circuit via the first node. The pull-down control circuit is configured to pull down the output signal output by the output circuit under the control of the fixed on-time control signal of the DC-DC converter; The output circuit is configured to: generate a ramp signal as an output signal under the control of the boost control signal, maintain the voltage of the output signal under the control of the voltage holding signal, and output the output signal from the output terminal; The adaptive ramp compensation circuit is configured such that, under steady-state conditions, when the fixed on-time control signal is low, the adaptive ramp compensation circuit starts generating a ramp signal, and the ramp signal stops rising after the voltage of the ramp signal reaches the clamping voltage; when the fixed on-time control signal is high, the ramp signal is pulled down to 0V. The adaptive ramp compensation circuit is also configured such that, under dynamic conditions, when the fixed on-time control signal is at a low level, the adaptive ramp compensation circuit starts to generate a ramp signal. When the voltage of the ramp signal has not yet reached the clamping voltage but the fixed on-time control signal is at a high level, the ramp signal is pulled down to 0V and held.

2. The adaptive slope compensation circuit according to claim 1, wherein, The boost control circuit includes: a first voltage-controlled switch. Wherein, the first terminal of the first voltage-controlled switch is coupled to the first voltage terminal, the second terminal of the first voltage-controlled switch is coupled to the first node, and the controlled input terminal of the first voltage-controlled switch is coupled to the second node.

3. The adaptive slope compensation circuit according to claim 1, wherein, The voltage clamping circuit includes: a first comparator and a second voltage-controlled switch. Wherein, the first input terminal of the first comparator is coupled to the output terminal, the second input terminal of the first comparator is coupled to the clamping voltage terminal, the first output terminal of the first comparator is coupled to the controlled input terminal of the second voltage-controlled switch, and the second output terminal of the first comparator is coupled to the second node; The first terminal of the second voltage-controlled switch is coupled to the second voltage terminal, and the second terminal of the second voltage-controlled switch is coupled to the first node.

4. The adaptive slope compensation circuit according to claim 3, wherein, The voltage clamping circuit further includes: a first resistor and a second resistor. Wherein, the first end of the first resistor is coupled to the third voltage terminal, and the second end of the first resistor is coupled to the clamping voltage terminal and the first end of the second resistor; The second end of the second resistor is coupled to the second voltage terminal.

5. The adaptive slope compensation circuit according to claim 4, wherein, The first resistor and / or the second resistor are arranged outside the package of the DC-DC converter.

6. The adaptive slope compensation circuit according to claim 1, wherein, The pull-down control circuit includes: a third voltage-controlled switch and a third resistor. Wherein, the first terminal of the third voltage-controlled switch is coupled to the output terminal, the second terminal of the third voltage-controlled switch is coupled to the first terminal of the third resistor, and the controlled input terminal of the third voltage-controlled switch is provided with the fixed on-time control signal of the DC-DC converter; The second end of the third resistor is coupled to the second voltage terminal.

7. The adaptive slope compensation circuit according to claim 1, wherein, The output circuit includes a voltage-controlled current source and a first capacitor. Wherein, the first input terminal of the voltage-controlled current source is coupled to the first node, the second input terminal of the voltage-controlled current source is coupled to the second voltage terminal, the first output terminal of the voltage-controlled current source is coupled to the second terminal of the first capacitor and the second voltage terminal, and the second output terminal of the voltage-controlled current source is coupled to the first terminal of the first capacitor and the output terminal.

8. The adaptive slope compensation circuit according to claim 7, wherein, The first capacitor is disposed outside the package of the DC-DC converter.

9. An adaptive slope compensation circuit for a DC-DC converter based on ACOT control mode, comprising: The system comprises a first voltage-controlled switch, a second voltage-controlled switch, a third voltage-controlled switch, a first comparator, a first capacitor, a first resistor, a second resistor, a third resistor, and a voltage-controlled current source. Wherein, the first terminal of the first voltage-controlled switch is coupled to the first voltage terminal, the second terminal of the first voltage-controlled switch is coupled to the first input terminal of the voltage-controlled current source, and the controlled input terminal of the first voltage-controlled switch is coupled to the second output terminal of the first comparator; The first input terminal of the first comparator is coupled to the output terminal of the adaptive ramp compensation circuit, the second input terminal of the first comparator is coupled to the second terminal of the first resistor and the first terminal of the second resistor, and the first output terminal of the first comparator is coupled to the controlled input terminal of the second voltage-controlled switch. The first terminal of the second voltage-controlled switch is coupled to the second voltage terminal, and the second terminal of the second voltage-controlled switch is coupled to the first input terminal of the voltage-controlled current source; The first end of the first resistor is coupled to the third voltage terminal; The second end of the second resistor is coupled to the second voltage terminal; The second input terminal of the voltage-controlled current source is coupled to the second voltage terminal, the first output terminal of the voltage-controlled current source is coupled to the second terminal of the first capacitor and the second voltage terminal, and the second output terminal of the voltage-controlled current source is coupled to the first terminal of the first capacitor and the output terminal. The first terminal of the third voltage-controlled switch is coupled to the output terminal, the second terminal of the third voltage-controlled switch is coupled to the first terminal of the third resistor, and the controlled input terminal of the third voltage-controlled switch is provided with a fixed on-time control signal of the DC-DC converter; The second end of the third resistor is coupled to the second voltage terminal; The adaptive ramp compensation circuit is configured such that, under steady-state conditions, when the fixed on-time control signal is low, the adaptive ramp compensation circuit starts generating a ramp signal, and the ramp signal stops rising after the voltage of the ramp signal reaches the clamping voltage; when the fixed on-time control signal is high, the ramp signal is pulled down to 0V. The adaptive ramp compensation circuit is also configured such that, under dynamic conditions, when the fixed on-time control signal is at a low level, the adaptive ramp compensation circuit starts to generate a ramp signal. When the voltage of the ramp signal has not yet reached the clamping voltage but the fixed on-time control signal is at a high level, the ramp signal is pulled down to 0V and held.

10. A DC-DC converter based on ACOT control mode, comprising an adaptive ramp compensation circuit according to any one of claims 1 to 9.

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