Data mutual exclusion filtering circuit and data mutual exclusion filtering method

Abstract

The present invention provides a data mutually exclusive filtering circuit and a data mutually exclusive filtering method. The data mutually exclusive filtering circuit provided by the disclosed embodiment The disclosed embodiment provides a data mutually exclusive filtering circuit, including a preprocessing subcircuit and N-level filtering subcircuits, N≥2; each level of filtering subcircuit can compare whether the input data currently received by the main input end is the same as the historical data stored in itself, and feed back the comparison result to the preprocessing subcircuit; the preprocessing subcircuit outputs corresponding data to the first level filtering subcircuit according to the comparison results fed back by the filtering subcircuits at each level; if the comparison results fed back by any level of filtering subcircuits are the same, a preset placeholder is output; if the comparison results fed back by the filtering subcircuits at each level are different, the input data is output.

Description

Technical Field

[0001] The invention belongs to the technical field of data processing, and in particular relates to a data mutual exclusion filtering circuit and a data mutual exclusion filtering method. Background Art

[0002] In the fields of data transmission and image processing based on digital (integrated) circuit technology, when there is a situation where the same data is continuously output in a preset specific neighborhood in the data stream, the problem of merging the same data often arises. For example, in the preprocessing process of grayscale equalization of an image, the grayscale data can be used as the address of a static random access memory (SRAM). When two or more identical grayscale data are continuously input, the operation of the SRAM (due to the read and write latency) will result in a read-write conflict. Alternatively, in the process of data transmission, the transmission of the same data in a limited neighborhood will cause a waste of bandwidth resources, reducing the utilization of hardware resources and bandwidth resources. Summary of the invention

[0003] The present invention aims to solve at least one of the technical problems existing in the prior art and provides a data mutual exclusion filtering circuit, which can mutually exclude data in a data stream within a preset range, that is, merge the same data to avoid problems such as output confusion or read-write address conflicts, and can avoid wasting transmission bandwidth and improve computing efficiency.

[0004] In a first aspect, an embodiment of the present disclosure provides a data mutually exclusive filtering circuit, including a preprocessing subcircuit and an N-stage filtering subcircuit, N≥2; wherein,

[0005] When N=2, the input end of the first-stage filter subcircuit is connected to the preprocessing subcircuit, and the output end is connected to the input end of the second-stage filter subcircuit; the input end of the second-stage filter subcircuit is connected to the output end of the first-stage filter subcircuit, and the output end is connected to the main output end;

[0006] When N>2, the input end of the first-stage filter subcircuit is connected to the preprocessing subcircuit, and the output end is connected to the input end of the second-stage filter subcircuit; the input end of the N-stage filter subcircuit is connected to the output end of the N-1-stage filter subcircuit, and the output end is connected to the main output end; the input end of the M-stage filter subcircuit is connected to the output end of the M-1-stage filter subcircuit, and the output end is connected to the input end of the M+1-stage filter subcircuit; wherein 1<M<N;

[0007] Each level of the filtering subcircuit can compare whether the input data currently received by the main input terminal is the same as the historical data stored in itself, and feed back the comparison result to the preprocessing subcircuit;

[0008] The preprocessing subcircuit outputs corresponding data to the first-stage filtering subcircuit according to the comparison results fed back by the filtering subcircuits at each stage; if the comparison results fed back by the filtering subcircuits at any stage are the same, a preset placeholder is output; if the comparison results fed back by the filtering subcircuits at each stage are different, the input data is output.

[0009] The data mutually exclusive filtering circuit provided by the embodiment of the present disclosure filters the input data when the input data is identical to the historical data in the filtering sub-circuits at each level; and stores the input data in the first-level filtering sub-circuit when the input data is different from the historical data in the filtering sub-circuits at each level. Therefore, within a preset range, data in the data stream can be mutually exclusive, that is, the same data can be merged to avoid problems such as output confusion or read-write address conflicts, and can also avoid wasting transmission bandwidth and improve computing efficiency.

[0010] In some examples, the pre-processing sub-circuit includes a first data selector and an OR gate; each stage of the filtering sub-circuit includes a data register and a comparator;

[0011] The input end of the data register of the first-stage filtering subcircuit is connected to the output end of the first data selector, and the output end is connected to the input end of the data register of the second-stage filtering subcircuit;

[0012] The input end of the data register of the Nth level filter subcircuit is connected to the input end of the data register of the N-1th level filter subcircuit, and the output end is connected to the main output end;

[0013] The input end of the data register of the Mth level filter subcircuit is connected to the output end of the data register of the M-1th level filter subcircuit, and the output end is connected to the input end of the data register of the M+1th level filter subcircuit;

[0014] In each level of the filtering subcircuit, the comparator has a first input terminal, a second input terminal and an output terminal, wherein the first input terminal is connected to the output terminal of the data register, the second input terminal is connected to the main input terminal, and the output terminal is connected to one of the multiple input terminals of the OR gate; wherein the output terminal of the comparator outputs the comparison result;

[0015] The first data selector has a first input terminal, a second input terminal, a first selection terminal and an output terminal, wherein the first input terminal is connected to the main input terminal, the second input terminal is connected to the placeholder output terminal, and the first selection terminal is connected to the output terminal of the OR gate.

[0016] In some examples, the data register of each stage of the filtering subcircuit further includes a clock input terminal connected to a clock signal source; the clock input terminals of each of the data registers are connected to the same clock signal source.

[0017] In some examples, each level of the filtering subcircuit further includes: a frequency counting unit, which is connected to the comparator and the data register of the filtering subcircuit and is used to count the frequency of the same data in each data received by the main input end.

[0018] In some examples, the data mutually exclusive filtering circuit further includes: a main frequency data output terminal; the frequency statistics unit includes: a frequency register and a second data selector; wherein,

[0019] In each level of the filtering subcircuit, the second data selector has a first input terminal, a second input terminal, a second selection terminal and an output terminal, the first input terminal and the second input terminal are both connected to the output terminal of the frequency register, and the frequency data input to the second input terminal is equal to the sum of the frequency data input to the first input terminal and a constant 1; the second selection terminal is connected to the output terminal of the comparator; wherein,

[0020] The output end of the second data selector of the Nth filter subcircuit is connected to the main frequency data output end, and the output ends of the second data selectors of the other filter subcircuits are connected to the input end of the frequency register of the next filter subcircuit;

[0021] The input end of the frequency register of the first-stage filtering subcircuit is connected to the output end of the OR gate.

[0022] In some examples, the frequency statistics unit further includes: an adder, whose input terminal is connected to the output terminal of the frequency register; and whose output terminal is connected to the second input terminal of the second data selector.

[0023] In some examples, the preprocessing subcircuit further includes: a NOT gate; an input end of the NOT gate is connected to an output end of the OR gate; and an output end of the NOT gate is connected to an input end of the frequency register of the first-stage filtering subcircuit.

[0024] In some examples, it also includes: a data filtering subcircuit, which can filter invalid data and pass valid data; the data input to the main input end passes through the data filtering subcircuit and is output to the preprocessing subcircuit and each level of the filtering subcircuit.

[0025] In some examples, the data filtering subcircuit includes an AND gate having an input terminal, an enable terminal and an output terminal, wherein the input terminal serves as the main input terminal, the enable terminal is connected to the enable signal terminal, and the output terminal is connected to the preprocessing subcircuit and each level of the filtering subcircuit.

[0026] In a second aspect, the embodiments of the present disclosure further provide a data mutually exclusive filtering method, which is applied to the above-mentioned data mutually exclusive filtering circuit, and the method comprises the following steps:

[0027] Each level of filtering subcircuit compares the input data currently received by the main input terminal with the historical data stored in itself to see if they are the same, and feeds the comparison result back to the preprocessing subcircuit;

[0028] The preprocessing subcircuit outputs corresponding data to the first-stage filtering subcircuit according to the comparison results fed back by the filtering subcircuits at each stage;

[0029] If the comparison results fed back by the filtering subcircuits at any level are the same, a preset placeholder is output; if the comparison results fed back by the filtering subcircuits at each level are different, the input data is output. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 A schematic diagram of the architecture of an embodiment of a data mutual exclusion filtering circuit provided by an embodiment of the present disclosure;

[0031] Figure 2 A circuit structure diagram of an embodiment of a preprocessing subcircuit of a data mutual exclusion filtering circuit provided in an embodiment of the present disclosure;

[0032] Figure 3 A circuit structure diagram of an embodiment of a filter subcircuit of a data mutual exclusion filter circuit provided in an embodiment of the present disclosure;

[0033] Figure 4 A circuit structure diagram of an embodiment of a data mutual exclusion filter circuit provided by an embodiment of the present disclosure;

[0034] Figure 5 A circuit structure diagram of another embodiment of a data mutual exclusion filter circuit provided in an embodiment of the present disclosure (an embodiment of a two-stage filter subcircuit);

[0035] Figure 6 A circuit structure diagram of another embodiment of a preprocessing subcircuit of a data mutual exclusion filtering circuit provided in an embodiment of the present disclosure;

[0036] Figure 7 A circuit structure diagram of another embodiment of a filter subcircuit of a data mutual exclusion filter circuit provided in an embodiment of the present disclosure;

[0037] Figure 8 A circuit structure diagram of another embodiment of a data mutual exclusion filter circuit provided in an embodiment of the present disclosure;

[0038] Fig. 9 A circuit structure diagram of another embodiment of a data mutual exclusion filter circuit provided in an embodiment of the present disclosure (an embodiment of a two-stage filter subcircuit)

[0039] Fig.10A schematic diagram of simulation waveforms of an embodiment of a data mutual exclusion filter circuit provided in an embodiment of the present disclosure (an embodiment of a two-stage filter subcircuit);

[0040] Fig.11 A schematic diagram of simulation waveforms of another embodiment of a data mutual exclusion filter circuit provided in an embodiment of the present disclosure (an embodiment of an eight-level filter subcircuit);

[0041] Fig.12 A schematic diagram of the architecture of another embodiment of a data mutual exclusion filtering circuit provided in an embodiment of the present disclosure;

[0042] Fig.13 A circuit structure diagram of another embodiment of a data mutual exclusion filter circuit provided in an embodiment of the present disclosure;

[0043] Fig.14 The present invention is a flowchart of an embodiment of a data mutually exclusive filtering method provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0044] In order to make the purpose, technical scheme and advantages of the present invention clearer, the present invention will be further described in detail below in conjunction with the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, rather than all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0045] The shapes and sizes of the components in the drawings do not reflect the actual proportions, and are only intended to facilitate understanding of the contents of the embodiments of the present invention.

[0046] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure should be understood by people with ordinary skills in the field to which the present disclosure belongs. The "first", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, similar words such as "one", "one" or "the" do not indicate quantity restrictions, but indicate that there is at least one. Similar words such as "include" or "comprise" mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Similar words such as "connect" or "connected" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0047] The embodiments of the present disclosure are not limited to the embodiments shown in the drawings, but include modifications of the configurations formed based on the manufacturing process. Therefore, the regions illustrated in the drawings have schematic properties, and the shapes of the regions shown in the drawings illustrate the specific shapes of the regions of the elements, but are not intended to be limiting.

[0048] In a first aspect, an embodiment of the present disclosure provides a data mutually exclusive filtering circuit, comprising a preprocessing subcircuit 100 and an N-stage filtering subcircuit 200, wherein N is an integer and N≥2. The N-stage filtering subcircuit 200 is cascaded, and is respectively referred to as the first-stage filtering subcircuit 200-1, the second-stage filtering subcircuit 200-2, ... the N-stage filtering subcircuit 200-N.

[0049] Specifically, if N=2, that is, the data mutually exclusive filtering circuit only includes a second-level filtering subcircuit 200, then the input end of the first-level filtering subcircuit 200-1 is connected to the preprocessing subcircuit 100, and the output end of the first-level filtering subcircuit 200-1 is connected to the input end of the second-level filtering subcircuit; the input end of the second-level filtering subcircuit is connected to the output end of the first-level filtering subcircuit, and the output end of the second-level filtering subcircuit is connected to the main output end IN of the data mutually exclusive filtering circuit.

[0050] When N>2, the input end of the first-stage filter subcircuit 200-1 is connected to the preprocessing subcircuit 100, and the output end of the first-stage filter subcircuit 200-1 is connected to the input end of the second-stage filter subcircuit; the input end of the Nth-stage (i.e., the last-stage) filter subcircuit 200-N is connected to the output end of the N-1th-stage filter subcircuit 200-(N-1), and the output end of the Nth-stage filter subcircuit 200-N is connected to the main output end IN; the input end of the Mth-stage filter subcircuit 200-M is connected to the output end of the M-1th-stage filter subcircuit 200-(M-1), and the output end of the Mth-stage filter subcircuit 200-M is connected to the input end of the M+1th-stage filter subcircuit 200-(M+1); wherein M is an integer, and 1<M<N.

[0051] That is to say, for the filter subcircuit located between the first-stage filter subcircuit and the last-stage filter subcircuit, the input end of the filter subcircuit is always connected to the output end of the previous-stage filter subcircuit, and the output end of the filter subcircuit is always connected to the input end of the next-stage filter subcircuit, so that when a first-stage filter subcircuit stores an input data, the historical data originally stored in the filter subcircuit is transmitted to the next-stage filter subcircuit for storage. Each time the input data currently received by the main input terminal IN of the data mutually exclusive filter circuit is received, the preprocessing subcircuit 100 always decides whether to store it in the first-stage filter subcircuit 200-1. If the first-stage filter subcircuit 200-1 stores the input data, the historical data stored in the first-stage filter subcircuit 200-1 itself is transmitted to the second-stage filter subcircuit 200-2, and the historical data stored in the second-stage filter subcircuit 200-2 is transmitted to the third-stage filter subcircuit 200-3... The N-th stage filter subcircuit 200-N stores the historical data transmitted by the N-1-th stage filter subcircuit 200-(N-1), and then outputs the historical data stored in itself to the subsequent circuit through the main output terminal OUT as the output data data_out of the data mutually exclusive filter circuit. That is, data is always transmitted from the first-stage filtering subcircuit 200-1 to the N-stage step by step, and the data output by the N-stage is the output data data_out of the data mutually exclusive filtering circuit, that is, a pipelined data mutually exclusive filtering circuit is formed, which can realize continuous input and continuous output of data and can be adapted to the pipeline architecture.

[0052] Furthermore, whenever the main input terminal IN of the data mutually exclusive filtering subcircuit receives input data, it will first be transmitted to each level of the filtering subcircuit 200 in the filtering subcircuit 200 (but will not be stored first), and each level of the filtering subcircuit 200 can compare whether the input data data_in currently received by the main input terminal IN is the same as the historical data stored in itself, and feed back the comparison result to the pre-processing subcircuit 100; the pre-processing subcircuit 100 outputs the corresponding data (such as a preset placeholder or the currently received input) to the first level filtering subcircuit 200 according to the comparison results fed back by the filtering subcircuits 200 at each level. Specifically, if the comparison results fed back by any level of filtering subcircuit 200 are the same, that is, the current input data is the same as the historical data stored in any level of filtering subcircuit 200, then the preprocessing subcircuit 100 outputs a preset placeholder to the first level filtering subcircuit 200; if the comparison results fed back by the filtering subcircuit 200 at each level are different, that is, the current input data is different from the historical data stored in the filtering subcircuit 200 at each level, then the preprocessing subcircuit 100 outputs the input data data_in to the first level filtering subcircuit 200-1. The preprocessing subcircuit 100 outputs the preset placeholder or input data data_in to the first level filtering subcircuit 200-1, and the first level filtering subcircuit 200-1 stores the corresponding placeholder or input data data_in, and stores the historical data stored in the second level filtering subcircuit 200-2, and then the data is updated step by step according to the above. When the input data data_in is identical to the historical data in each level of the filtering sub-circuit 200, the input data data_in is filtered; only when the input data data_in is different from the historical data in each level of the filtering sub-circuit 200, the input data data_in is stored in the first level filtering sub-circuit 200-1. Therefore, within a preset range, the data in the data stream formed by multiple consecutive input data data_in can be mutually exclusive. That is to say, if the same data exists in each data within a preset range of each segment of the data stream, the data mutual exclusion circuit only outputs the first data, filters out other data identical to the data, and outputs a placeholder, which is equivalent to merging the same data to avoid problems such as output confusion or read-write address conflicts, and can avoid waste of transmission bandwidth and improve computing efficiency. It can be understood that each data in the data stream passes through the data mutually exclusive filtering circuit and is only compared with the historical data stored in each level of filtering sub-circuit 200. Therefore, the number of filtering sub-circuits 200 and the number of pre-processing sub-circuits 100 define the filtering range of the data mutually exclusive filtering circuit (i.e., the above-mentioned preset range). The pre-processing sub-circuit 100 must exist and the number is 1. Therefore, by adjusting the number of filtering sub-circuits 200, the filtering range of the data mutually exclusive filtering circuit can be adjusted.It can be understood that, for data processing, the above filtering range is equivalent to the size of the neighborhood, that is, the data streams are mutually exclusive within the preset range, which is equivalent to the data streams being mutually exclusive within the preset neighborhood.

[0053] It should be noted that, for the data mutually exclusive filter circuit in the initialization state, the data stored in each filter sub-circuit 200 is 0, and it can be regarded that the historical data of each filter sub-circuit 200 in the initialization state is 0.

[0054] It should be noted that the placeholder can be any constant, such as 0. The placeholder is only used for placeholding and does not affect the data in the data stream. The following description is based on the placeholder being 0 as an example.

[0055] In some examples, the preprocessing subcircuit 100 may have a variety of circuit structures, and the filtering subcircuit 200 may also have a variety of circuit structures. Figure 2-Figure 4 The pre-processing sub-circuit 100 may include a first data selector MUX1 and an OR gate (a device represented by OR in the figure), the first data selector MUX1 has a first input terminal m1, a second input terminal m2, a first selection terminal m4 and an output terminal m3, and the OR gate has a plurality of input terminals r1-rN and an output terminal o1. Each stage of the filtering sub-circuit 200 includes a data register Reg_data and a comparator C, the data register Reg_data has an input terminal d and an output terminal q, and the comparator C has a first input terminal p1, a second input terminal p2 and an output terminal p3.

[0056] It should be noted that, in order to facilitate the description of the data register Reg_data and the comparator C of each level of the filtering sub-circuit 200, the data registers of the 1st level filtering sub-circuit to the Nth level filtering sub-circuit are respectively recorded as data registers Reg_data-1, Reg_data-2...Reg_data-N; the input terminal d and the output terminal q of the data register Reg_data are respectively recorded as d1, d2...dN and q1, q2...qN; the comparator C is respectively recorded as C-1, C-2...CN; the first input terminal p1, the second input terminal p2 and the output terminal p3 of the comparator C are respectively recorded as p11, p21...pN1; p12, p22...pN2; p13, p23...pN3.

[0057] Specifically, see Figure 4 , Figure 5, the input terminal d1 of the data register Reg_data-1 of the first-stage filter subcircuit 200-1 is connected to the output terminal m3 of the first data selector MUX1 of the preprocessing subcircuit 100, the output terminal q1 of the data register Reg_data-1 of the first-stage filter subcircuit 200-1 is connected to the input terminal d2 of the data register Reg_data-2 of the second-stage filter subcircuit 200-2; the input terminal dN of the data register Reg_data-N of the N-stage filter subcircuit 200-N is connected to the input terminal d(N-1) of the data register Reg_data-(N-1) of the N-1-stage filter subcircuit 200-(N-1), and the output terminal qN of the data register Reg_data-N of the N-stage filter subcircuit 200-N is connected to the main output terminal OUT1 of the data mutually exclusive filter subcircuit. If N=2, then refer to Figure 5 , the data mutually exclusive filter circuit only includes the first-stage filter subcircuit 200-1 and the second-stage filter subcircuit 200-2. Accordingly, if N=2, the neighborhood of the data mutually exclusive filter circuit is N+1=3. If there is the same data in any three adjacent data in the data stream, only the first data is output, and other data identical to the data are filtered. The same applies below. If N>2, the input terminal dM of the data register Reg_data-M of the M-th stage filter subcircuit 200-M is connected to the output terminal q(M-1) of the data register Reg_data(M-1) of the M-1st stage filter subcircuit 200-(M-1), and the output terminal qM of the data register Reg_data-M of the M-th stage filter subcircuit 200-M is connected to the input terminal d(M+1) of the data register Reg_data-(M+1) of the M+1st stage filter subcircuit 200-(M+1). If the data register Reg_data of a certain level of filtering sub-circuit 200 receives and stores a data, the historical data stored in it will be transmitted to the data register Reg_data of the next level of filtering sub-circuit 200, and the data will be gradually shifted in sequence. The data register Reg_data of the last level of filtering sub-circuit 200 will output the historical data stored in it as the output data data_out of the data mutually exclusive filtering circuit.

[0058] Further, in each level of filtering subcircuit 200, the first input terminal p1 of the comparator C is connected to the output terminal q of the data register Reg_data of the filtering subcircuit 200 of the level, the second input terminal p2 of the comparator C is connected to the main input terminal IN of the data mutual exclusion circuit, the output terminal p3 of the comparator C is connected to one of the multiple input terminals r1-rN of the OR gate of the preprocessing circuit 100, and the output terminal o1 of the OR gate is connected to the first selection terminal m4 of the first data selector MUX1. The first input terminal m1 of the first data selector MUX1 is connected to the main input terminal IN of the data mutual exclusion filtering circuit, the second input terminal m2 of the first data selector MUX1 is connected to the placeholder output terminal h, the placeholder output terminal h outputs the placeholder, and the first selection terminal m4 of the first data selector MUX1 is connected to the output terminal o1 of the OR gate.

[0059] In some examples, the data register Reg_data of each level of filtering subcircuit 200 also includes a clock input terminal, the clock input terminal is connected to a clock signal source, and the clock signal source outputs a clock signal clk. The clock signal clk includes alternating high and low levels, each alternating high and low level is a clock cycle clk cycle, and each clock cycle clk cycle main signal terminal IN receives an input data, that is, the processing cycle of a single data of the data mutual exclusion filtering circuit is a clock cycle clk cycle to receive an input data, which can be adapted to the pipeline architecture. In addition, since the pre-processing circuit 100 is a pure logic circuit, it can be regarded as having no delay. Therefore, the read and write latency (latency) of the data mutual exclusion filtering circuit can be the processing cycle time of each level of filtering subcircuit 200, that is, the latency is N clock cycles clkcycle. For the preset neighborhood (that is, the preset range), the relationship between the size of the neighborhood and the delay (latency) is K-1, K is the size of the neighborhood, K is an integer, and K=N-1. With Figure 5 Taking the three-neighborhood data mutually exclusive filtering circuit shown as an example, the processing cycle of a single data of the data mutually exclusive filtering circuit is 1 clock cycle clk cycle, and the latency is 2 clock cycles clk cycles.

[0060] It should be noted that, since the data mutually exclusive filtering circuit provided in the embodiment of the present disclosure has a single data processing cycle of one clock cycle clk cycle, it can be understood that an input data data_in or output data data_out mentioned in this article is the data of the data stream in each clock cycle clk cycle.

[0061] In some examples, the clock input end of the data register Reg_data of each level of the filtering sub-circuit 200 is connected to the same clock signal source and receives the same clock signal clk; of course, different clock signal sources can also be connected, but each clock signal source outputs a clock signal clk with the same period, which is not limited here.

[0062] The working principle of the data mutually exclusive filtering subcircuit provided by the embodiment of the present disclosure is as follows: the data stream is input through the main input terminal IN of the data mutually exclusive filtering circuit, and then output from the main output terminal OUT1 after filtering (merging the same data in a preset neighborhood). Specifically, in response to the clock signal clk, the main input terminal IN of the data mutually exclusive filtering circuit receives an input data data_in in each clock cycle clk cycle, and the input data data_in is first transmitted to the first input terminal m1 of the first data selector MUX1 of the pre-processing subcircuit 100, and the second input terminal p2 of the comparator C of each level of the filtering subcircuit 200, and the first input terminal p1 of each comparator C is respectively connected to the output terminal q of the data register Reg_data in the filtering subcircuit 200 to which it belongs, so as to obtain the historical data currently stored in the data register Reg_data, and the comparator C compares the current input data data_in with the historical data stored in the data register Reg_data to determine whether the two are the same, and feeds back the comparison result to one of the multiple input terminals r1-rN of the OR gate of the pre-processing subcircuit 100 through the output terminal p3 of the comparator C. Among them, if the comparator C compares and finds that the current input data data_in is the same as the historical data stored in the data register Reg_data, the comparison result output by the output terminal p3 is 1; if the comparison finds that the current input data data_in is different from the historical data stored in the data register Reg_data, the comparison result output by the output terminal p3 is 0.

[0063] The multiple input terminals r1-rN of the OR gate respectively receive the comparison results fed back by the output terminals p3 of the comparators C of the filter sub-circuits 200 at each level. If the historical data stored in the data register Reg_data of any filter sub-circuit 200 at each level is the same as the current input data data_in, that is, if the comparison result fed back by the output terminal p3 of the comparator C of any filter sub-circuit 200 is 1, the output terminal 01 of the OR gate outputs 1 to the first selection terminal m4 of the first data selector MUX1, selects the second input terminal m2, and turns the placeholder output terminal h is written into the input terminal d1 of the data register Reg_data-1 of the first-stage filter sub-circuit 200-1 through the output terminal m3 of the first data selector MUX1; accordingly, if the historical data stored in the data register Reg_data of any stage of the filter sub-circuit 200 is different from the current input data data_in, that is, if the comparison results fed back from the output terminals p3 of the comparators C of the filter sub-circuits 200 are all 0, then the output terminal 01 of the OR gate is fed back to the first selection terminal d2 of the first data selector MUX1. m4 outputs 0, selects the first input terminal m1, and writes the current input data data_in into the input terminal d1 of the data register Reg_data-1 of the first-stage filter sub-circuit 200-1 through the output terminal m3 of the first data selector MUX1; no matter whether the data register Reg_data-1 of the first-stage filter sub-circuit 200-1 stores the placeholder or the input data data_in, when storing the corresponding data, the historical data originally stored in itself will be transferred to the data register Reg_data-2 of the second-stage filter sub-circuit 200-2; after the data register Reg_data-2 of the second-stage filter sub-circuit 200-2 stores the data transmitted by the data register Reg_data-1 of the first-stage filter sub-circuit 200-1, the historical data originally stored will be transferred to the data register Reg_data-3 of the third-stage filter sub-circuit 200-3... After gradually storing the data, the output terminal qN of the data register Reg_data-N of the N-stage filter sub-circuit 200-N outputs the historical data stored in itself as the output data data_out via the main output terminal OUT1.

[0064] It should be noted that the data register Reg_data of each level of filtering sub-circuit 200 takes one clock cycle clk cycle to store and output data. Therefore, it takes N clock cycles clk cycles from the pre-processing sub-circuit 100 receiving an input data data_in to the output end qN of the data register Reg_data-N of the N-th level filtering sub-circuit 200-N outputting the output data data_out. That is, the latency of the data mutually exclusive filtering circuit is N clock cycles clk cycles.

[0065] In summary, in each input data data_in input circuit, the preprocessing subcircuit 100 determines whether to push the input data data_in into the first-stage filtering subcircuit 200-1; if there is no data identical to the input data data_in within the preset neighborhood (i.e., each level of filtering subcircuit 200), the input data data_in is pushed into the first-stage filtering subcircuit 200-1; if there is data identical to the input data data_in within the preset neighborhood (i.e., each level of filtering subcircuit 200), the input data data_in is filtered and the placeholder is pushed into the first-stage filtering subcircuit 200-1. After the data (placeholder or input data data_in) is stored in the first-stage filtering subcircuit 200-1, it is transmitted step by step in response to the clock signal clk, so it can be ensured that after a data stream is filtered by the data mutually exclusive filtering circuit, there is no identical data within any neighborhood, and the order of the data stream is not changed. If the range of the neighborhood (i.e., the number of filtering sub-circuits 200) is set according to the processing cycle of the subsequent circuit, it can prevent the subsequent circuit from continuously receiving the same data in adjacent cycles, causing output confusion, malfunction, etc.; or in data processing, it can prevent a large amount of invalid identical data from existing in a short period of time, causing bandwidth waste and read conflicts, etc.

[0066] For some examples, see Figure 6-Figure 9 In the data mutually exclusive filtering circuit provided in the embodiment of the present disclosure, each level of filtering subcircuit 200 further includes a frequency statistics unit, which is connected to the comparator C1 of the filtering subcircuit 200 of the level, and is connected to the data register Reg_data of the filtering subcircuit 200 of the level, and the frequency statistics unit is used to count the frequency of the same data in each data received by the main input terminal. That is, the data mutually exclusive filtering circuit can merge the same data in the preset neighborhood in the data stream, and can count the number of times the same data appears (i.e., the frequency). For example, if the data mutually exclusive filtering circuit provided by the embodiment of the present disclosure is applied in the field of grayscale histogram statistics, the data stream composed of the grayscale values ​​of the image is input into the circuit, the same grayscale values ​​can be merged within a preset neighborhood, and the number of the same grayscale values ​​(i.e., frequency) can be counted, thereby reducing the amount of data processing. The filtered data and the frequency statistics results are input into the SRAM, which can avoid the latency conflict problem of the SRAM reading and writing the same address (address) after the data stream is input into the static random-access memory (SRAM), and the filtered data and the frequency statistics results can be used to perform equalization processing on the image.

[0067] For some examples, see Figure 6-Figure 9The data mutually exclusive filtering circuit also includes a main frequency data output terminal OUT2 for outputting the frequency statistics result. The frequency statistics unit may include a variety of circuit structures, for example, it may include a frequency register Reg_label and a second data selector MUX2. Among them, the frequency register Reg_label has an input terminal b and an output terminal e, and the second data selector MUX2 specifically has a first input terminal u1, a second input terminal u2, a second selection terminal u4 and an output terminal u3.

[0068] It should be noted that, in order to facilitate the description of the frequency register Reg_label and the second data selector MUX2 of the frequency statistics unit of each level of filtering sub-circuit 200, the frequency registers Reg_label of the 1st level filtering sub-circuit to the Nth level filtering sub-circuit are respectively recorded as Reg_label-1, Reg_label-2...Reg_label-N; the input terminal b and the output terminal e of the frequency register Reg_label are respectively recorded as b1, b2...bN and e1, e2...eN; the second data selector MUX2 is respectively recorded as MUX2-1, MUX2-2...MUX2-N; the first input terminal u1, the second input terminal u2, the second selection terminal u4 and the output terminal u3 of the second data selector MUX2 are respectively recorded as u11, u21...uN1; u12, u22...uN2; u13, u23...uN3; u14, u24...uN4.

[0069] Specifically, see Figure 8 , Fig. 9 In each level of filtering sub-circuit 200, the first input terminal u1 and the second input terminal u2 of the second data selector MUX2 are connected to the output terminal e of the frequency register Reg_label of the filtering sub-circuit 200 to which the second data selector MUX2 belongs, and the frequency data input by the second input terminal u2 of the second data selector MUX2 is equal to the sum of the frequency data input by the first input terminal u1 of the second data selector MUX2 and the constant 1; the second selection terminal u4 of the second data selector MUX2 is connected to the output terminal p3 of the comparator C of the filtering sub-circuit 200 to which the second data selector MUX2 belongs, and receives the comparison result output by the comparator C. Among them, the output terminal uN3 of the second data selector MUX2-N of the Nth level (last level) filter subcircuit 200-N is connected to the main frequency data output terminal OUT2 of the data mutually exclusive filter circuit, that is, the frequency data output by the output terminal uN3 of the second data selector MUX2-N of the Nth level (last level) filter subcircuit 200-N is used as the frequency data label_out of the main frequency data output terminal OUT2. The output terminal u3 of the second data selector MUX2 of the other levels of filter subcircuits 200 is connected to the input terminal e of the frequency register Reg_label of the next level of filter subcircuit 200.

[0070] Furthermore, the input terminal b1 of the frequency register Reg_label-1 of the first-stage filter subcircuit 200-1 is connected to the preprocessing subcircuit 100, specifically, it can be connected to the output terminal 01 of the OR gate of the preprocessing subcircuit 100, and the output terminal e1 of the frequency register Reg_label-1 of the first-stage filter subcircuit 200-1 is connected to the first input terminal u11 and the second input terminal u22 of the second data selector MUX2-1 of the first-stage filter subcircuit 200-1. After that, the input terminal b of the frequency register Reg_label of each stage of the filter subcircuit 200 is connected to the output terminal e of the frequency register Reg_label of the previous stage of the filter subcircuit 300, and the output terminal of the frequency register Reg_label of each stage of the filter subcircuit 200 is connected to the first input terminal u1 and the second input terminal u2 of the second data selector MUX2 of the filter subcircuit 200 to which the frequency register Reg_label belongs.

[0071] The working principle of the data mutually exclusive filtering subcircuit provided in the embodiment of the present disclosure is as follows: the second data selector MUX of any level of filtering subcircuit 200 selects the frequency data of the statistical data to be added by 1 or to maintain the original frequency data according to the comparison result of the comparator C, so as to perform statistics, and stores the frequency data of the data with the data into the next level of filtering subcircuit. Specifically, the comparator C of each level of filtering subcircuit 200 compares and determines whether the current input data data_in is the same as the historical data stored in the data register Reg_data. If they are the same, the output terminal p3 of the comparator C outputs 1; if they are different, the output terminal p3 of the comparator C outputs 0. The output terminal p3 of the comparator C is connected to the second selection terminal u4 of the second data selector MUX2 of the filtering subcircuit 200 to which it belongs. In response to the signal of the second selection terminal u4, if the second selection terminal u4 of the second data selector MUX2 outputs 1, it means that the current input data data_in is the same as the historical data stored in the data register Reg_data, so the frequency data corresponding to the historical data stored in the current frequency register Reg_label should be increased by 1, then the second input terminal u2 of the second data selector MUX2 is selected, and the frequency data after addition by 1 is written from the output terminal u3 to the input terminal b of the frequency register Reg_label of the next-level filtering sub-circuit 200; correspondingly, if the second selection terminal u4 of the second data selector MUX2 outputs 0, it means that the current input data data_in is different from the historical data stored in the data register Reg_data, so the frequency data corresponding to the historical data stored in the current frequency register Reg_label remains unchanged, then the first input terminal u1 of the second data selector MUX2 is selected, and the original frequency data is written from the output terminal u3 to the input terminal b of the frequency register Reg_label of the next-level filtering sub-circuit 200. Whenever the frequency register Reg_label of a certain level of filtering subcircuit 200 receives frequency data input by the frequency register Reg_label of the previous level, it will transfer the historical frequency data originally stored in itself to the frequency register Reg_label of the next level of filtering subcircuit 200 when storing the frequency data. After gradually transmitting the frequency data, the output end eN of the frequency register Reg_label-N of the Nth level filtering subcircuit 200-N outputs the historical frequency data stored in itself as the frequency data label_out through the main frequency data output end OUT2.

[0072] Furthermore, since in each clock cycle, the data register Reg_data of the filtering subcircuit 200 will store its own stored historical data into the data register Reg_data of the next filtering subcircuit 200, the frequency data corresponding to the historical data stored in the data register Reg_data should also be transmitted to the next filtering subcircuit 200 along with the historical data. Therefore, the output end u3 of the second data selector MUX2 of each filtering subcircuit 200 is always connected to the input end d2 of the frequency register Reg_label of the next filtering subcircuit 200, ensuring that the positions of the data and the frequency data of the data are corresponding, so that after passing through the data mutually exclusive filtering circuit provided in this embodiment, the same data in the data stream within a preset neighborhood is merged, and the frequency of occurrence of each data in the statistical data stream can be counted.

[0073] In some examples, the frequency statistics unit may further include an adder add, which can perform a self-addition operation. Specifically, the input end of the adder add is connected to the output end e of the frequency register Reg_label of the filter subcircuit 200 to which the adder add belongs; the output end of the adder add is connected to the second input end u2 of the second data selector MUX2. The first input end u1 of the second data selector MUX2 is not provided with an adder, so that the frequency data output by the output end e of the frequency register Reg_label is connected to the first input end u1 and the second input end u2 of the second data selector MUX2, so that the frequency data of the second input end u2 = the frequency data of the first input end u1 + 1.

[0074] It should be noted that, in order to facilitate description of the adder add of the frequency statistics unit of each filter subcircuit 200, the adders add of the 1st filter subcircuit to the Nth filter subcircuit are respectively recorded as add-1, add-2, ..., add-N.

[0075] In some examples, the preprocessing subcircuit 100 may also include a NOT gate (a device represented by NOT in the figure). The NOT gate includes an input terminal t1 and an output terminal t2. The input terminal t1 of the NOT gate is connected to the output terminal o1 of the OR gate; the output terminal t2 of the NOT gate is connected to the input terminal b1 of the frequency register Reg_label of the first-stage filtering subcircuit 200. If the data mutually exclusive filter circuit is initialized, the data in the data register Reg_data of each level of the filter sub-circuit 200 is all 0. Therefore, when the first non-zero input data data_in is input to the main input terminal IN, the comparison results of the comparators C of each level of the filter sub-circuit 200 are all 0 (i.e. different). After being fed back to the OR gate of the preprocessing sub-circuit 100, the output terminal o1 of the OR gate outputs 0, and the input data data_in is stored in the data register Reg_data of the first-level filter sub-circuit 200-1. At this time, the corresponding frequency register Reg_label should store 1. However, if the input terminal b1 of the frequency register Reg_label of the first-level filter sub-circuit is directly connected to the output terminal o1 of the OR gate, 0 will be stored. Therefore, the output result of the output terminal o1 of the OR gate is inverted to 1 by the NOT gate, and then input to the input terminal b1 of the frequency register Reg_label of the filter sub-circuit, so that 1 is stored in the frequency register Reg_label, so as to ensure the accuracy of the statistical results.

[0076] In some examples, the frequency register Reg_label of each filter subcircuit 200 further includes a clock input terminal, the clock input terminal of the frequency register Reg_label is connected to a clock signal source, and the clock signal source outputs a clock signal clk. In each clock cycle clk cycle, the frequency register Reg_label stores a frequency data and outputs a historical frequency data.

[0077] In some examples, the clock input ends of the data register Reg_data and the frequency register Reg_label of each level of the filtering sub-circuit 200 are connected to the same clock signal source and receive the same clock signal clk; of course, different clock signal sources can also be connected, but each clock signal source outputs a clock signal clk with the same period, which is not limited here.

[0078] See also Fig. 9 , Fig.10 , Fig.10 For Fig. 9The waveform diagram of the simulation of the data mutually exclusive filter circuit as a model, the data mutually exclusive filter circuit includes a two-stage filter subcircuit 200, that is, N = 2, then latency = N clk cycles = 2 clock cycles clk cycles, the preset neighborhood is N + 1 = 3, that is, the same input data of the data stream within 3 clock cycles clk cycles are merged, and the frequency of each data can be counted. After simulation verification, it can be seen that when the input data data_in outputs the first 8, the output data data_out outputs 8 after 2 clock cycles clk cycles, and it can be seen that the latency is 2 clock cycles clk cycles. Moreover, the input data data_in has two 8s in 3 clock cycles clk cycles, so the two 8s are merged into 1 8 for output, and the placeholder 0 is output in another clock cycle clk cycles, and the frequency data is 2; and the input data data_in is 96 in 5 clock cycles clk cycles. Since the neighborhood range of the circuit is 3clk cycles, the 96 in 5 cycles is divided into 3 96s and 2 96s for merging, and the output data data_out corresponds to 96 in 1 clk cycle + placeholder 0 in 3 clk cycles + 96 in 1 clk cycle, and the frequency data are also expressed as 3 96s and 2 96s respectively. It can be verified that the data mutual exclusion filtering circuit can realize the above-mentioned data mutual exclusion filtering function and frequency statistics function.

[0079] It should be noted that the above description is based on the data register Reg_data and the frequency register Reg_label of each level of the filter sub-circuit 200 being 8-bit registers. Of course, registers with other bits may also be selected, which is not limited here.

[0080] Furthermore, data mutual exclusion filtering in a larger range can be performed by adjusting the preset neighborhood range (ie, increasing / decreasing the number of filtering subcircuits 200). Fig.11 , Fig.11The data mutually exclusive filter circuit includes 8 levels of filter subcircuits 200, that is, N=8, then latency=8 clk cycles=8 clock cycles clk cycles, and the preset neighborhood is N+1=9, that is, the same input data of the data stream within 9 clock cycles clk cycles are merged, and the frequency of each data can be counted. After simulation verification, it can be seen that when the input data data_in outputs the first 8, the output data data_out outputs 8 after 9 clock cycles clkcycles, and it can be seen that the latency is 9 clock cycles clk cycles. In addition, the same data in the input data data_in within 9 clock cycles clk cycles are all merged, and the correct frequency data is obtained. Therefore, the required neighborhood range can be adjusted as needed.

[0081] For some examples, see Figure 12-13 The data mutually exclusive filtering circuit provided in the embodiment of the present disclosure may also include a data filtering subcircuit 300. The data filtering subcircuit 300 can filter out invalid data in the data stream and allow valid data in the data stream to pass through. The data stream passes through the data filtering subcircuit 300 to filter out valid data as input data data_in and input into the preprocessing subcircuit 100 and each filtering subcircuit 200.

[0082] In some examples, the data screening subcircuit 300 may include multiple types of circuit structures. For example, the data screening subcircuit 300 may include an AND gate (a device represented by AND in the figure), the AND gate having an input terminal a1, an enable terminal en and an output terminal a2, the input terminal a1 of the AND gate serves as the main input terminal IN of the data mutual exclusion filter circuit to receive the input data data_in; the enable terminal en of the AND gate is connected to the enable signal terminal, and the enable signal terminal provides an enable signal; the output terminal a2 of the AND gate is connected to the pre-processing subcircuit 100 and each level of filtering subcircuit 200. By modulating the effective level of the enable signal, only when the enable signal outputs an effective level, the input data data_in is valid data and enters the subsequent pre-processing subcircuit 100 and filtering subcircuit 200; if the enable signal is an invalid level, the input data data_in is filtered as invalid data.

[0083] In summary, the data mutual exclusion filter circuit provided by the embodiment of the present disclosure can be applied in a variety of fields, including image compression coding, data statistics, data channel (compression) coding, etc. By merging the same data in the data stream, the operation efficiency can be effectively improved. The data mutual exclusion filter circuit is adapted to the Pipeline architecture so that it has technical advantages such as fast operation speed and high bandwidth support, and the solution can be applied to custom integrated circuits (Application Specific Integrated Circuit, ASIC), etc., which is conducive to integration.

[0084] Second, see Fig.14 The embodiment of the present disclosure also provides a data mutual exclusion filtering method, which is applied to the above-mentioned data mutual exclusion filtering circuit, and the method comprises the following steps:

[0085] S1 . Each level of filtering sub-circuit 200 compares whether the input data data_in currently received by the main input terminal IN is the same as the historical data stored in itself, and feeds back the comparison result to the pre-processing sub-circuit 100 .

[0086] Specifically, in response to the clock signal clk, the main input terminal IN of the data mutually exclusive filtering circuit receives an input data data_in in each clock cycle clk cycle. The input data data_in is first transmitted to the first input terminal m1 of the first data selector MUX1 of the pre-processing sub-circuit 100, and the second input terminal p2 of the comparator C of each level of the filtering sub-circuit 200, and the first input terminal p1 of each comparator C is respectively connected to the output terminal q of the data register Reg_data in the corresponding filtering sub-circuit 200 to obtain the historical data currently stored in the data register Reg_data. The comparator C compares the current input data data_in with the historical data stored in the data register Reg_data to determine whether the two are the same, and feeds back the comparison result to one of the multiple input terminals r1-rN of the OR gate of the pre-processing sub-circuit 100 through the output terminal p3 of the comparator C. Among them, if the comparator C compares and finds that the current input data data_in is the same as the historical data stored in the data register Reg_data, the comparison result output by the output terminal p3 is 1; if the comparison finds that the current input data data_in is different from the historical data stored in the data register Reg_data, the comparison result output by the output terminal p3 is 0.

[0087] S2. The preprocessing subcircuit 100 outputs corresponding data to the first-stage filtering subcircuit 200 according to the comparison results fed back by the filtering subcircuits 200 at each stage.

[0088] Specifically, the multiple input terminals r1 -rN of the OR gate respectively receive the comparison results fed back from the output terminals p3 of the comparators C of the filter sub-circuits 200 of each stage.

[0089] S31 , if the comparison results fed back by any one-stage filtering sub-circuit 200 are the same, the pre-processing sub-circuit 100 outputs a preset placeholder to the first-stage filtering sub-circuit 200 .

[0090] Specifically, if the historical data stored in the data register Reg_data of any level of the filtering sub-circuit 200 in the filtering sub-circuit 200 is the same as the current input data data_in, that is, if the comparison result fed back by the output terminal p3 of the comparator C of any level of the filtering sub-circuit 200 is 1, then the output terminal 01 of the OR gate outputs 1 to the first selection terminal m4 of the first data selector MUX1, selects the second input terminal m2, and writes the placeholder output by the placeholder output terminal h into the input terminal d1 of the data register Reg_data-1 of the first level filtering sub-circuit 200-1 through the output terminal m3 of the first data selector MUX1.

[0091] S31 ′: If the comparison results fed back by the filter sub-circuits 200 at each level are all different, the pre-processing sub-circuit 100 outputs the input data to the first-stage filter sub-circuit 200 .

[0092] Specifically, if the historical data stored in the data register Reg_data of any level of the filtering sub-circuit 200 in the filtering sub-circuit 200 is different from the current input data data_in, that is, if the comparison results fed back by the output terminals p3 of the comparator C of the filtering sub-circuit 200 at each level are all 0, then the output terminal 01 of the OR gate outputs 0 to the first selection terminal m4 of the first data selector MUX1, selects the first input terminal m1, and writes the current input data data_in into the input terminal d1 of the data register Reg_data-1 of the first level filtering sub-circuit 200-1 through the output terminal m3 of the first data selector MUX1.

[0093] Optionally, the data mutually exclusive filtering method provided by the embodiment of the present disclosure further includes: when each filtering sub-circuit 200 stores input data data_in, the historical data stored in the filtering sub-circuit 200 is input into the next filtering sub-circuit 200 .

[0094] Specifically, the input data data_in is always transmitted gradually. No matter whether the data register Reg_data-1 of the first-level filter sub-circuit 200-1 stores the placeholder or the input data data_in, the historical data originally stored in itself will be transferred to the data register Reg_data-2 of the second-level filter sub-circuit 200-2 when the corresponding data is stored; after the data register Reg_data-2 of the second-level filter sub-circuit 200-2 stores the data transmitted by the data register Reg_data-1 of the first-level filter sub-circuit 200-1, the historical data originally stored will be transferred to the data register Reg_data-3 of the third-level filter sub-circuit 200-3... After the data is gradually stored, the output terminal qN of the data register Reg_data-N of the N-th level filter sub-circuit 200-N outputs the historical data stored in itself as the output data data_out via the main output terminal OUT1.

[0095] Optionally, the data mutually exclusive filtering method provided by the embodiment of the present disclosure further includes: counting the frequency of each input data, and transmitting the frequency of each input data to the next filtering sub-circuit along with the input data.

[0096] Specifically, the second data selector MUX of any level of filtering subcircuit 200 selects to add 1 to the frequency data of the statistical data or maintain the original frequency data according to the comparison result of the comparator C, so as to perform statistics, and stores the frequency data of the data into the next level of filtering subcircuit along with the data. Specifically, the comparator C of each level of filtering subcircuit 200 compares and determines whether the current input data data_in is the same as the historical data stored in the data register Reg_data. If they are the same, the output terminal p3 of the comparator C outputs 1; if they are different, the output terminal p3 of the comparator C outputs 0. The output terminal p3 of the comparator C is connected to the second selection terminal u4 of the second data selector MUX2 of the filtering subcircuit 200 to which it belongs. In response to the signal of the second selection terminal u4, if the second selection terminal u4 of the second data selector MUX2 outputs 1, it means that the current input data data_in is the same as the historical data stored in the data register Reg_data, so the frequency data corresponding to the historical data stored in the current frequency register Reg_label should be increased by 1, then the second input terminal u2 of the second data selector MUX2 is selected, and the frequency data after addition by 1 is written from the output terminal u3 to the input terminal b of the frequency register Reg_label of the next-level filtering sub-circuit 200; correspondingly, if the second selection terminal u4 of the second data selector MUX2 outputs 0, it means that the current input data data_in is different from the historical data stored in the data register Reg_data, so the frequency data corresponding to the historical data stored in the current frequency register Reg_label remains unchanged, then the first input terminal u1 of the second data selector MUX2 is selected, and the original frequency data is written from the output terminal u3 to the input terminal b of the frequency register Reg_label of the next-level filtering sub-circuit 200. Whenever the frequency register Reg_label of a certain level of filtering subcircuit 200 receives frequency data input by the frequency register Reg_label of the previous level, it will transfer the historical frequency data originally stored in itself to the frequency register Reg_label of the next level of filtering subcircuit 200 when storing the frequency data. After gradually transmitting the frequency data, the output end eN of the frequency register Reg_label-N of the Nth level filtering subcircuit 200-N outputs the historical frequency data stored in itself as the frequency data label_out through the main frequency data output end OUT2.

[0097] It is to be understood that the above embodiments are merely exemplary embodiments used to illustrate the principles of the present invention, but the present invention is not limited thereto. For those of ordinary skill in the art, various modifications and improvements can be made without departing from the spirit and essence of the present invention, and these modifications and improvements are also considered to be within the scope of protection of the present invention.

Claims

1. A data mutually exclusive filter circuit, having a main input terminal and a main output terminal, characterized in that: It includes a preprocessing subcircuit and an N-level filtering subcircuit, N≥2; wherein, When N=2, the input end of the first-stage filter subcircuit is connected to the preprocessing subcircuit, and the output end is connected to the input end of the second-stage filter subcircuit; the input end of the second-stage filter subcircuit is connected to the output end of the first-stage filter subcircuit, and the output end is connected to the main output end; When N>2, the input end of the first-stage filter subcircuit is connected to the preprocessing subcircuit, and the output end is connected to the input end of the second-stage filter subcircuit; the input end of the N-stage filter subcircuit is connected to the output end of the N-1-stage filter subcircuit, and the output end is connected to the main output end; the input end of the M-stage filter subcircuit is connected to the output end of the M-1-stage filter subcircuit, and the output end is connected to the input end of the M+1-stage filter subcircuit; wherein 1<M<N; Each level of the filtering subcircuit can compare whether the input data currently received by the main input terminal is the same as the historical data stored in itself, and feed back the comparison result to the preprocessing subcircuit; The preprocessing subcircuit outputs corresponding data to the first-stage filtering subcircuit according to the comparison results fed back by the filtering subcircuits at each stage; if the comparison results fed back by the filtering subcircuits at any stage are the same, a preset placeholder is output; if the comparison results fed back by the filtering subcircuits at each stage are different, the input data is output.

2. The data mutually exclusive filtering circuit according to claim 1, characterized in that: The preprocessing subcircuit includes a first data selector and an OR gate; each level of the filtering subcircuit includes a data register and a comparator; The input end of the data register of the first-stage filtering subcircuit is connected to the output end of the first data selector, and the output end is connected to the input end of the data register of the second-stage filtering subcircuit; The input end of the data register of the Nth level filter subcircuit is connected to the input end of the data register of the N-1th level filter subcircuit, and the output end is connected to the main output end; The input end of the data register of the Mth level filter subcircuit is connected to the output end of the data register of the M-1th level filter subcircuit, and the output end is connected to the input end of the data register of the M+1th level filter subcircuit; In each level of the filtering subcircuit, the comparator has a first input terminal, a second input terminal and an output terminal, wherein the first input terminal is connected to the output terminal of the data register, the second input terminal is connected to the main input terminal, and the output terminal is connected to one of the multiple input terminals of the OR gate; wherein the output terminal of the comparator outputs the comparison result; The first data selector has a first input terminal, a second input terminal, a first selection terminal and an output terminal, wherein the first input terminal is connected to the main input terminal, the second input terminal is connected to the placeholder output terminal, and the first selection terminal is connected to the output terminal of the OR gate.

3. The data mutually exclusive filtering circuit according to claim 2, characterized in that: The data register of each level of the filtering subcircuit also includes a clock input terminal connected to a clock signal source; the clock input terminals of each of the data registers are connected to the same clock signal source.

4. The data mutually exclusive filtering circuit according to any one of claims 2 or 3, characterized in that: Each level of the filtering subcircuit further includes: a frequency counting unit, which is connected to the comparator and the data register of the filtering subcircuit and is used to count the frequency of the same data among the data received by the main input end.

5. The data mutually exclusive filtering circuit according to claim 4, characterized in that: The data mutually exclusive filtering circuit further comprises: a main frequency data output terminal; the frequency statistics unit comprises: a frequency register and a second data selector; wherein, In each level of the filtering subcircuit, the second data selector has a first input terminal, a second input terminal, a second selection terminal and an output terminal, the first input terminal and the second input terminal are both connected to the output terminal of the frequency register, and the frequency data input to the second input terminal is equal to the sum of the frequency data input to the first input terminal and a constant 1; the second selection terminal is connected to the output terminal of the comparator; wherein, The output end of the second data selector of the Nth filter subcircuit is connected to the main frequency data output end, and the output ends of the second data selectors of the other filter subcircuits are connected to the input end of the frequency register of the next filter subcircuit; The input end of the frequency register of the first-stage filtering subcircuit is connected to the output end of the OR gate.

6. The data mutually exclusive filtering circuit according to claim 5, characterized in that: The frequency statistics unit further includes: an adder, an input end of which is connected to the output end of the frequency register; and an output end of which is connected to the second input end of the second data selector.

7. The data mutually exclusive filtering circuit according to any one of claims 5-6, characterized in that: The preprocessing subcircuit further includes: a NOT gate; the input end of the NOT gate is connected to the output end of the OR gate; the output end of the NOT gate is connected to the input end of the frequency register of the first-stage filtering subcircuit.

8. The data mutually exclusive filtering circuit according to claim 1, characterized in that: Also includes: A data screening subcircuit is provided, wherein the data screening subcircuit can filter invalid data and pass valid data; the data input to the main input terminal passes through the data screening subcircuit and is then output to the preprocessing subcircuit and each level of the filtering subcircuit.

9. The data mutually exclusive filtering circuit according to claim 8, characterized in that: The data screening subcircuit includes an AND gate having an input terminal, an enable terminal and an output terminal, wherein the input terminal serves as the main input terminal, the enable terminal is connected to the enable signal terminal, and the output terminal is connected to the preprocessing subcircuit and each level of the filtering subcircuit.

10. A data mutually exclusive filtering method, characterized in that: The method applied to the data mutually exclusive filtering circuit described in any one of claims 1 to 9 comprises the following steps: Each level of filtering subcircuit compares the input data currently received by the main input terminal with the historical data stored in itself to see if they are the same, and feeds the comparison result back to the preprocessing subcircuit; The preprocessing subcircuit outputs corresponding data to the first-stage filtering subcircuit according to the comparison results fed back by the filtering subcircuits at each stage; If the comparison results fed back by the filtering subcircuit at any level are the same, a preset placeholder is output; If the comparison results fed back by the filter sub-circuits at each level are different, the input data is output.

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