clock circuit, data operation unit, chip

Abstract

Embodiments of the present application provide a clock circuit, a data operation unit and a chip. The clock circuit comprises a functional unit, a first output unit, a second output unit and a feedback loop. A first input end of the functional unit receives a clock source signal, an output end of the functional unit is connected with the first output unit and the second output unit, and the output end is connected with a second input end of the functional unit to form the feedback loop. The feedback loop is used to generate a feedback signal according to an output signal of the functional unit. The functional unit is used to generate a pulse clock signal according to the clock source signal, and generate the output signal according to the pulse clock signal and the clock source signal. The first output unit is used to generate a first pulse trigger signal according to the output signal. The second output unit is used to generate a second pulse trigger signal according to the output signal. A time difference between the first pulse trigger signal and the second pulse trigger signal is a specified time length, so that a clock signal with a pulse width meeting specific scene requirements can be generated.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor device technology, and in particular to a clock circuit, a data processing unit, and a chip. Background Technology

[0002] Clock circuits have a wide range of applications, such as the clock circuits in computers and electronic watches. The clock circuit used to generate clocks is often also called a clock generator. In existing technology, the clock width (duty cycle) of a clock generator is specified by the clock source. In other words, limited by the pulse width of the clock source signal, the fixed pulse width of the clock source may change after several stages of processing by the clock generator, resulting in it not meeting the requirements of certain specific scenarios. Summary of the Invention

[0003] The purpose of this invention is to provide a clock circuit, a data processing unit, a chip, and an electronic terminal to at least partially solve the above-mentioned problems.

[0004] A first aspect of the present invention provides a clock circuit, the clock circuit including: a functional unit, a first output unit, a second output unit, and a feedback loop;

[0005] The first input terminal of the functional unit receives a clock source signal, and the output terminal is connected to the first output unit and the second output unit. The output terminal is also connected to the second input terminal of the functional unit to form the feedback loop.

[0006] The feedback loop is used to generate a feedback signal based on the output signal of the functional unit;

[0007] The functional unit is used to generate a pulse clock signal based on the clock source signal, and to generate the output signal based on the pulse clock signal and the clock source signal;

[0008] The first output unit is configured to generate a first pulse trigger signal based on the output signal;

[0009] The second output unit is used to generate a second pulse trigger signal based on the output signal, wherein the time difference between the first pulse trigger signal and the second pulse trigger signal is a specified duration.

[0010] Optionally, the clock circuit is applied to a two-stage shift register, the specified duration is greater than or equal to the hold time of the latter shift register in the two-stage shift register, the first clock pulse signal is used to control the former shift register in the two-stage shift register, and the second clock pulse signal is used to control the latter shift register in the two-stage shift register.

[0011] Optionally, the functional unit includes a logic flipping module, which includes several inverters connected in series, wherein the input terminal of the first inverter serves as the first input terminal of the functional unit, and the several inverters are used to sequentially flip the clock source signal to generate a pulse clock signal.

[0012] Optionally, the functional unit further includes: a delay module, which is connected to the logic flip module; the delay module includes a selector and multiple delay sub-units;

[0013] Each of the delay sub-units corresponds to a different delay time, which is used to delay the received pulse clock signal for a corresponding preset duration based on the feedback signal;

[0014] The selector is configured to, based on the selected delay sub-unit, cause the delay sub-unit to delay the pulse clock signal for a preset duration based on the feedback signal to generate a delayed feedback signal.

[0015] Optionally, the functional unit further includes: a NAND gate module, which is connected to the logic flip module. The NAND gate module receives the clock source signal and the pulse clock signal respectively, and performs NAND logic processing on the clock source signal and the pulse clock signal to obtain the output signal.

[0016] Optionally, the logic switching module includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, and a fifth NMOS transistor;

[0017] The gates of the first PMOS transistor and the first NMOS transistor are connected, forming the first input terminal of the functional unit; the gate of the second NMOS transistor forms the second input terminal of the functional unit.

[0018] Optionally, the NAND gate module includes a sixth PMOS transistor, a seventh PMOS transistor, a sixth NMOS transistor, and a seventh NMOS transistor. The gates of the sixth PMOS transistor and the sixth NMOS transistor are both connected to the clock source signal. The gates of the seventh NMOS transistor and the seventh PMOS transistor are both connected to the delay feedback signal. The drain of the sixth PMOS transistor is connected to the source of the sixth NMOS transistor and internally connected to the output terminal. The drain of the seventh NMOS transistor is grounded and connected to the output terminal.

[0019] Optionally, the first output unit includes a cascaded M-stage inverter for performing an odd number of flips and an even number of inversions on the output signal to generate the first pulse trigger signal, where M is an integer greater than or equal to M.

[0020] Optionally, the second output unit includes a cascaded N-stage inverter for performing an odd number of flips and an even number of inversions on the output signal to generate the second pulse trigger signal, where N is an integer greater than or equal to M.

[0021] In a second aspect, a data processing unit is provided, including an interconnected control circuit, a processing circuit, and a clock circuit, wherein the clock circuit is the clock circuit described in any embodiment.

[0022] Thirdly, a chip is provided that includes at least one data processing unit as described in the embodiments of this application.

[0023] Fourthly, an electronic terminal is provided, which includes at least one chip as described in the embodiments of this application.

[0024] According to an embodiment of the present invention, a clock circuit includes a functional unit, a first output unit, a second output unit, and a feedback loop. The first input terminal of the functional unit receives a clock source signal, and its output terminal is connected to both the first and second output units. The output terminal is also connected to the second input terminal of the functional unit to form the feedback loop. The feedback loop generates a feedback signal based on the output signal of the functional unit. The functional unit generates a pulse clock signal based on the clock source signal, and generates the output signal based on the pulse clock signal and the clock source signal. The first output unit generates a first pulse trigger signal based on the output signal. The second output unit generates a second pulse trigger signal based on the output signal. The time difference between the first and second pulse trigger signals is a specified duration, thereby generating a pulse trigger signal with a pulse width that meets the requirements of a specific scenario. Attached Figure Description

[0025] Other features, objects, and advantages of this application will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings:

[0026] Figure 1 This is a schematic diagram of the circuit structure of a clock circuit according to Embodiment 1 of the present invention;

[0027] Figure 2 This is a schematic diagram of a clock circuit provided in Embodiment 2 of the present invention;

[0028] Figure 3 This is a schematic diagram illustrating the application of a two-stage shift register in an embodiment of this application;

[0029] Figure 4 This is another circuit structure diagram of the clock circuit provided in Embodiment 4 of the present invention;

[0030] Figure 5 This is another circuit structure diagram of the clock circuit provided in Embodiment 5 of the present invention;

[0031] Figure 6A This is a schematic diagram of the delay module in an embodiment of this application;

[0032] Figure 6B This is a schematic diagram of the U-shaped delay chain in an embodiment of this application;

[0033] Figure 7 This is a schematic diagram of the data processing unit in an embodiment of the present invention.

[0034] Figure 8 This is a schematic diagram of the chip structure in an embodiment of the present invention. Detailed Implementation

[0035] The present invention will now be described in further detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and not intended to limit it. Furthermore, it should be noted that, for ease of description, only the parts relevant to the invention are shown in the accompanying drawings.

[0036] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. The present invention will now be described in detail with reference to the accompanying drawings and embodiments.

[0037] Example 1

[0038] See Figure 1 , Figure 1 This is a schematic diagram of the circuit structure of a clock circuit according to Embodiment 1 of the present invention. The clock circuit includes: a functional unit 1, a first output unit 2, a second output unit 3, and a feedback loop 4; the functional unit 1 has a first input terminal, a second input terminal, and an output terminal.

[0039] The first input terminal of the functional unit 1 receives a clock source signal, and the output terminals are all connected to the first output unit 2 and the second output unit 3. The output terminals are also connected to the second input terminal of the functional unit 1 to form the feedback loop.

[0040] The feedback loop is used to generate a feedback signal based on the output signal of the functional unit 1;

[0041] The functional unit 1 is used to generate a pulse clock signal based on the clock source signal, so as to generate the output signal based on the pulse clock signal and the clock source signal;

[0042] The first output unit 2 is used to generate a first pulse trigger signal based on the output signal;

[0043] The second output unit 3 is used to generate a second pulse trigger signal based on the output signal, wherein the time difference between the first pulse trigger signal and the second pulse trigger signal is a specified duration.

[0044] In this embodiment, the time difference between the first pulse trigger signal and the second pulse trigger signal can be a pre-specified time length according to actual needs. For example, when the clock circuit is applied to a two-stage shift register, the first clock pulse signal is used to control the first stage shift register in the two-stage shift register, and the second clock pulse signal is used to control the second stage shift register in the two-stage shift register. The specified time length is greater than or equal to the hold time of the second stage shift register in the two-stage shift register.

[0045] Example 2

[0046] Figure 2 This is a schematic diagram of a clock circuit provided in Embodiment 2 of the present invention. Figure 2 As shown, Figure 1 The difference is that the functional unit 1 includes: a logic flip module 10 and a NAND gate module 11.

[0047] The logic flipping module 10 includes several inverters connected in series. The input terminal of the first inverter serves as the first input terminal of the functional unit. The inverters are used to sequentially flip the clock source signal to generate a pulse clock signal. The output terminal of the last inverter serves as the output terminal of the functional unit.

[0048] The NAND gate module 11 is connected to the logic flip module 10. The NAND gate module 11 receives the clock source signal and the pulse clock signal respectively, and performs NAND logic processing on the clock source signal and the pulse clock signal to obtain the output signal of the functional unit.

[0049] Example 3

[0050] Figure 3 This is a schematic diagram illustrating the application of a two-stage shift register in an embodiment of this application. Figure 3 In this context, the first pulse trigger signal is denoted as (CKN2, CKP2), and the second pulse trigger signal is denoted as (CKN1, CKP1).

[0051] like Figure 3 As shown, its working principle is briefly described as follows: For example, after data Dn is passed to the previous stage shift register, the previous stage shift register outputs data Dn when the rising edge of the CLKP1 clock arrives; when the rising edge of the CLKP2 clock arrives, the next stage shift register begins to latch the data Dn output by the previous stage shift register. During the time period from when the next stage shift register starts latching the data to when the data latching is completed, if the previous stage shift register transmits another data to the next stage shift register before the holding time, it may result in data Dn not being stored in the next stage shift register.

[0052] Therefore, the clock circuit provided in this embodiment of the invention can generate a first pulse trigger signal and a second pulse trigger signal. The time difference between the first pulse trigger signal and the second pulse trigger signal is a specified duration. This specified duration is greater than or equal to the hold time of the latter shift register in the two-stage shift register. This ensures that the former shift register can transmit another data to the latter shift register after the hold time, thus satisfying the hold time of the shift register and achieving accurate data storage.

[0053] Example 4

[0054] Figure 4 This is a schematic diagram of another circuit structure of the clock circuit provided in Embodiment 4 of the present invention. Exemplarily, the clock circuit can be applied to... Figure 3 The specified duration of the two-stage shift register shown is greater than or equal to the hold duration of the latter stage shift register in the two-stage shift register.

[0055] For example, such as Figure 4 As shown, the logic switching module 10 includes: a first PMOS transistor P1, a third PMOS transistor P3, a fourth PMOS transistor P4, and a first NMOS transistor N1, a third NMOS transistor N3, and a fourth NMOS transistor N4, which can be used to perform logic switching on the clock source signal. Specifically, the first PMOS transistor P1 and the first NMOS transistor N1 form a first-stage inverter, the third PMOS transistor P3 and the third NMOS transistor N3 form a second-stage inverter, and the fourth PMOS transistor P4 and the fourth NMOS transistor N4 form a third-stage inverter. That is, the logic switching module 10 includes three stages of inverters. The output signal of the first-stage inverter is denoted as S1, the output signal of the second-stage inverter is denoted as S2, and the output signal of the third-stage inverter is denoted as S3. S3 serves as the pulse clock signal output by the logic switching module.

[0056] The gates of the first PMOS transistor P1 and the first NMOS transistor N1 are both connected to the clock source signal. The source of the first PMOS transistor P1 is connected to the power supply, and the drain of the first PMOS transistor P1 is connected to the drain of the first NMOS transistor N1. The gates of the third PMOS transistor P3 and the third NMOS transistor N3 are connected to S1. The drains of the third PMOS transistor P3 and the third NMOS transistor N3 are connected to each other, and the source of the third NMOS transistor N3 is grounded. The gates of the fourth PMOS transistor P4 and the fourth NMOS transistor N4 are connected to S2. The drains of the fourth PMOS transistor P4 and the fourth NMOS transistor N4 are connected to each other and connected to S3. The source of the fourth PMOS transistor P4 is connected to the power supply, and the source of the fourth NMOS transistor N4 is grounded.

[0057] It should be noted that in other embodiments, the number of inverters included in the logic flip module 10 is determined according to the application scenario and is not limited to three stages.

[0058] The NAND gate module includes a sixth PMOS transistor P6, a seventh PMOS transistor P7, a sixth NMOS transistor N6, and a seventh NMOS transistor N7. The gates of the sixth PMOS transistor and the sixth NMOS transistor are both connected to the clock source signal. The gates of the seventh NMOS transistor and the seventh PMOS transistor are both connected to the pulse clock signal. The drain of the sixth PMOS transistor is connected to the source of the sixth NMOS transistor and to the output terminal of the functional unit. The source of the seventh NMOS transistor is grounded, and the drain of the seventh PMOS transistor is connected to the output terminal. The sources of the sixth PMOS transistor P6 and the seventh PMOS transistor P7 are connected to the power supply. The source of the seventh NMOS transistor is grounded. The drain of the seventh PMOS transistor N7 is connected to the output terminal of functional unit 1.

[0059] Furthermore, after the gates of the sixth PMOS transistor P6 and the sixth NMOS transistor N6 are connected, they are also connected to the gates of the first PMOS transistor P1 and the first NMOS transistor N1, together serving as the first input terminal of the functional unit 1.

[0060] See Figure 4 Feedback loop 4 includes an inverter, a pull-down module, and a pull-up module. The input of the inverter is connected to the output of the functional unit. The input of the pull-down module is connected to the output of the inverter. The output of the pull-down module is connected to the input of the pull-up module. The output of the pull-up module is connected to the second-stage inverter in the logic flip module 10, specifically to the source of the third PMOS transistor P3.

[0061] Specifically, the inverter included in the feedback loop 4 includes an eighth PMOS transistor P8 and an eighth NMOS transistor N8. The gates of both the eighth PMOS transistor P8 and the eighth NMOS transistor N8 are connected to the output terminal of the functional unit 1. The source of the eighth PMOS transistor P8 is connected to the power supply, and the drain of the eighth PMOS transistor P8 is connected to the drain of the eighth NMOS transistor N8. The source of the eighth NMOS transistor N8 is grounded. The output signal of the inverter is denoted as FB, which is the feedback signal.

[0062] Specifically, the pull-down module includes a second PMOS transistor N2, whose drain is connected to the drain of the first NMOS transistor N1, whose source is grounded, and whose gate is connected to the output of the inverter (composed of P8 and N8) to receive the feedback signal FB.

[0063] Specifically, the pull-up module includes: a second PMOS transistor P2, a fifth PMOS transistor P5, and a fifth NMOS transistor N5. The gates of the fifth PMOS transistor P5 and the fifth NMOS transistor N5 are connected to the output of the inverter (composed of P8 and N8) to receive the feedback signal FB. The source of the fifth PMOS transistor P5 is connected to the power supply, the source of the fifth NMOS transistor N5 is grounded, the drain of the fifth PMOS transistor P5 is connected to the drain of the fifth NMOS transistor N5, and is also connected to the gate of the second PMOS transistor P2. The source of the second PMOS transistor P2 is connected to the power supply, and the drain of the second PMOS transistor P2 is connected to the source of the third PMOS transistor P3.

[0064] Therefore, for Figure 4 The clock pulse signal generation process of the clock circuit shown is explained as follows: Clock source signal CLK=0, clock source signal CLK as rising edge (0↑1), CLK=1, and clock source signal CLK as falling edge (0↓1) are explained respectively:

[0065] (1) When the clock source signal CLK=0, the circuit is in a stable state:

[0066] When the clock source signal CLK=0, the first PMOS transistor P1 is turned on and N1 is turned off, so S1 is 1. The third NMOS transistor N3 is turned on and P3 is turned off, so S2 is 0. The fourth PMOS transistor P4 is turned on and N4 is turned off, so S3 is 1.

[0067] In addition, when the clock source signal CLK=0, the sixth PMOS transistor P6 is turned on and the sixth NMOS transistor N6 is turned off. S3=1, which turns off the seventh PMOS transistor P7 and turns on the seventh NMOS transistor N7. OUT=1, and the eighth NMOS transistor N8 is turned on, which makes FB=0. The sixth PMOS transistor P6, the sixth NMOS transistor N6, the seventh PMOS transistor P7, and the seventh NMOS transistor N7 are equivalent to forming a NAND gate.

[0068] Furthermore, since FB=0, the second NMOS transistor N2 is turned off, the fifth NMOS transistor N5 is turned off, and the second PMOS transistor P2 is turned off. This means that CLK is essentially processed through three stages of inversion (P1 and N1 form the first stage of inversion to generate the signal at S1, which is 1 at this time; P3 and N3 form the second stage of inversion to generate the signal at S2, which is 0 at this time; and P4 and N4 form the third stage of inversion to generate the signal at S3, which is 1 at this time), thus generating OUT, which is 1 at this time.

[0069] Since OUT=1, after processing by the first output unit 2, CKN2=1 and CKP2=0; after processing by the second output unit 3, CKN1=1 and CKP1=0.

[0070] (2) When the clock source signal CLK is a rising edge signal (0↑1):

[0071] When the clock source signal CLK is a rising edge signal (0↑1), the first PMOS transistor P1 is turned off, while N1 is turned on. However, since FB remains 0, N2, N5, and P2 are turned off. Therefore, S1 remains 1, S2 remains 0, and S3 remains 1. At the same time, since the clock source signal CLK is a rising edge signal (0↑1), N6 is turned on, while P6 is turned off, making OUT a falling edge signal. At this time, after processing by the first output unit 2, CKN2 is a falling edge signal, and CKP2 is a rising edge signal; after processing by the second output unit 3, CKN1 is a falling edge signal, and CKP1 is a rising edge signal.

[0072] (3) When the clock source signal CLK=1:

[0073] When CLK is 1, and S3 remains 1, after being processed by the NAND gate composed of the sixth PMOS transistor P6, the sixth NMOS transistor, the seventh PMOS transistor P7, and the seventh NMOS transistor N7, OUT is flipped to 0.

[0074] Since OUT=0, FB becomes 1, which makes N2 conduct, N5 conduct, P2 conduct, S1 becomes 0, S2 becomes 1, and S3 becomes 0.

[0075] Since OUT=0, after processing by the first output unit 2, CKN2 becomes 0 and CKP2 becomes 1; after processing by the second output unit 3, CKN1 becomes 0 and CKP1 becomes 1.

[0076] S3 becomes 0, and after being processed by the NAND gate, OUT changes from 0 to 1, thus achieving the inversion of OUT and generating the trailing edge of OUT.

[0077] Figure 5 This is another circuit structure diagram of the clock circuit provided in Embodiment 5 of the present invention. Figure 5 As shown, the feedback loop 4 includes an inverter, a pull-down module, a pull-up module, and a delay module.

[0078] The delay module 11 is connected to the logic inversion module 10. The delay module 11 includes a selector and multiple delay sub-units. Each delay sub-unit corresponds to a different delay time and is used to delay the inverted signal of the functional unit's output signal (OUT) for a corresponding preset duration. The selector is used to select a delay sub-unit so that the delay sub-unit delays the inverted signal of the functional unit's output signal (OUT) for a preset duration to generate a feedback signal. The inverted signal of the functional unit's output signal (OUT) is denoted as S4.

[0079] Specifically, the delay module is positioned after the inverter (such as those composed of P8 and N8) and before the pull-down module. For example, the input of the delay module is connected to the drains of P8 and N8, and the output of the delay module is connected to the gate of N2.

[0080] Figure 5 Taking four delay sub-units (referred to as delay 1, delay 2, delay 3, and delay 4 in sequence) as an example, it can be understood that in practical applications, those skilled in the art can set any appropriate number of delay sub-units according to their needs.

[0081] Therefore, for Figure 5 The clock pulse signal generation process of the clock circuit shown is explained below: Clock source signal CLK=0, clock source signal CLK as a rising edge signal (0↑1), and CLK=1 are explained respectively:

[0082] (1) When the clock source signal CLK=0, the circuit is in a stable state:

[0083] When the clock source signal CLK=0, the first PMOS transistor P1 is turned on and N1 is turned off, so S1 is 1. The third NMOS transistor N3 is turned on and P3 is turned off, so S2 is 0. The fourth PMOS transistor P4 is turned on and N4 is turned off, so S3 is 1.

[0084] In addition, when the clock source signal CLK=0, the sixth PMOS transistor P6 is turned on and the sixth NMOS transistor N6 is turned off. S3=1, which turns off the seventh PMOS transistor P7 and turns on the seventh NMOS transistor N7. OUT=1, and the eighth NMOS transistor N8 is turned on, which makes FB=0. The sixth PMOS transistor P6, the sixth NMOS transistor N6, the seventh PMOS transistor P7, and the seventh NMOS transistor N7 are equivalent to forming a NAND gate.

[0085] Furthermore, in the stable state of the circuit, the delay module does not delay the inverted signal OUT (denoted as S4). As mentioned above, this will cause FB=0, ensuring that the second NMOS transistor N2 is off, the fifth NMOS transistor N5 is off, and the second PMOS transistor P2 is off. Thus, CLK is equivalent to directly undergoing three stages of inversion (P1 and N1 form the first stage of inversion to generate the signal at S1, which is 1 at this time; P3 and N3 form the second stage of inversion to generate the signal at S2, which is 0 at this time; P4 and N4 form the third stage of inversion to generate the signal at S3, which is 1 at this time), thereby generating OUT, which is 1 at this time.

[0086] Since OUT=1, after processing by the first output unit 2, CKN2=1 and CKP2=0; after processing by the second output unit 3, CKN1=1 and CKP1=0.

[0087] (2) When the clock source signal CLK is a rising edge signal (0↑1), the delay module performs delay processing on the signal OUT after it has been inverted (the inversion is performed by the inverter composed of P8 and N8):

[0088] When the clock source signal CLK is a rising edge signal (0↑1), the sixth PMOS transistor P6 is turned off, and the sixth NMOS transistor N6 is turned on. However, since the delay time has not yet been reached, FB remains 0, N2 is turned off, N5 is turned off, and P2 is also turned off, thus causing S1 to be in a floating state and held at 1, thereby causing S2 to remain 0 and S3 to remain 1. Furthermore, since the clock source signal CLK is a rising edge signal (0↑1), OUT↓ (i.e., the falling edge that generates OUT) is inverted, and its signal is 1.

[0089] Since OUT flips (OUT↓), after processing by the first output unit 2, CKN2↓ (i.e., a falling edge is generated) and CKP2↑ (i.e., a rising edge is generated); after processing by the second output unit 3, CKN1↓ (i.e., a falling edge is generated) and CKP1↑ (i.e., a rising edge is generated).

[0090] When OUT flips (OUT↓), P8 turns on, and the inverted signal of OUT goes up.

[0091] (3) When the clock source signal CLK=1:

[0092] Before the delay time is reached, when CLK is 1, FB remains 0, N2 is turned off, N5 is turned off, and P2 is also turned off, causing S1 to be in a floating state and kept at 1. This causes S2 to remain 0 and S3 to remain 1. After processing by the NAND gate composed of the sixth PMOS transistor P6, the sixth NMOS transistor, the seventh PMOS transistor P7, and the seventh NMOS transistor N7, OUT decreases until OUT=0. The inverted signal of OUT becomes 1. At this time, after processing by the first output unit 2, CKN2=0 and CKP2=1; after processing by the second output unit 3, CKN1=0 and CKP1=1.

[0093] When the delay time is reached, FB changes from 0 to 1, N2 turns on, N5 turns on, P2 also turns on, S1 turns on, S2 turns on, S3 turns on. Since CLK=1 at this time, OUT turns on. After processing by the first output unit 2, CKN2 turns on and CKP2 turns on; after processing by the second output unit 3, CKN1 turns on and CKP1 turns on.

[0094] See circuit Figure 4 , Figure 5 The first output unit 2 may include a first inverter and a second inverter. The two clock pulse signals output by the first inverter and the second inverter are out of phase. The second output unit 3 includes four inverters connected in series. The second output unit 3 may also output CKN1 and CKP1 with out of phase. The signal at OUT (same as the signal at FB) output by the functional unit can be delayed for a first duration by the inverter in the first output unit 2, and then the first clock pulse signal CKP2 can be output. Similarly, the signal at OUT output by the functional unit can be delayed for a second duration by the inverter in the second output unit 3, and the second clock pulse signal CKP1 can be output. In this embodiment, the time difference between the first duration and the second duration is greater than or equal to... Figure 3 The duration of the hold time for the second stage shift register in the two-stage shift register shown.

[0095] It is understood that the more inverters a circuit unit contains, the longer the delay; in this embodiment or Figure 4 In this example, the extended duration (second duration) of the second output unit 3 is greater than the extended duration (first duration) of the first output unit 2.

[0096] In the application scenario of this embodiment, it can be applied to Figure 3 The two-stage shift register shown can now have the time difference between the second duration and the first duration set to be greater than or equal to... Figure 3 The duration of the hold time of the second shift register in the two-stage shift register is shown. Therefore, CKP2 can be input into the second shift register and CKP1 into the first shift register to ensure that the next data is input only after the current data in the second shift register has been latched, thus guaranteeing accurate storage of the current data. It should be understood that the difference in delay between the second output unit 3 and the first output unit 2 can also be greater than the duration of the hold time of the second shift register in the two-stage shift register.

[0097] In the clock circuit of this embodiment, exemplarily, after receiving the rising edge signal of the clock source signal, functional unit 1 flips it through a branch and outputs it. Then, after being flipped by the first output unit and / or the second output unit, it becomes the rising edge of the newly generated clock pulse signal. The falling edge signal of the flipped signal is then input into functional unit 1 through feedback loop 4 to start the delay module 11 to perform a delay of a preset duration (wherein, the preset duration is less than the duration corresponding to the pulse width of the clock source signal). Then, based on the feedback signal, functional unit 1 uses the NAND gate module 11 to perform NAND operations on the clock source signal and the pulse clock signal, thereby realizing the trailing edge clipping operation of the clock source signal to obtain the falling edge of the newly generated clock pulse signal, and thus obtaining a new clock pulse signal. That is to say, the pulse width of the newly generated clock pulse signal can be preset by the delay subunit, thereby obtaining a clock pulse signal that is arbitrarily smaller than the pulse width of the clock source signal. Further, when the delay duration of the first output unit 2 is less than the delay duration of the second output unit 3, and the time difference between the two is greater than or equal to the delay duration of the second output unit 3, the clock pulse signal can be obtained. Figure 3 The hold time of the second-stage shift register in the two-stage shift register setup ensures that the next data is input only after the current data in the second-stage shift register has been latched, thus ensuring accurate storage of the current data. In other words, it can generate a clock signal with a pulse width that meets the requirements of specific scenarios.

[0098] The clock circuit provided in this embodiment of the invention can serve as a customized standard unit, such as a clock signal generator to provide clock pulse signals for scenarios requiring pulse signals. For example, it can function as a clock generator for pulse latches, a shift register misalignment clock generator, or a multi-directional non-overlapping clock generator. Furthermore, it can serve as a clock generation unit in a CPU / CPU for generating clock pulse signals in ultra-large-scale computing scenarios; it can also serve as a clock generation unit in an AI (Artificial Intelligence) chip for generating clock pulse signals in high-density computing scenarios; and it can also serve as a system-level clock generation unit in a System on Chip (SOC) / Field Programmable Gate Array (FPGA) for generating clock pulse signals in low-power computing scenarios.

[0099] Figure 6A This is a schematic diagram of the delay module in an embodiment of this application; please refer to... Figure 6A Optionally, in one specific embodiment, the delay module 40 includes several U-shaped delay chains in a chain. Each U-shaped delay chain includes a selector and a delay selection switch (also known as a delay device). The selector is used to control the delay duration of the current U-shaped delay chain or the delay duration of the next U-shaped delay chain, so as to turn on the several U-shaped delay chains one by one to form delay chains with different delay times, so as to delay S4 with different delay times.

[0100] Figure 6B This is a schematic diagram of the U-shaped delay chain in an embodiment of this application; please refer to... Figure 6B, optionally, in a specific embodiment, the structure of the delay chain may include: n + 1 delay selection switches (Delay Mux, also known as a delay element), where one delay selection switch participates in forming one stage of a U-shaped delay chain, n is an integer greater than or equal to 1, and these n + 1 delay selection switches form n + 1 stages of U-shaped delay chains. Additionally, one stage of the U-shaped delay chain further includes a selector for generating a gating signal, and each delay selection switch operates or pauses under the control of the corresponding gating signal. Specifically, the gating signals corresponding to the n + 1 delay selection switches are EN(0), EN(1)...... EN(n - 1), EN(n) in sequence. When EN(i) = 1, 0 ≤ i ≤ y, the corresponding delay selection switch is effective and can play a delaying role, and at the same time, the delay selection switches corresponding to EN(0) - EN(i - 1) are also effective; otherwise, when EN = 0, the corresponding delay selection switch does not work and does not play a delaying role. When EN = 1, it means that this stage of the U-shaped delay chain is connected in series, and In will go to Out_Ext. In fact, Out_Ext is connected to the In of the next stage of the U-shaped delay chain. In this way, the delay unit is equivalent to passing through two delay units, that is, the delay is doubled.

[0101] EN(0), EN(1)...... EN(n - 1), EN(n) are specifically generated by the selector. The selector specifically performs a logical operation on the hot code (also known as one hot) generated by the decoder to generate EN(0), EN(1)...... EN(n - 1), EN(n). The specific principle is: when EN[i] = 1, the control circuit ensures that EN[x] = 1 (0 <= x < i). At the same time, since EN[n] is a one-hot code structure and EN[y] = 0 (i < y < n), therefore, assuming EN[i] = 1 is selected, for the selected stage and the stages of EN[x] (x < i) before the selection, Out will be connected in series by In_Ext, thus forming a return path of the U-shaped loop chain. And EN[i + 1] = 0, In - DelayCell - AND2 - Out forms a folded return path. At the same time, Out_Ext = 0. For the stage of EN[y] = 0 (y > i + 1), because In = 0, all output nodes become 0. Therefore, In_Ext of the EN[i + 1] stage is 0, which makes Out = the output of AND2, thus forming a U-shaped loop.

[0102] Assume that the delay of each delay selection switch is 50 ps / stage, that is, the corresponding delay time is 50 ps.

[0103] For example, taking EN[0]=1, EN[1]=1, EN[2]=0 as an example, since EN[2]=0, the third-level U-shaped delay chain is the last level of this delay, and the delay time is 150ps; and so on, when EN(0:n-1)=1, EN(n)=0, the nth-level U-shaped delay chain is the last level of this delay, and the delay time is (n+1)*50ps.

[0104] exist Figure 6B In the signal, the In terminal is used to receive S4, and the Out terminal is used to output the delayed signal.

[0105] Please see Figure 6B Optionally, in one specific embodiment, the structure of the delay selection switch (Delay Mux) includes: a delay cell, two AND gates (AND1, AND2), an OR gate, and a NOT gate. The connection relationships of these logic circuit components are detailed in [reference needed]. Figure 6B As shown, it forms a U-shaped structure. The delay unit specifically includes a buffer and a multiplexer. The buffer buffers S4 and outputs the signal to the inputs of two AND gates via the multiplexer. This involves multiplexing the low or high level input from S4 to the inputs of the two AND gates, allowing for delay processing via multiple or one delay selection switches, thus delaying the high level in S4 as a delay signal.

[0106] Combination Figure 6B The principle behind the delay time of 150ps when EN[0]=1, EN[1]=1, and EN[2]=0 is explained in detail below:

[0107] When EN[2]=0, EN[1]=1, and EN[0]=1, S4 will be transmitted from the U-shaped delay chain enabled by EN[0], delayed by 50ps, to the U-shaped delay chain unit enabled by EN[1], then from the U-shaped delay chain unit enabled by EN[1], to the EN[2] unit, where it passes through the AND gate (AND2) in the U-shaped delay chain enabled by EN[2], then through the OR gate, and then back in the opposite direction. It passes through the Out of the U-shaped delay chain enabled by EN[2], through the Out of the U-shaped delay chain enabled by EN[1], through the Out of the U-shaped delay chain enabled by EN[0], and finally to the output.

[0108] See above Figure 6BIn the above process, EN[0]=1, the output of the NOT gate in its corresponding U-type delay chain is 0, then the output of AND2 is 0, and the output of AND1 is 1, that is, S4 is input to the In end of the U-type delay chain corresponding to EN[1]. However, at this time, when the output of AND2 is 0 and in_Ext is 0, then the output of the OR gate is 0; EN[1]=1, the output of the NOT gate in its corresponding U-type delay chain is 0, then the output of AND2 is 0, and the output of AND1 is 1, but at this time, in_Ext is also 0, then the output of the OR gate is 0; EN[2]=0, the output of the NOT gate in its corresponding U-type delay chain is 1, then the output of AND2 is 1, and the output of AND1 is 0, that is, the delayed S4 will not be input to the U-type delay chain corresponding to EN[3]. However, at this time, the OR gate is equivalent to a buffer, thus making Out=AND2. The output of the U-type delay chain corresponding to EN[2] is 1, and is input to the output Out of the U-type delay chain corresponding to EN[1] and EN[0] in sequence. Referring to the above process, in each U-shaped delay chain, since there is a delay unit, S4 will be delayed by 50ps. Therefore, the U-shaped delay chains corresponding to EN[0], EN[1], and EN[2] will be delayed a total of 3 times, for a total of 3*50ps=150ps.

[0109] This invention also provides a data processing unit. Figure 7 This is a schematic diagram of the data processing unit in an embodiment of the present invention. Figure 7 As shown, the data processing unit 700 includes a control circuit 701, a processing circuit 702, and multiple clock circuits 703. The control circuit 701 controls the clock circuits 703 to generate clock pulse signals with a preset pulse width, and the processing circuits 702 perform processing on the data according to the clock pulse signals. The clock circuits 703 are the clock circuits in any of the above embodiments.

[0110] This invention also provides a chip. Figure 8 This is a schematic diagram of the chip structure in an embodiment of the present invention. Figure 8 As shown, chip 800 includes a control unit 801 and one or more data processing units 700. The control unit 801 inputs data to the data processing units 700 and processes the data output by the data processing units 700.

[0111] This application provides an electronic terminal that includes at least one chip as described in this application.

[0112] The terms "first," "second," "first," or "second" used in the various embodiments of this disclosure may modify various components regardless of their order and / or importance, but these terms do not limit the corresponding components. The above terms are configured only for the purpose of distinguishing an element from other elements. For example, "first user equipment" and "second user equipment" refer to different user equipments, although both are user equipment. For example, without departing from the scope of this disclosure, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element.

[0113] When a component (e.g., a first component) is referred to as being "(operably or communicatively) coupled" or "(operably or communicatively) coupled to" or "connected to" another component (e.g., a second component), it should be understood that the first component is directly connected to the second component or that the first component is indirectly connected to the second component via yet another component (e.g., a third component). Conversely, it can be understood that when a component (e.g., a first component) is referred to as being "directly connected" or "directly coupled" to another component (the second component), no component (e.g., a third component) is inserted between the two.

[0114] The above description is merely a preferred embodiment of this application and an explanation of the technical principles employed. Those skilled in the art should understand that the scope of the invention involved in this application is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the above-described inventive concept. For example, technical solutions formed by substituting the above features with (but not limited to) technical features with similar functions disclosed in this application.

Claims

1. A clock circuit, characterized in that, The clock circuit includes: a functional unit, a first output unit, a second output unit, and a feedback loop; The first input terminal of the functional unit receives a clock source signal, and the output terminal is connected to the first output unit and the second output unit. The output terminal is also connected to the second input terminal of the functional unit to form the feedback loop. The feedback loop is used to generate a feedback signal based on the output signal of the functional unit; The functional unit is used to generate a pulse clock signal based on the clock source signal, and to generate the output signal based on the pulse clock signal and the clock source signal; The first output unit is configured to generate a first pulse trigger signal based on the output signal; The second output unit is used to generate a second pulse trigger signal based on the output signal, wherein the time difference between the first pulse trigger signal and the second pulse trigger signal is a specified duration; The functional unit includes a logic flipping module, which includes several inverters connected in series. The input terminal of the first inverter serves as the first input terminal of the functional unit. The several inverters are used to flip the clock source signal sequentially to generate a pulse clock signal. The NAND gate module is connected to the logic flip module. The NAND gate module receives the clock source signal and the pulse clock signal respectively, and performs NAND logic processing on the clock source signal and the pulse clock signal to obtain the output signal. The logic switching module includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, and a fifth NMOS transistor. The gates of the first PMOS transistor and the first NMOS transistor are connected, forming the first input terminal of the functional unit; the gate of the second NMOS transistor is the second input terminal of the functional unit, its drain is connected to the drain of the first NMOS transistor, and its source is grounded; the source of the fifth PMOS transistor is connected to the power supply, its gate is connected to the gate of the fifth NMOS transistor, its source is grounded, its drain is connected to the drain of the fifth NMOS transistor and to the gate of the second PMOS transistor, its source is connected to the power supply, and its drain is connected to the source of the third PMOS transistor. The drain of the second NMOS transistor is connected to the drain of the first NMOS transistor, and the source of the second NMOS transistor is grounded; the gates of the fifth PMOS transistor and the fifth NMOS transistor are connected to the output of the inverter to receive feedback signals.

2. The clock circuit according to claim 1, characterized in that, The clock circuit is applied to a two-stage shift register, the specified duration is greater than or equal to the hold time of the latter shift register in the two-stage shift register, the first pulse trigger signal is used to control the former shift register in the two-stage shift register, and the second pulse trigger signal is used to control the latter shift register in the two-stage shift register.

3. The clock circuit according to claim 1, characterized in that, The NAND gate module includes a sixth PMOS transistor, a seventh PMOS transistor, a sixth NMOS transistor, and a seventh NMOS transistor. The gates of the sixth PMOS transistor and the sixth NMOS transistor are both connected to the clock source signal. The gates of the seventh NMOS transistor and the seventh PMOS transistor are both connected to the pulse clock signal. The drain of the sixth PMOS transistor is connected to the source of the sixth NMOS transistor and is also connected to the output terminal. The drain of the seventh NMOS transistor is grounded and connected to the output terminal.

4. The clock circuit according to claim 1, characterized in that, The first output unit includes cascaded M-stage inverters for performing odd-numbered flips and even-numbered inversions on the output signal to generate the first pulse trigger signal, where M is an integer.

5. The clock circuit according to claim 4, characterized in that, The second output unit includes N cascaded inverters for performing an odd number of flips and an even number of inversions on the output signal to generate the second pulse trigger signal, where N is an integer and N is greater than M.

6. A data processing unit, comprising an interconnected control circuit, a processing circuit, and a clock circuit, wherein the clock circuit is the clock circuit according to any one of claims 1-5.

7. A chip, characterized in that, It includes at least one data processing unit as described in claim 6.

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