A circuit for a single line synchronization pulse signal and a method for implementing the same

Abstract

The application discloses a kind of single line synchronous pulse signal circuits, including at least two synchronization modules, the power input end of synchronization module is connected with the output end of AC-DC module, and synchronization module includes chip U1, the 3 feet of chip U1 are control signal input end, the 4 feet and 5 feet of chip U1 are control signal output end, and the collector of at least two synchronization modules triode Q1 is connected by wire;The application also discloses a kind of single line synchronous pulse signal circuit implementation method.The application is ensured that the pulse signal received by the 6 feet of chip U1 is same with the pulse signal emitted by the 2 feet of chip U1 by the cooperation of triode Q1 and triode Q2, so that corresponding operation can be accurately executed;The application can realize pulse signal transmission between multiple synchronization modules by only one wire, with the characteristics of low cost, no master-slave relationship and supporting multipoint data communication.

Description

Technical Field

[0001] This invention belongs to the field of signal transmission and control technology, specifically relating to a circuit for a single-wire synchronous pulse signal and its implementation method. Background Technology

[0002] Currently, in some building lighting and industrial lighting applications, due to the complex indoor environment, it is not possible to use wireless modules for communication. However, it is still necessary to synchronize the status of all lights in a certain area. When the status of one light changes, the status of the other lights must be synchronized.

[0003] Due to the development of smart lights, commonly used switches can only meet the needs of turning lights on and off, but cannot meet the needs of dimming and color adjustment. To achieve the aforementioned control, RS485 and RS232 protocols are generally used in the market. However, both of these methods have the following shortcomings:

[0004] First, the RS232 protocol is a point-to-point communication protocol. When more than two devices need to be controlled, wiring and management will be very troublesome.

[0005] Secondly, the RS485 protocol requires a dedicated chip to convert differential signals for judgment, which is costly. Summary of the Invention

[0006] The purpose of this invention is to provide a circuit for a single-wire synchronous pulse signal to solve the problems mentioned in the background section. The circuit for a single-wire synchronous pulse signal provided by this invention features single-wire synchronous pulse signal, low cost, no master-slave relationship, and support for multi-point data communication.

[0007] Another objective of this invention is to provide a method for implementing a single-wire synchronous pulse signal circuit.

[0008] To achieve the above objectives, the present invention provides the following technical solution: a circuit for a single-wire synchronous pulse signal, comprising at least two synchronization modules. The power input terminal of the synchronization module is connected to the output terminal of an AC-DC module. The synchronization module includes a chip U1, pin 3 of chip U1 is a control signal input terminal, pins 4 and 5 of chip U1 are control signal output terminals, pin 2 of chip U1 is connected to one end of resistor R1, the other end of resistor R1 is connected to one end of resistor R2 and the base of transistor Q1, and the emitter of transistor Q1 is connected to one end of resistor R3. The other ends of resistors R3 and R2 are connected to the output of the AC-DC module. The collector of transistor Q1 is connected to one end of resistors R4 and R5 respectively. The other end of resistor R5 is connected to the base of transistor Q2. The emitter of transistor Q2 and the other end of resistor R4 are both connected to the GND terminal. The collector of transistor Q2 is connected to one end of resistor R6 and pin 6 of chip U1 respectively. The other end of resistor R6 is connected to the output of the AC-DC module. The collectors of transistors Q1 of at least two synchronization modules are connected by wires.

[0009] To further improve the stability of the voltage on the collector of transistor Q1, the collector of transistor Q1 is also connected to capacitor C1, and the other end of capacitor C1 is connected to the GND terminal.

[0010] To further improve the power supply stability of chip U1, a capacitor C2 is connected between pin 1 and pin 8 of chip U1.

[0011] To improve the stability of the pulse signal received by pin 6 of chip U1, the synchronization module further includes transistor Q3. The collector of transistor Q3 is connected to the output terminal of the AC-DC module, the base of transistor Q3 is connected to resistor R5, the emitter of transistor Q3 is connected to one end of resistors R7 and R8 respectively, the other end of resistor R7 is connected to the base of transistor Q2, and the other end of resistor R8 is connected to the GND terminal.

[0012] In order to make the pulse signal output by pin 2 of chip U1 consistent with the pulse signal received by pin 6 of chip U1, transistor Q1 is further made to be PNP type, while transistors Q2 and Q3 are both NPN type.

[0013] To improve the load-carrying capacity of pin 2 of chip U1, resistor R3 is a 0805 surface mount resistor, and the resistance of resistor R4 is at least 50 times greater than that of resistor R3.

[0014] Furthermore, in this invention, the method for implementing a single-wire synchronous pulse signal circuit includes the following steps:

[0015] (i) Connect the power input terminals of at least two synchronization modules to the output terminal of the AC-DC module;

[0016] (ii) Define the voltage signal at the collector of transistor Q1 in the synchronization module as the communication signal, and connect the collectors of transistor Q1 in at least two synchronization modules through wires.

[0017] (III) Pin 3 of chip U1 is the control signal input terminal, and pins 4 and 5 of chip U1 are the control signal output terminals;

[0018] (iv) By default, pin 6 of chip U1 is in the receiving state, and pin 2 of chip U1 continuously outputs a high level.

[0019] (v) When pin 3 of chip U1 of one of the synchronization modules receives a control signal, pins 4 and 5 of chip U1 of the synchronization module send control signals to execute the corresponding operation, and at the same time pin 2 of chip U1 of the synchronization module outputs the set pulse signal.

[0020] (vi) When the 6th pin of the chip U1 of other synchronization modules receives the set pulse signal, it sends control signals through the 4th and 5th pins of its own chip U1 to execute the corresponding operation.

[0021] To prevent the transmitted pulse signal from affecting itself and causing repeated operations, further in step (v), when pin 3 of chip U1 receives a control signal, the receiving function of pin 6 of chip U1 is turned off.

[0022] Compared with the prior art, the beneficial effects of the present invention are:

[0023] 1. This invention ensures that the pulse signal received by pin 6 of chip U1 is the same as the pulse signal emitted by pin 2 of chip U1 through the cooperation of transistor Q1 and transistor Q2, so that the corresponding operation can be executed accurately.

[0024] 2. This invention can realize pulse signal transmission between multiple synchronization modules using only one wire, and has the characteristics of low cost, no master-slave relationship, and support for multi-point data communication;

[0025] 3. When the chip U1 receives a control signal at pin 3, the present invention disables the receiving function of pin 6 of the chip U1, which can effectively prevent the transmitted pulse signal from affecting itself and causing repeated operation. Attached Figure Description

[0026] Figure 1 This is a circuit diagram of the synchronization module of the present invention;

[0027] Figure 2 This is a system block diagram of the present invention;

[0028] Figure 3 This is a circuit diagram of the synchronization module in Embodiment 2 of the present invention;

[0029] In the diagram: 1. AC-DC module; 2. Synchronization module. Detailed Implementation

[0030] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0031] Example 1

[0032] Please see Figure 1-2 The present invention provides the following technical solution: a circuit for a single-wire synchronous pulse signal, comprising at least two synchronization modules 2, wherein the power input terminal of the synchronization module 2 is connected to the output terminal of the AC-DC module 1, the synchronization module 2 includes a chip U1, pin 3 of the chip U1 is the control signal input terminal, pins 4 and 5 of the chip U1 are the control signal output terminals, pin 2 of the chip U1 is connected to one end of a resistor R1, the other end of the resistor R1 is connected to one end of a resistor R2 and the base of a transistor Q1, the emitter of the transistor Q1 is connected to one end of a resistor R3, and the other end of resistor R3 and resistor R2 are connected to the resistor R2. All transistors are connected to the output of AC-DC module 1. The collector of transistor Q1 is connected to one end of resistors R4 and R5 respectively. The other end of resistor R5 is connected to the base of transistor Q2. The emitter of transistor Q2 and the other end of resistor R4 are both connected to the GND terminal. The collector of transistor Q2 is connected to one end of resistor R6 and pin 6 of chip U1 respectively. The other end of resistor R6 is connected to the output of AC-DC module 1. The collectors of transistors Q1 in at least two synchronization modules 2 are connected by wires. Transistor Q1 is PNP type and transistor Q2 is NPN type.

[0033] Specifically, when pin 2 of chip U1 outputs a high level, transistor Q1 is in the off state, and the voltage on the wire is high; conversely, when pin 2 of chip U1 outputs a low level, transistor Q1 is in the on state, and the voltage on the wire is low; when the voltage on the wire is high, transistor Q2 is in the on state, and pin 6 of chip U1 is low; conversely, when the voltage on the wire is low, transistor Q2 is in the off state, and pin 6 of chip U1 is high.

[0034] By adopting the above technical solution, the present invention ensures that the pulse signal received by pin 6 of chip U1 is the same as the pulse signal emitted by pin 2 of chip U1 through the cooperation of transistor Q1 and transistor Q2, so that the corresponding operation can be executed accurately. The present invention can realize the pulse signal transmission between multiple synchronization modules 2 with only one wire, and has the characteristics of low cost, no master-slave relationship and support for multi-point data communication.

[0035] Specifically, the collector of transistor Q1 is also connected to capacitor C1, and the other end of capacitor C1 is connected to GND.

[0036] By adopting the above technical solution and filtering through capacitor C1, the voltage on the collector of transistor Q1 becomes more stable.

[0037] Specifically, a capacitor C2 is connected between pin 1 and pin 8 of chip U1.

[0038] By adopting the above technical solution and filtering through capacitor C2, the power supply of chip U1 is ensured to be more stable.

[0039] Example 2

[0040] Please see Figure 3 The difference between this embodiment and embodiment 1 is that, specifically, the synchronization module 2 also includes a transistor Q3, wherein the collector of transistor Q3 is connected to the output terminal of AC-DC module 1, the base of transistor Q3 is connected to resistor R5, the emitter of transistor Q3 is connected to one end of resistor R7 and resistor R8 respectively, the other end of resistor R7 is connected to the base of transistor Q2, and the other end of resistor R8 is connected to the GND terminal. Transistor Q3 is an NPN type.

[0041] By adopting the above technical solution, the pulse signal on the collector of transistor Q1 is amplified by two stages of transistors Q3 and Q2, and the pulse signal received by pin 6 of chip U1 will be more stable.

[0042] Example 3

[0043] The difference between this embodiment and embodiment 1 is that, specifically, resistor R3 is a 0805 type surface mount resistor, and the resistance value of resistor R4 is at least 50 times greater than the resistance value of resistor R3.

[0044] By adopting the above technical solution, the load-carrying capacity of pin 2 of chip U1 is enhanced, enabling more synchronization modules to be connected to the communication signal line.

[0045] Example 4

[0046] Furthermore, the implementation method of the single-wire synchronous pulse signal circuit of the present invention includes the following steps:

[0047] (i) Connect the power input terminals of the three synchronization modules to the output terminals of the AC-DC module. The three synchronization modules are synchronization module A, synchronization module B and synchronization module C. The chips U1 on synchronization module A, synchronization module B and synchronization module C are chip U1A, chip U1B and chip U1C respectively. The collectors of transistor Q1 on synchronization module A, synchronization module B and synchronization module C are connected by wires.

[0048] (ii) By default, pin 6 of chips U1A, U1B and U1C are in the receiving state, and pin 2 of chips U1A, U1B and U1C continuously output a high level.

[0049] (III) When pin 3 of chip U1A of synchronization module A receives a control signal, pin 6 of chip U1A turns off the receiving function, pins 4 and 5 of chip U1A send control signals to execute the corresponding operation, and at the same time, pin 2 of chip U1A outputs the corresponding number of pulse signals with a frequency of 10KHZ and a duty cycle of 50%.

[0050] (iv) Chip U1B of synchronization module B and chip U1C of synchronization module C receive the same number of pulse signals with a frequency of 10KHZ and a duty cycle of 50%. Then, pins 4 and 5 of chip U1B and chip U1C send control signals to execute the corresponding operations.

[0051] In this invention, the chip U1 is the PL51T020 model sold by Suzhou Juyuan Microelectronics Co., Ltd.; the AC-DC module is the LHE10-20D0512-02 model sold by Guangzhou Mornsun Technology Co., Ltd.

[0052] In summary, this invention ensures that the pulse signal received by pin 6 of chip U1 is the same as the pulse signal emitted by pin 2 of chip U1 through the cooperation of transistor Q1 and transistor Q2, thereby enabling accurate execution of the corresponding operation. This invention can realize pulse signal transmission between multiple synchronization modules 2 using only one wire, and has the characteristics of low cost, no master-slave relationship, and support for multi-point data communication. When pin 3 of chip U1 receives a control signal, this invention disables the receiving function of pin 6 of chip U1, which can effectively prevent the transmitted pulse signal from affecting itself and causing repeated execution of the operation.

[0053] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A circuit for single wire synchronization pulse signals, characterized by: The power input end of the at least two synchronous modules is connected with the output end of the AC-DC module, the synchronous module comprises a chip U1, the 3-pin of the chip U1 is a control signal input end, the 4-pin and the 5-pin of the chip U1 are control signal output ends, the 2-pin of the chip U1 is connected with one end of a resistor R1, the other end of the resistor R1 is connected with one end of a resistor R2 and the base of a transistor Q1 respectively, the emitter of the transistor Q1 is connected with one end of a resistor R3, the other ends of the resistor R3 and the resistor R2 are connected with the output end of the AC-DC module, the collector of the transistor Q1 is connected with one end of a resistor R4 and one end of a resistor R5 respectively, the other end of the resistor R5 is connected with the base of a transistor Q2, the emitter of the transistor Q2 and the other end of the resistor R4 are connected with a GND end respectively, the collector of the transistor Q2 is connected with one end of a resistor R6 and the 6-pin of the chip U1 respectively, the other end of the resistor R6 is connected with the output end of the AC-DC module, the collectors of the transistors Q1 of the at least two synchronous modules are connected through wires; the cooperation of the transistor Q1 and the transistor Q2 ensures that the pulse signal received by the 6-pin of the chip U1 is the same as the pulse signal emitted by the 2-pin of the chip U1, so that the corresponding operation can be accurately performed; the synchronous module further comprises a transistor Q3, wherein the collector of the transistor Q3 is connected with the output end of the AC-DC module, the base of the transistor Q3 is connected with the resistor R5, the emitter of the transistor Q3 is connected with one end of a resistor R7 and one end of a resistor R8 respectively, the other end of the resistor R7 is connected with the base of the transistor Q2, the other end of the resistor R8 is connected with the GND end; The implementation method of the single-wire synchronous pulse signal circuit comprises the following steps: (1) connecting the power input end of the at least two synchronous modules with the output end of the AC-DC module; (2) defining the voltage signal of the collector of the transistor Q1 of the synchronous module as a communication signal, and connecting the collectors of the transistors Q1 of the at least two synchronous modules through wires; (3) the 3-pin of the chip U1 is a control signal input end, and the 4-pin and the 5-pin of the chip U1 are control signal output ends; (4) defining that the 6-pin of the chip U1 is in a receiving state in a default state, and the 2-pin of the chip U1 continuously outputs a high level; (5) when the 3-pin of the chip U1 of one of the synchronous modules receives a control signal, the 4-pin and the 5-pin of the chip U1 of the synchronous module send a control signal to perform a corresponding operation, and the 2-pin of the chip U1 of the synchronous module outputs a set pulse signal; (6) the 6-pin of the chip U1 of the other synchronous modules receives the set pulse signal, and sends a control signal to perform a corresponding operation through the 4-pin and the 5-pin of the chip U1 itself; In step (5), when the 3-pin of the chip U1 receives a control signal, the receiving function of the 6-pin of the chip U1 is closed.

2. A circuit for a single line synchro pulse signal as claimed in claim 1, characterized in that: The collector of the transistor Q1 is further connected with a capacitor C1, and the other end of the capacitor C1 is connected with the GND end.

3. A circuit for a single wire sync pulse signal as defined in claim 1, characterized in that: A capacitor C2 is connected between the 1-pin and the 8-pin of the chip U1.

4. A circuit for a single line synchro pulse signal as defined in claim 1, characterized in that: The transistor Q1 is PNP type, and the transistors Q2 and Q3 are NPN type.

5. A circuit for a single line synchro pulse signal as defined in claim 1, characterized by: The resistance R3 is a 0805 type chip resistor, and the resistance R4 has a resistance value at least 50 times greater than that of the resistance R3.

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