Frequency lock error detection circuit and method and display driving circuit

Abstract

This invention relates to a frequency lock-up error detection circuit, comprising a comparison unit and a control unit. The comparison unit compares a common-mode voltage signal with a first reference voltage signal and a second reference voltage signal to generate a comparison result, wherein the common-mode voltage signal corresponds to a differential signal pair output by a timing controller. The control unit determines, based on the comparison result, whether to reset the clock data recovery circuit coupled to the timing controller. The frequency lock-up error detection circuit of this invention can detect whether the frequency locked by the clock data recovery circuit is incorrect, and reset the clock data recovery circuit when a frequency lock-up error is detected, avoiding erroneous recovery of the clock signal and data signal due to frequency lock-up errors.

Description

Technical Field

[0001] This invention relates to frequency lock-in error detection, and more particularly to a frequency lock-in error detection circuit, a frequency lock-in error detection method, and a display driver circuit with frequency lock-in error detection function. Background Technology

[0002] The data driver has clock and data recovery circuitry, which performs frequency locking on the data signal output by the timing controller to generate a recovery clock signal and a recovery data signal. However, when the system is powered on, the common-mode voltage signal may be affected by noise, causing errors in subsequent frequency locking and generating incorrect recovery clock and data signals, which in turn leads to problems with image display. Summary of the Invention

[0003] The purpose of this invention is to provide a frequency lock error detection function, which can detect whether the frequency locked by the clock data recovery circuit is incorrect when the display device system is powered on, and reset the clock data recovery circuit when a frequency lock error is detected, so as to avoid incorrect recovery of clock signal and recovery data signal caused by frequency lock error.

[0004] One aspect of this invention relates to a frequency lock-up error detection circuit, comprising a comparison unit and a control unit. The comparison unit compares a common-mode voltage signal with a first reference voltage signal and a second reference voltage signal to generate a first comparison result indicating whether the potential of the common-mode voltage signal is within the range between the potentials of the first and second reference voltage signals, wherein the potential of the first reference voltage signal is higher than the potential of the second reference voltage signal, and wherein the common-mode voltage signal corresponds to a differential signal pair output by a timing controller. The control unit, based on the first comparison result, determines whether to reset the clock and data recovery circuit coupled to the timing controller.

[0005] According to one or more embodiments of the present invention, the comparison unit includes a first comparator, a second comparator, and a logic gate. The first input terminal and the second input terminal of the first comparator are respectively used to input a first reference voltage signal and a common-mode voltage signal. The first input terminal and the second input terminal of the second comparator are respectively used to input the common-mode voltage signal and the second reference voltage signal. The first input terminal and the second input terminal of the logic gate are respectively coupled to the output terminals of the first comparator and the second comparator, and the output terminal of the logic gate is used to output a first comparison result.

[0006] According to one or more embodiments of the present invention, the frequency lock error detection circuit further includes a first phase shift circuit coupled to the second input terminal of the first comparator and the first input terminal of the second comparator.

[0007] According to one or more embodiments of the present invention, the frequency lock error detection circuit further includes a second phase shift circuit and a third phase shift circuit, which are respectively coupled to the output terminals of the first comparator and the second comparator.

[0008] According to one or more embodiments of the present invention, the frequency lock error detection circuit further includes a digital comparator for comparing the recovered data signal generated by the clock data recovery circuit with a comparison data string to generate a second comparison result. The control unit is used to determine whether to reset the clock data recovery circuit based on the first comparison result and the second comparison result.

[0009] Another aspect of the present invention relates to a frequency lock-in error detection method, comprising: comparing a common-mode voltage signal with a first reference voltage signal and a second reference voltage signal to generate a first comparison result indicating whether the potential of the common-mode voltage signal is within a range between the potentials of the first reference voltage signal and the second reference voltage signal, wherein the potential of the first reference voltage signal is higher than the potential of the second reference voltage signal, wherein the common-mode voltage signal corresponds to a differential signal pair output by a timing controller; and determining, based on the first comparison result, whether to reset a clock data recovery circuit coupled to the timing controller.

[0010] According to one or more embodiments of the present invention, the frequency lock error detection method further includes: comparing the recovered data signal generated by the clock data recovery circuit with the comparison data string to generate a second comparison result; and determining whether to reset the clock data recovery circuit based on the first comparison result and the second comparison result.

[0011] According to one or more embodiments of the present invention, the differential signal pair is generated based on clock training data of the corresponding comparison data string.

[0012] Another aspect of the invention relates to a display driving circuit comprising a timing controller, a clock data recovery circuit, and a frequency lock-up error detection circuit. The timing controller generates differential signal pairs. The clock data recovery circuit is coupled to the timing controller and generates a recovered data signal and a recovered clock signal based on the differential signal pairs. The frequency lock-up error detection circuit includes a comparison unit and a control unit, wherein the comparison unit compares a common-mode voltage signal of a corresponding differential signal pair with a first reference voltage signal and a second reference voltage signal to generate a first comparison result indicating whether the potential of the common-mode voltage signal is within the range between the potentials of the first and second reference voltage signals, wherein the potential of the first reference voltage signal is higher than the potential of the second reference voltage signal, and the control unit determines whether to reset the clock data recovery circuit based on the first comparison result. Attached Figure Description

[0013] To gain a more complete understanding of the embodiments and their advantages, the following description is made with reference to the accompanying drawings, wherein:

[0014] Figure 1 This is a schematic diagram of a display device according to an embodiment of the present invention;

[0015] Figure 2 This is a partial circuit block diagram of the display driving circuit according to an embodiment of the present invention;

[0016] Figure 3 This is a flowchart of the frequency locking error detection method according to an embodiment of the present invention;

[0017] Figure 4 for Figure 2 A schematic diagram of the components of the comparison unit;

[0018] Figure 5 This is a partial circuit block diagram of the display driving circuit according to an embodiment of the present invention;

[0019] Figure 6 A flowchart of a frequency locking error detection method according to an embodiment of the present invention; and

[0020] Figure 7A and Figure 7B These are examples of comparison data strings from embodiments of the present invention.

[0021] Explanation of reference numerals in the attached figures

[0022] 100: Display device

[0023] 110: Display panel

[0024] 120: Data Drive

[0025] 122: Clock Data Recovery Circuit

[0026] 130: Scan drive

[0027] 140: Timing Controller

[0028] 200, 500: Frequency lock-in error detection circuit

[0029] 210, 510: Comparison Units

[0030] 212A, 212B: Comparators

[0031] 214: Logic Gate

[0032] 220, 530: Control Unit

[0033] 300, 600: Frequency Locking Error Detection Method

[0034] 520: Digital comparator COMP: Compares data strings CR1, CR2: Comparison result

[0035] CTRL: Control signal

[0036] D: Data cable

[0037] DATA: Recovered data signals DS(1)~DS(M): Data drive signals

[0038] LOCK: Restore clock signal

[0039] P: Pixel unit

[0040] R1, R2: Resistors

[0041] S: Scan line

[0042] S302, S304, S306, S308, S310, S602, S604, S606, S608, S610, S612, S614: Steps

[0043] SS(1)~SS(N): Scan drive signals

[0044] T: Switching element

[0045] V CM Common-mode voltage signal V REF1 V REF2 Reference voltage signal V DATA + V DATA - Differential signal pair Detailed Implementation

[0046] The embodiments of the present invention will now be discussed in detail. However, it will be understood that the embodiments provide many applicable concepts that can be implemented in a wide variety of specific contexts. The discussed and disclosed embodiments are for illustrative purposes only and are not intended to limit the scope of the invention.

[0047] The language used herein is for the purpose of describing particular embodiments only and is not intended to limit the claims. Unless otherwise limited, the singular forms of "a" or "the" may also be used to denote the plural forms.

[0048] The term "coupled" and its derivatives may be used in the following description and claims. In certain embodiments, "coupled" may refer to two or more elements that are in direct physical or electrical contact with each other, or that are not in direct contact with each other. "Coupled" may also refer to two or more elements that operate or move with each other.

[0049] For the sake of simplicity and clarity, element symbols and / or letters may be repeated in various embodiments herein, but this does not imply a causal relationship between the various embodiments and / or configurations discussed.

[0050] Please refer to Figure 1 This is a schematic diagram of a display device 100 according to an embodiment of the present invention. The display device 100 includes a display panel 110, a data driver 120, a scan driver 130, and a timing controller 140. The display panel 110 may be a thin-film transistor liquid crystal display (TFT-LCD), but is not limited thereto. The display panel 110 includes a plurality of pixel units P, a plurality of data lines D, and a plurality of scan lines S. In the display panel 110, all pixel units P form a matrix of M columns and N rows. Each pixel unit P includes a switching element T, which is driven by a data line D and a scan line S to be turned on within a specific time interval, so that the pixel unit P can display the corresponding grayscale. The data driver 120 is used to generate data driving signals DS(1) to DS(M), which are used to drive each data line D to transmit grayscale data to each column of pixel units P. The scan driver 130 is used to generate scan driving signals SS(1) to SS(N) to drive each scan line S to control the switching state of the switching element T in each row of pixel units P. Within a specific time interval, the switching element T is in an "on" state, causing the pixel unit P to display the corresponding grayscale. Utilizing the principle of visual persistence, the human eye can see the complete display image. The timing controller 140 controls the scan driver 130 to sequentially drive each scan line S of the display panel 110, and while each scan line S is sequentially driven, it controls the data driver 120 to send corresponding image data to each data line D of the display panel 110. In some embodiments, the data driver 120, scan driver 130, and timing controller 140 can be integrated into a single display driving circuit and fabricated on a single chip. Furthermore, in some embodiments, the chip integrating the functions of the data driver 120, scan driver 130, and timing controller 140 can also provide touch sensing functionality for the display panel 110 with an in-cell touch sensing structure or a touch panel on top of it.

[0051] Figure 2 This is a partial circuit block diagram of the display driving circuit according to an embodiment of the present invention. Figure 2 In this circuit, the clock and data recovery circuit 122 can be a part of the data driver 120. It is coupled to the timing controller 140 and receives the differential signal output by the timing controller 140 to V. DATA + V DATA -This is used to generate recovery data signals and recovery clock signals. The frequency lock error detection circuit 200 includes a comparison unit 210 and a control unit 220, wherein the comparison unit 210 is used to compare the corresponding differential signal pair V. DATA + V DATA - The common mode voltage signal and the reference voltage signal V REF1 V REF2 The comparison is performed to generate a comparison result CR1, and the control unit 220 uses the comparison result CR1 to decide whether to reset the clock data recovery circuit 122.

[0052] Figure 3 This is a flowchart of the frequency lock-up error detection method 300 according to an embodiment of the present invention. First, step S302 is performed to power on the system, enabling the clock data recovery circuit to recover the clock and data. Then, step S304 is performed to provide clock training data, causing the differential signal output by the timing controller 140 to be applied to V. DATA + V DATA - It has a format that conforms to the clock training data. Then, proceed to step S306 to determine the common-mode voltage signal V. CM Whether the potential is within the predetermined range, that is, whether it is within the reference voltage signal V. REF1 V REF2 Within the range. Common-mode voltage signal V CM The potential can be a differential signal to V DATA + V DATA - The midpoint of the potential, i.e., V CM =(V DATA + +V DATA - ) / 2. If the common-mode voltage signal V CM The potential at the reference voltage signal V REF1 V REF2 Within the range, i.e., V REF2 <V CM <V REF1 If the frequency is locked, proceed to step S308 to confirm whether the frequency is locked; otherwise, proceed to step S310 to stop clock and data recovery, reset the clock and data recovery circuit, and then return to step S304.

[0053] In step S308, if it is determined that the frequency is locked, then proceed to step S312 to complete the clock data recovery and use the recovered data signal and the recovered clock signal for image display; otherwise, if it is determined that the frequency is not locked, then return to step S304.

[0054] Figure 4 for Figure 2 A schematic diagram of the components of the comparison unit 210. (See attached diagram.) Figure 4 As shown, the common-mode voltage signal V CM The differential signal to V is converted by resistors R1 and R2. DATA + V DATA - Thus, comparators 212A and 212B respectively use the reference voltage signal V REF1 V REF2 For common-mode voltage signal V CM The comparison is performed, where the reference voltage signal V is used. REF1 The potential is higher than the reference voltage signal V. REF2 The potential of the comparator 212A. The positive and negative input terminals are configured to input common-mode voltage signals V. CM and reference voltage signal V REF1 The positive and negative input terminals of comparator 212B are respectively configured to input reference voltage signals V. REF2 and common-mode voltage signal V CM The two inputs and output of logic gate 214 are respectively coupled to the outputs of comparators 212A and 212B and the output comparison result CR1. In other embodiments, comparators 212A and 212B can be replaced with reference voltage signals V. REF1 V REF2 For common-mode voltage signal V CM Compare them.

[0055] The comparison result CR1 output by logic gate 214 is determined by the signals output from the output terminals of comparators 212A and 212B. If the common-mode voltage signal V... CM The potential is higher than the reference voltage signal V. REF1 V REF2 If the voltage level is high, comparators 212A and 212B will output low logic level signals and high logic level signals respectively, and the voltage level of the comparison result CR1 output by logic gate 214 will be high logic level, representing the common-mode voltage signal V. CM The potential is not within the predetermined range. If the common-mode voltage signal V CM The potential is lower than the reference voltage signal V. REF1 The potential is higher than the reference voltage signal V. REF2 If the voltage level is low, comparators 212A and 212B will both output low logic voltage signals, and the voltage level of the comparison result CR1 output by logic gate 214 will be low, representing the common-mode voltage signal V. CM The potential is within the predetermined range. If the common-mode voltage signal V CM The potential is higher than the reference voltage signal V. REF1 VREF2 If the voltage level is high, comparators 212A and 212B will output high logic voltage signals and low logic voltage signals respectively, and the voltage level of the comparison result CR1 output by logic gate 214 will be high logic voltage, representing the common-mode voltage signal V. CM The potential is outside the predetermined range. Logic gate 214 can be an OR gate or a logic unit composed of multiple other types of logic gates. When the comparison result CR1 is a high logic potential, the control signal CTRL output by the control unit 220 is used to stop clock and data recovery and reset the clock data recovery circuit 122.

[0056] The negative input terminal of comparator 212A and the positive input terminal of comparator 212B may include a phase shift circuit (not shown) for removing the common-mode voltage signal V. CM The AC component. Furthermore, the outputs of comparators 212A and 212B may each include a phase-shifting circuit (not shown in the figure). The phase-shifting circuit referred to herein can be an RC filter circuit or other suitable circuit.

[0057] Figure 5 This is a partial circuit block diagram of the display driving circuit according to an embodiment of the present invention. Figure 5 In the frequency lock-up error detection circuit 500, a comparison unit 510, a digital comparator 520, and a control unit 530 are included. The comparison unit 510 is the same as or similar to the comparison unit 210 in the frequency lock-up error detection circuit 200, and will not be described further here. The digital comparator 520 is used to compare the recovered data signal DATA with the comparison data string COMP to generate a comparison result CR2, wherein the comparison data string COMP is applied to generate the differential signal pair V. DATA + V DATA - The clock training data. In some embodiments, if the recovered data signal DATA conforms to the type of the comparison data string COMP, the output comparison result CR2 is a low logic level; otherwise, if the recovered data signal DATA does not conform to the type of the comparison data string COMP, the output comparison result CR2 is a high logic level. When at least one of the comparison results CR1 and CR2 is a high logic level, the control signal CTRL output by the control unit 530 is used to stop clock and data recovery and reset the clock data recovery circuit 122.

[0058] Figure 6This is a flowchart of a frequency lock-up error detection method 600 according to an embodiment of the present invention. Steps S602, S604, S606, and S610 in the frequency lock-up error detection method 600 are the same as or similar to steps S302, S304, S306, and S310 in the frequency lock-up error detection method 300, and will not be described in detail here. In step S608, if it is determined that the frequency is locked, then proceed to step S612 to compare the recovered data signal with the comparison data string; otherwise, if it is determined that the frequency is not locked, return to step S604.

[0059] In step S612, if it is determined that the recovered data signal conforms to the type of the comparison data string, then proceed to step S614 to complete the clock data recovery, and use the recovered data signal and the recovered clock signal for image display; otherwise, if it is determined that the frequency is not locked, then proceed to step S610 to stop the clock and data recovery, reset the clock data recovery circuit, and then return to step S604.

[0060] Figure 7A This is an example of the comparison data string COMP in an embodiment of the present invention. Figure 7A As shown, in this example, the comparison data string COMP has 9 bits (COMP[1] to COMP[9]), and has 1 to 9 types (numbered 1 to 9 respectively). In any type, the bit value 0 and 1 represent low and high potentials respectively. The recovered data signal DATA must conform to one of the 1 to 9 types to determine that the frequency has been correctly locked; otherwise, it is determined that the frequency lock is incorrect, and the clock data recovery circuit is reset. In some embodiments, the recovered data signal DATA is continuously compared with the comparison data string COMP in units of 9 bits. If all conform to the same type of 1 to 9, the frequency is determined to be correctly locked; otherwise, it is determined that the frequency lock is incorrect, and the clock data recovery circuit is reset. The above determination method is similar to determining whether the recovered data signal DATA conforms to the pattern of 5 consecutive high-potential bits followed by 4 consecutive low-potential bits in sequence. The number of consecutive comparisons can be adjusted according to the circuit design and product specifications.

[0061] Figure 7B This is an example of the comparison data string COMP in an embodiment of the present invention. Figure 7BAs shown, in this example, the comparison data string COMP also has 9 bits (COMP[1] to COMP[9]), and has the 1st to 9th types (numbered 1 to 9 respectively). In any type, the bit value 0 and 1 represent low potential and high potential respectively, and the bit value X represents high / low potential (i.e., not limited to low potential or high potential). The recovered data signal DATA must conform to one of the 1st to 9th types to determine that the frequency has been correctly locked. Otherwise, it is determined that the frequency lock is incorrect, and the clock data recovery circuit is reset. In some embodiments, the recovered data signal DATA is continuously compared with the comparison data string COMP in units of 9 bits. If they all conform to the same type of the 1st to 9th types, the frequency is determined to be correctly locked; otherwise, it is determined that the frequency lock is incorrect, and the clock data recovery circuit is reset. The above determination method is similar to determining whether the recovered data signal DATA conforms to the pattern of 4 consecutive high potential bits followed by 3 consecutive low potential bits followed by 1 bit interval in a sequential cycle. Similarly, the number of consecutive comparisons can be adjusted according to the circuit design and product specifications.

[0062] According to the above embodiments of the present invention, when the display device system is powered on, it can detect whether the frequency locked by the clock data recovery circuit is incorrect, and when a frequency locking error is detected, the clock data recovery circuit can be reset to avoid incorrect recovery of clock signals and recovery of data signals caused by frequency locking errors.

[0063] Although the present invention has been disclosed above by way of embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the scope defined in the appended claims.

Claims

1. A frequency lock-in error detection circuit, characterized in that, The frequency lock error detection circuit includes a comparison unit and a control unit; wherein... The comparison unit is used to compare a common-mode voltage signal with a first reference voltage signal and a second reference voltage signal to generate a first comparison result indicating whether the potential of the common-mode voltage signal is within the range between the potentials of the first reference voltage signal and the second reference voltage signal, wherein the potential of the first reference voltage signal is higher than the potential of the second reference voltage signal, and the common-mode voltage signal corresponds to a differential signal pair output by a timing controller; and The control unit is used to determine whether to reset the clock data recovery circuit coupled to the timing controller based on the first comparison result.

2. The frequency lock-in error detection circuit according to claim 1, characterized in that, The comparison unit includes: The first comparator has its first input terminal and its second input terminal used to input the first reference voltage signal and the common-mode voltage signal, respectively. A second comparator, wherein its first input terminal and second input terminal are respectively used to input the common-mode voltage signal and the second reference voltage signal; and The logic gate has its first input terminal and second input terminal coupled to the output terminals of the first comparator and the second comparator, respectively, and its output terminal is used to output the first comparison result.

3. The frequency lock-in error detection circuit according to claim 2, characterized in that, The frequency lock error detection circuit also includes: The first phase shift circuit is coupled to the second input terminal of the first comparator and the first input terminal of the second comparator.

4. The frequency lock-in error detection circuit according to claim 3, characterized in that, The frequency lock error detection circuit also includes: The second phase shift circuit is coupled to the output of the first comparator; and The third phase shift circuit is coupled to the output of the second comparator.

5. The frequency lock-in error detection circuit according to claim 1, characterized in that, The frequency lock error detection circuit also includes: A digital comparator is used to compare the recovered data signal generated by the clock data recovery circuit with the comparison data string to produce a second comparison result; The control unit is used to determine whether to reset the clock data recovery circuit based on the first comparison result and the second comparison result.

6. A method for detecting frequency locking errors, characterized in that, The frequency lock error detection method includes: A common-mode voltage signal is compared with a first reference voltage signal and a second reference voltage signal to generate a first comparison result indicating whether the potential of the common-mode voltage signal is within the range between the potentials of the first reference voltage signal and the second reference voltage signal, wherein the potential of the first reference voltage signal is higher than the potential of the second reference voltage signal, and the common-mode voltage signal corresponds to a differential signal pair output by a timing controller; and Based on the first comparison result, a decision is made as to whether to reset the clock data recovery circuit coupled to the timing controller.

7. The frequency locking error detection method according to claim 6, characterized in that, The frequency lock error detection method further includes: The recovered data signal generated by the clock data recovery circuit is compared with the comparison data string to produce a second comparison result; and Based on the first comparison result and the second comparison result, a decision is made on whether to reset the clock data recovery circuit.

8. The frequency locking error detection method according to claim 7, characterized in that, The differential signal pair is generated based on clock training data corresponding to the comparison data string.

9. A display driving circuit, characterized in that, The display driving circuit includes a timing controller, a clock data recovery circuit, and a frequency lock error detection circuit; wherein: The timing controller is used to generate differential signal pairs; The clock data recovery circuit is coupled to the timing controller, and is used to generate a recovered data signal and a recovered clock signal based on the differential signal; and The frequency lock error detection circuit includes: A comparison unit is configured to compare a common-mode voltage signal corresponding to the differential signal pair with a first reference voltage signal and a second reference voltage signal to generate a first comparison result indicating whether the potential of the common-mode voltage signal is within the range between the potentials of the first reference voltage signal and the second reference voltage signal, wherein the potential of the first reference voltage signal is higher than the potential of the second reference voltage signal; and The control unit is used to determine whether to reset the clock data recovery circuit based on the first comparison result.

10. The display driving circuit according to claim 9, characterized in that, The frequency lock error detection circuit also includes: A digital comparator is used to compare the recovered data signal with the comparison data string to produce a second comparison result; The control unit is used to determine whether to reset the clock data recovery circuit based on the first comparison result and the second comparison result.

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