Self-adaptive frequency modulation and voltage regulation chip control circuit and method

Abstract

The invention relates to the technical field of integrated circuits, and provides a self-adaptive frequency modulation and voltage regulation chip control circuit and method, the circuit comprises a time sequence monitoring module which comprises a critical path replication sub-module and a daisy chain delay sub-module which are connected, and the critical path replication sub-module is used for simulating an actual critical data path in a chip; the daisy chain delay sub-module is used for applying a configurable delay amount on a time sequence to the output data signal; the time sequence performance after different time points is simulated; the first trigger is used for transmitting data signals; the sampling trigger module is used for sampling the data signal output by the time sequence monitoring module; the comparison logic module is used for generating a multi-bit time sequence margin indication code according to a comparison result; the time sequence margin indication code is used for adaptively adjusting the working frequency or the working voltage of the chip. According to the invention, through accurate monitoring and self-adaptive adjustment of a chip time sequence, all design margins can be utilized, and the energy utilization efficiency is improved, so that extreme low power consumption is realized.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular to chip control circuits and methods for adaptive frequency and voltage modulation. Background Technology

[0002] In the field of chip design, PPA (Performance, Power, and Area) are three key considerations. As chip technology continues to advance, performance improvements are gradually reaching a bottleneck, making power consumption increasingly important. Low-power design has become a crucial requirement across all stages of chip design, aiming to reduce chip energy consumption, improve energy efficiency, and extend device battery life.

[0003] Traditional Dynamic Voltage and Frequency Scaling (DVFS) technology is a frequency and voltage regulation method based on a fixed voltage-frequency correspondence, employing an open-loop design. While easy to implement, this design suffers from significant inefficiency. For example, for processors like General-Purpose Computing on Graphics Processing Units (GPGPUs), the operating environment is provided by the host computer, and the GPGPU cannot predict the upcoming operating environment. Therefore, DVFS cannot precisely adjust voltage and frequency based on the chip's real-time operating state, failing to achieve ultra-low power consumption.

[0004] Furthermore, in this open-loop design, in order to ensure that the chip can operate normally under various possible working conditions, designers need to reserve a certain design margin. This prevents the chip from fully utilizing the circuit's maximum performance, resulting in energy waste. Summary of the Invention

[0005] This application provides a chip control circuit and method for adaptive frequency and voltage regulation. It adopts AVFS (Adaptive Voltage and Frequency Scaling) closed-loop power control technology, which can monitor the timing status of the chip in real time and adaptively adjust the chip's operating frequency and operating voltage according to the generated timing margin indicator code, thereby improving energy utilization efficiency.

[0006] This application provides an adaptive frequency and voltage modulation chip control circuit, comprising: a timing monitoring module, including a critical path replication submodule and a daisy-chain delay submodule connected together; the critical path replication submodule is used to simulate the actual critical data path in the chip; the daisy-chain delay submodule includes multiple delay units connected in sequence, and is used to apply a timing delay to the output data signal; the delay amount can be configured to simulate the timing performance after different time points; a first flip-flop, the output of which is connected to the input of the timing monitoring module, is used to transmit a data signal to the timing monitoring module under the drive of a clock signal; a sampling flip-flop module, the input of which is connected to the output of the timing monitoring module, is used to sample the data signal delayed by the timing monitoring module under the drive of a clock signal to obtain multiple sampled outputs; a comparison logic module, the input of which is connected to the output of the first flip-flop and multiple outputs of the sampling flip-flop module respectively, is used to generate a multi-bit timing margin indicator code based on the comparison result; the timing margin indicator code can characterize the delay state of the timing monitoring module and is used to adaptively adjust the chip's operating frequency or operating voltage.

[0007] According to the adaptive frequency and voltage modulation chip control circuit provided in this application, the delay unit is an inverter.

[0008] According to the adaptive frequency and voltage modulation chip control circuit provided in this application, the sampling trigger module includes multiple sampling triggers, and a fixed delay unit is set between the signal input paths of adjacent sampling triggers, so that there is a preset time difference in the time when the data signal arrives at the input terminal of each sampling trigger, so as to perform time-division sampling on the data signal after being delayed by the timing monitoring module.

[0009] According to the adaptive frequency and voltage modulation chip control circuit provided in this application, the comparison logic module includes multiple XOR units. Each XOR unit is used to compare the output data of the first flip-flop with the output data of a corresponding sampling flip-flop in the sampling flip-flop module to generate one bit of the timing margin indicator code.

[0010] According to the adaptive frequency and voltage modulation chip control circuit provided in this application, the fixed delay unit includes a first fixed delay unit and a second fixed delay unit; the input terminal of the first fixed delay unit is connected to the output terminal of the timing monitoring module; the output terminal of the first fixed delay unit is connected to the input terminal of the second fixed delay unit; multiple XOR units include a first XOR unit, a second XOR unit, and a third XOR unit; the first XOR unit, the second XOR unit, and the third XOR unit are respectively connected to the output terminal of a first flip-flop; multiple sampling flip-flops include a first sampling flip-flop, a second sampling flip-flop, and a third sampling flip-flop; the first sampling flip-flop is respectively connected to the output terminal of the timing monitoring module, the clock signal, and the first XOR unit; the second sampling flip-flop is respectively connected to the output terminal of the first fixed delay unit, the clock signal, and the second XOR unit; the third sampling flip-flop is respectively connected to the output terminal of the second fixed delay unit, the clock signal, and the third XOR unit.

[0011] According to the adaptive frequency and voltage regulation chip control circuit provided in this application, when the timing margin indicator code is 000 or 001, it indicates that the current timing margin is sufficient, and instructs the chip control module to increase the operating frequency or decrease the operating voltage; when the timing margin indicator code is 011 or 111, it indicates that the current timing margin is in a critical state, and instructs the chip control module to maintain the current operating frequency and operating voltage.

[0012] This application also provides an adaptive frequency and voltage modulation chip control method. Using the above-mentioned adaptive frequency and voltage modulation chip control circuit, the adaptive frequency and voltage modulation chip control method includes: gradually adjusting the delay of the timing monitoring module under a preset operating voltage; monitoring the timing margin indicator code output by the comparison logic module until the characterization circuit is in a critical operating state; and determining the maximum operating frequency under the preset operating voltage based on the current clock cycle of the circuit and the delay of the timing monitoring module.

[0013] According to the adaptive frequency and voltage regulation chip control method provided in this application, after determining the maximum operating frequency under a preset operating voltage based on the current circuit's clock cycle and the delay of the timing monitoring module, the method further includes: acquiring multiple preset operating voltages and the maximum operating frequency corresponding to each preset operating voltage; generating a frequency-voltage relationship table based on the multiple preset operating voltages and the maximum operating frequency corresponding to each preset operating voltage; the frequency-voltage relationship table is used to adaptively adjust the chip's operating frequency or operating voltage.

[0014] According to the adaptive frequency and voltage regulation chip control method provided in this application, after generating a frequency-voltage relationship table based on multiple preset operating voltages and the maximum operating frequency corresponding to each preset operating voltage, the method further includes: in response to a low-power task, reading initial operating parameters from the frequency-voltage relationship table; combining a timing margin indicator code, performing frequency or voltage reduction processing on the initial operating parameters until the timing margin indicator code indicates a critical state, and determining the target operating parameters for the low-power task to achieve the lowest power consumption.

[0015] According to the adaptive frequency and voltage modulation chip control method provided in this application, after generating a frequency-voltage relationship table based on multiple preset operating voltages and the maximum operating frequency corresponding to each preset operating voltage, the method further includes: responding to a high-power task by reading initial operating parameters from the frequency-voltage relationship table; combining a timing margin indicator code to perform frequency or voltage boosting on the initial operating parameters until the timing margin indicator code indicates a critical state, and determining the target operating parameters for the high-power task.

[0016] This application provides an adaptive frequency and voltage modulation chip control circuit and method. The control circuit includes: a timing monitoring module, comprising a critical path replication submodule and a daisy-chain delay submodule connected together. The critical path replication submodule is used to simulate the actual critical data path in the chip. The daisy-chain delay submodule includes multiple delay units connected in sequence, and is used to apply a timing delay to the output data signal. The delay amount can be configured to simulate the timing performance at different time points. A comparison logic module has its input terminals connected to the output terminals of a first flip-flop and multiple output terminals of a sampling flip-flop module, respectively, for generating a multi-bit timing margin indicator code based on the comparison result. The timing margin indicator code can characterize the delay state of the timing monitoring module and is used to adaptively adjust the chip's operating frequency or operating voltage. Through the above methods, this application can monitor the timing status of the chip in real time and adaptively adjust the chip's operating frequency and voltage according to the generated timing margin indicator code, enabling the chip to better adapt to various complex and changing working scenarios; fully utilize the design margin to improve energy efficiency, thereby achieving extremely low power consumption; in addition, the configurable delay allows the timing monitoring module to adapt to different chip working scenarios and requirements, and can accurately monitor the timing status under corresponding conditions by adjusting the delay, thereby achieving more flexible and precise adaptive frequency and voltage regulation control. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is one of the structural schematic diagrams of the adaptive frequency and voltage modulation chip control circuit provided in the embodiments of this application.

[0019] Figure 2 This is the second schematic diagram of the adaptive frequency and voltage modulation chip control circuit provided in the embodiments of this application.

[0020] Figure 3 This is a schematic flowchart of the adaptive frequency and voltage modulation chip control method provided in the embodiments of this application. Detailed Implementation

[0021] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0022] In the description of the embodiments of this application, it should be noted that the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance. Unless otherwise expressly specified and limited, the terms "connected" and "linked" should be interpreted broadly, for example, they can be fixed connections, detachable connections, or integral connections; they can be mechanical connections or electrical connections; they can be direct connections or indirect connections through an intermediate medium. Those skilled in the art can understand the specific meaning of the above terms in the embodiments of this application based on the specific circumstances.

[0023] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of the embodiments of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0024] This application provides an adaptive frequency and voltage modulation chip control circuit that can fully utilize design margins, improve energy efficiency, and thus achieve extremely low power consumption.

[0025] Please see Figure 1 , Figure 1 This is one of the structural schematic diagrams of the adaptive frequency and voltage modulation chip control circuit provided in the embodiments of this application.

[0026] In this embodiment, the adaptive frequency and voltage regulation chip control circuit includes a timing monitoring module 110, a first flip-flop 120, a sampling flip-flop module 130, and a comparison logic module 140. These modules cooperate with each other to generate a timing margin indicator code by monitoring and analyzing the chip timing, thereby realizing adaptive adjustment of the chip's operating frequency or operating voltage.

[0027] The timing monitoring module 110 includes a critical path replication submodule 111 and a daisy-chain delay submodule 112 connected to each other. The critical path replication submodule 111 is used to simulate the actual critical data path in the chip. The daisy-chain delay submodule 112 includes multiple delay units connected in sequence. The daisy-chain delay submodule 112 is used to apply a timing delay to the output data signal. The delay can be configured to simulate the timing performance after different time points.

[0028] The first trigger 120 has its output connected to the input of the timing monitoring module 110, and is used to transmit data signals to the timing monitoring module 110 under the drive of the clock signal.

[0029] The sampling trigger module 130 has its input connected to the output of the timing monitoring module 110. It is used to sample the data signal delayed by the timing monitoring module 110 under the drive of the clock signal to obtain multiple sampled outputs.

[0030] The comparison logic module 140 has its input terminals connected to the output terminals of the first flip-flop 120 and multiple output terminals of the sampling flip-flop module 130, respectively. It is used to generate a multi-bit timing margin indicator code based on the comparison result. The timing margin indicator code can characterize the delay state of the timing monitoring module and is used to adaptively adjust the chip's operating frequency or operating voltage.

[0031] In this embodiment, the critical path replication submodule 111 is used to simulate the actual critical data path in the chip.

[0032] The critical path replication submodule 111 simulates the signal transmission process on the actual critical data path by replicating the circuit structure of that path within the chip. During normal chip operation, the actual critical data path transmits various data signals, and the critical path replication submodule 111 simultaneously processes the same data signals. Therefore, by monitoring the signal transmission of the critical path replication submodule 111, the timing performance of the actual critical data path can be indirectly understood.

[0033] The daisy-chain delay submodule 112 consists of multiple delay units connected in sequence. Optionally, the delay units can be inverters. The function of the daisy-chain delay submodule 112 is to apply a timing delay to the output data signal, and this delay is configurable. Therefore, the timing performance of the chip at different time points can be simulated, thereby providing a more comprehensive evaluation of the chip's timing characteristics.

[0034] For example, when a data signal enters the daisy-chain delay submodule 112, the signal will experience a certain delay after passing through each delay unit. Since the delay units in this embodiment are connected sequentially, the signal will accumulate a total delay after passing through multiple delay units. Moreover, this delay is configurable; by adjusting the number of delay units involved in signal delay or changing the parameters of the delay units, the timing behavior at different time points can be simulated.

[0035] The first flip-flop 120 operates under the drive of a clock signal. This clock signal is a periodic signal that provides a time base for register operations.

[0036] The input of the sampling trigger module 130 is connected to the output of the timing monitoring module 110. The sampling trigger module 130 also operates under the drive of a clock signal. The sampling process involves acquiring the current state of the data signal at a specific moment and storing it in the sampling trigger module 130.

[0037] The input terminals of the comparison logic module 140 are respectively connected to the output terminals of the first flip-flop 120 and multiple output terminals of the sampling flip-flop module 130. The comparison logic module 140 can compare the original data signal output by the first flip-flop 120 with multiple sampled data signals output by the sampling flip-flop module 130 to determine the state change of the data signal after being delayed by the timing monitoring module 110.

[0038] Based on the comparison results, the comparison logic module 140 can generate a multi-bit timing margin indicator code. The timing margin indicator code can be used to characterize the delay state of the timing monitoring module 110, thereby providing a basis for adaptively adjusting the chip's operating frequency or operating voltage.

[0039] In the adaptive frequency and voltage regulation chip control circuit provided in this application embodiment, by monitoring the chip's timing margin in real time, the operating frequency or voltage can be adaptively adjusted according to the chip's actual operating state. When the chip's timing margin is large, the operating frequency can be appropriately increased, thereby improving the chip's processing speed; when the chip's timing margin is small, the operating frequency or voltage can be reduced to ensure the chip's stability; different operating scenarios have different performance requirements for the chip. Through adaptive frequency and voltage regulation, the chip's power consumption can be reduced while meeting performance requirements.

[0040] Furthermore, the delay of this control circuit is configurable, enabling the simulation of different timing scenarios. This allows chip designers to more flexibly evaluate the timing characteristics of the chip during the design process and optimize the chip design. By simulating the chip's critical data paths and timing performance at different points in time, potential timing problems can be identified in a timely manner. Once insufficient timing margin is found, the operating frequency or voltage can be adjusted promptly to avoid chip failures caused by timing issues, thereby improving the chip's reliability and stability.

[0041] Unlike the DVFS open-loop design mentioned in related technologies, this embodiment uses AVFS, which can be precisely adjusted according to the actual operating conditions of the chip to fully utilize the circuit's maximum performance. Therefore, the chip can operate with minimal power consumption in different operating scenarios, achieving extremely low power consumption, greatly improving energy efficiency, and extending the device's battery life.

[0042] Since the timing state of a chip is affected by various factors such as temperature, voltage, and manufacturing process, this control circuit can monitor and adapt to these changes in real time. For example, when the chip temperature rises, causing transistor performance to degrade and signal delay to increase, the control circuit can compensate for this change by adjusting the operating frequency or voltage, ensuring that the chip can operate stably under different operating environments and improving the chip's reliability and stability.

[0043] For processors like GPGPUs, whose operating scenarios are unpredictable, this embodiment can dynamically adjust based on real-time timing monitoring results, enabling the chip to better adapt to various complex and changing operating environments. Whether under high or low load conditions, the chip maintains stable performance, avoiding performance fluctuations caused by changes in operating scenarios, thus improving the chip's overall performance and adaptability.

[0044] In some embodiments, the sampling trigger module includes multiple sampling triggers, and a fixed delay unit is provided between the signal input paths of adjacent sampling triggers, so that there is a preset time difference in the time when the data signal arrives at the input terminal of each sampling trigger, so as to perform time-division sampling on the data signal after being delayed by the timing monitoring module.

[0045] The sampling trigger module consists of multiple sampling triggers, with fixed delay units set between the signal input paths of adjacent sampling triggers. These delay units have stable and known delay characteristics. When the data signal, after being delayed by the timing monitoring module, passes through a fixed delay unit during transmission, a fixed time delay is generated, and the time it takes for the data signal to arrive at the input terminals of each sampling trigger will form a preset time difference.

[0046] For example, suppose the first sampling flip-flop receives a data signal at time t1. After a fixed delay unit, the second sampling flip-flop will receive the data signal at time t1+Δt (where Δt is the delay time of the fixed delay unit), and so on. Under the synchronous control of the clock signal, each sampling flip-flop samples the data signal at its corresponding time point, thus realizing time-division sampling.

[0047] In some embodiments, the comparison logic module includes a plurality of XOR units, each XOR unit being used to compare the output data of the first flip-flop with the output data of a corresponding sampling flip-flop in the sampling flip-flop module to generate one bit of a timing margin indicator code.

[0048] The comparison logic module contains multiple XOR units, each with two input ports. One port is connected to the output of the first flip-flop to obtain the original data signal; the other port is connected to the output of a corresponding sampling flip-flop in the sampling flip-flop module to obtain the data signal after delay and sampling.

[0049] Each XOR unit performs an XOR operation on its two input signals. The rule for the XOR operation is that when the two input signals are the same, the output is 0; when the two input signals are different, the output is 1.

[0050] The output of each XOR unit constitutes one bit of the timing margin indicator code. The outputs of multiple XOR units are combined to form a multi-bit timing margin indicator code. This indicator code reflects the difference between the data signal and the original signal after different delays, thus characterizing the delay status of the timing monitoring module.

[0051] In this embodiment, the difference between the original data signal and the sampled data signal after different delays can be accurately compared through XOR operation. Each bit of the timing margin indicator code corresponds to the sampling result at a specific time point. The combination of multiple indicator codes can describe in detail the changes of the data signal at different delay stages, providing accurate data for accurately evaluating the timing margin of the chip.

[0052] In some embodiments, the fixed delay unit includes a first fixed delay unit and a second fixed delay unit; the input of the first fixed delay unit is connected to the output of the timing monitoring module; and the output of the first fixed delay unit is connected to the input of the second fixed delay unit.

[0053] The multiple XOR units include a first XOR unit, a second XOR unit, and a third XOR unit; the first XOR unit, the second XOR unit, and the third XOR unit are respectively connected to the output terminal of the first flip-flop.

[0054] The multiple sampling triggers include a first sampling trigger, a second sampling trigger, and a third sampling trigger. The first sampling trigger is connected to the output of the timing monitoring module, the clock signal, and the first XOR unit, respectively. The second sampling trigger is connected to the output of the first fixed delay unit, the clock signal, and the second XOR unit, respectively. The third sampling trigger is connected to the output of the second fixed delay unit, the clock signal, and the third XOR unit, respectively.

[0055] In some embodiments, when the timing margin indicator code is 000 or 001, it indicates that the current timing margin is sufficient, and instructs the chip's control module to increase the operating frequency or decrease the operating voltage.

[0056] When the timing margin indicator code is 011 or 111, it indicates that the current timing margin is in a critical state, and instructs the chip's control module to maintain the current operating frequency and operating voltage.

[0057] As mentioned in the above embodiments, the comparison logic module compares the output data of the first flip-flop with the output data of the corresponding sampling flip-flop in the sampling flip-flop module through multiple XOR units to generate a timing margin indicator code. Each bit of the timing margin indicator code reflects the difference between the delayed and sampled data signal and the original data signal at a specific delay time point.

[0058] Specifically, when the timing margin indicator is 000, the data signals sampled by the three sampling flip-flops are identical to the original data signal output by the first flip-flop in their corresponding XOR operations. This means that the data signals remain essentially unchanged after different delays, indicating that the timing margin of the current chip is very sufficient. When the timing margin indicator is 001, only one sampling point's data signal differs from the original signal, still indicating that the overall timing margin is relatively sufficient.

[0059] At this point, the chip's control module can make corresponding adjustments based on this information. Increasing the operating frequency allows the chip to process more tasks per unit time, thereby improving chip performance; decreasing the operating voltage reduces chip power consumption and improves energy efficiency.

[0060] When the timing margin indicator is 011, the data signals at two sampling points are different from the original signal. When the timing margin indicator is 111, the data signals at all three sampling points are different from the original signal. This indicates that the data signal has changed significantly after the delay, suggesting that the timing margin of the current chip is in a critical state and is close to the edge of timing errors.

[0061] At this point, the chip's control module will maintain the current operating frequency and voltage. This is because, under critical conditions, any adjustment to the frequency or voltage could cause timing errors and affect the chip's normal operation. Therefore, maintaining the current state is to ensure the chip's stability.

[0062] In this embodiment, dynamic adjustment based on timing margin indicator codes enables the chip to respond in real time according to its own timing status. This adaptive adjustment mechanism enhances the chip's adaptability to different workloads and environmental conditions, improving the chip's overall performance and reliability.

[0063] In this embodiment, AVFS is used, and AVFS relies on a timing monitor for monitoring. Specifically, the operating status of the function is reflected by monitoring the sampling between two registers. If the monitoring circuit is working normally, it indicates that there is still room to further reduce the current operating conditions, such as reducing the operating voltage or frequency. However, if the monitoring circuit malfunctions, it means that the critical condition has been reached, and the operating conditions cannot be further reduced, otherwise it may affect the normal operation of the system.

[0064] The monitoring circuit operates continuously, combining two key factors—voltage and temperature—to construct a closed-loop power control system. Based on the monitored information, this system performs real-time, dynamic closed-loop power control on the System-on-Chip (SoC), thereby optimizing power consumption while ensuring system performance.

[0065] Please see Figure 2 , Figure 2 This is the second schematic diagram of the adaptive frequency and voltage modulation chip control circuit provided in the embodiments of this application.

[0066] The fixed delay unit includes a first fixed delay unit and a second fixed delay unit; the delay time of both the first fixed delay unit and the second fixed delay unit is 30ps.

[0067] The input of the first fixed delay unit is connected to the output of the timing monitoring module 210; the output of the first fixed delay unit is connected to the input of the second fixed delay unit. The timing monitoring module 210 includes a critical path (corresponding to the critical path replication submodule mentioned above) and a daisy chain delay submodule.

[0068] Multiple XOR units include a first XOR unit P[2], a second XOR unit P[1], and a third XOR unit P[0]; the first XOR unit P[2], the second XOR unit P[1], and the third XOR unit P[0] are respectively connected to the output terminal of the first flip-flop.

[0069] Multiple sampling triggers include a first sampling trigger, a second sampling trigger, and a third sampling trigger. The first sampling trigger is connected to the output terminal of the timing monitoring module 210, the clock signal, and the first XOR unit P[2], respectively. The second sampling trigger is connected to the output terminal of the first fixed delay unit, the clock signal, and the second XOR unit P[1], respectively. The third sampling trigger is connected to the output terminal of the second fixed delay unit, the clock signal, and the third XOR unit P[0].

[0070] In addition, an inverter I[0] can be provided between the first flip-flop and multiple XOR units of the comparison logic module. The inverter I[0] is used to make the value of the first flip-flop change in each clock cycle. For example, in the previous clock cycle, Q i Q is 0 in the next clock cycle. i+1 The value is 1, thus achieving the purpose of real-time comparison.

[0071] In this embodiment, the flip-flop (FF) includes a data input (D), a clock input (CLK), and an output (Q). The clock input (CLK) of different flip-flops is connected to the signals output by different registers.

[0072] For example, the first flip-flop is connected to the reg0 signal output from the first register; the first sampling flip-flop is connected to the reg1 signal output from the second register; the second sampling flip-flop is connected to the reg2 signal output from the third register; and the third sampling flip-flop is connected to the reg3 signal output from the fourth register.

[0073] In hardware circuits, the highest operating frequency that a circuit can achieve is determined by the highest frequency of the critical path. The critical path mainly consists of two parts: the clock path and the data path.

[0074] In practical applications, it is necessary to know the exact highest frequency of the hardware circuit. Therefore, the actual critical path needs to be processed in order to make it possible to measure.

[0075] Specifically, the original critical path is copied as a critical path copying submodule, where the critical path includes the critical clock path and the critical data path. By copying, relevant tests can be performed without affecting the normal operation of the original circuit.

[0076] Add a configurable daisy chain delay submodule after the copied critical data path. This module can consist of inverters (inv) with 64 stages of inverters inserted.

[0077] The purpose of inserting a delay chain is to simulate the transmission of a signal over a certain period of time. Because each inverter stage introduces a certain delay, the maximum cumulative delay time of 64 inverter stages is 640 ps.

[0078] When the forward detection circuit fails to function properly, while the functional circuit still functions normally, this can serve as an early warning signal, indicating a potential timing risk in the circuit. In this case, an adaptive voltage and frequency adjustment (AVFS) closed-loop power control system can be used to adjust the circuit's operating conditions in a timely manner, such as adjusting the voltage or frequency, to avoid circuit failures caused by timing issues.

[0079] Combined with appendix Figure 2A flip-flop is placed at the source as a launch stimulus. This flip-flop generates a signal each clock cycle to initiate data transmission along the critical path. Three flip-flops are placed sequentially at the destination, with a 30ps delay manually set between each stage of the flip-flop at the destination. These flip-flops act as capture units, used to capture the signal after it has traveled along the critical path. By setting different delays, the timing can be projected 30ps and 60ps later, providing a more comprehensive understanding of the signal transmission characteristics along the critical path.

[0080] For the subsequent three stages of flip-flops, each stage performs an XOR operation. The purpose of the XOR logic is to check whether the signals at the source and destination are consistent. Performing this check in every clock cycle allows for real-time monitoring of signal transmission errors along the critical path.

[0081] In this embodiment, the timing margin indicator code Pass[2:0] can be used to indicate whether there is still a margin in the current sampling. The timing margin indicator code Pass[2:0] can be regarded as a 3-bit status flag, with each bit corresponding to the detection result of the first-level trigger. Through these 3 bits, the timing margin of the signal under different delay conditions can be intuitively understood.

[0082] In summary, this embodiment can detect potential timing problems in advance by copying the critical path, inserting delay chains, and setting excitation capture units, providing a time window for timely adjustment of operating conditions and avoiding circuit errors due to timing faults. By setting different delays and performing multi-level XOR logic detection, the signal transmission status can be monitored at multiple time points, providing a more comprehensive understanding of the circuit's timing characteristics and offering a more accurate basis for AVFS closed-loop power control. Using Pass[2:0] to represent timing margins allows the timing situation to be presented in a quantitative manner, facilitating precise adjustment of operating conditions based on the margin situation and achieving a balance between performance and power consumption.

[0083] This application also provides an adaptive frequency and voltage modulation chip control method, which uses the above-described adaptive frequency and voltage modulation chip control circuit.

[0084] Please see Figure 3 , Figure 3 This is a schematic flowchart of the adaptive frequency and voltage modulation chip control method provided in this application embodiment. In this embodiment, the adaptive frequency and voltage modulation chip control method may include steps S310 to S330, each step of which is as follows: S310: Under the preset operating voltage, gradually adjust the delay of the timing monitoring module.

[0085] Before initiating the adaptive frequency and voltage regulation process, the chip can first set a preset operating voltage. The preset operating voltage can be the chip's default operating voltage, or it can be a voltage value predetermined based on previous operating experience, application scenarios, and other factors.

[0086] Using the aforementioned adaptive frequency and voltage modulation chip control circuit, the timing monitoring module simulates critical paths within the chip and applies a configurable delay to the data signals. By adjusting the delay amount, the signal transmission delay within the chip under different operating conditions can be simulated, allowing for subsequent observation of changes in the chip's timing margin.

[0087] S320: Monitors the timing margin indicator code output by the comparison logic module until the characterization circuit is in a critical operating state.

[0088] Using the aforementioned adaptive frequency and voltage modulation chip control circuit, the comparison logic module generates a timing margin indicator code by comparing the original data signal output by the first flip-flop with the data signal output by the sampling flip-flop module after different delays and sampling.

[0089] During the gradual adjustment of the timing monitoring module's delay, the timing margin indicator code is continuously monitored. When the indicator code reaches a specific value (such as 011 or 111 mentioned in the above embodiment), it indicates that the current circuit is in a critical operating state. In the critical operating state, the chip's timing margin is close to its limit, and there is no need to change the operating parameters.

[0090] S330: Determines the maximum operating frequency under the preset operating voltage based on the current circuit's clock cycle and the delay of the timing monitoring module.

[0091] In the chip manufacturing process, manufacturing process deviations are an unavoidable problem. Differences in doping concentration, diffusion depth, and etching degree can cause performance differences between different batches of chips, and even between chips on different wafers in the same batch.

[0092] Even under the same process corner conditions, the maximum frequency that each chip can achieve is not the same. Some chips may have a maximum frequency higher than the frequency at which the chip design was finalized (signoff), while others may have a frequency lower than that design frequency.

[0093] Therefore, it is necessary to accurately determine the maximum operating frequency (Fmax) of each chip. On the one hand, this helps to differentiate and select products, allowing chips with different performance levels to be applied to suitable scenarios; on the other hand, it enables the calibration of the chip's frequency-voltage coefficient table (F-VFtable), allowing the adaptive voltage-frequency adjustment (AVFS) function to be implemented precisely, effectively reducing the chip's dynamic power consumption.

[0094] In this embodiment, based on the relationship between clock cycle and delay, the maximum operating frequency at which the chip can operate stably under the current preset operating voltage can be calculated. The maximum operating frequency is the reciprocal of the clock cycle. Through precise calculation, the upper limit of the chip's performance under this preset operating voltage can be determined, providing data support for subsequent adaptive frequency and voltage adjustment.

[0095] In a chip, a function circuit must meet the setup time constraint Tdata during normal operation. <Tclk+T; Where Tdata represents the data transmission time; Tclk represents the clock cycle; and T represents the circuit's operating time.

[0096] To determine the circuit's maximum operating frequency, the data path delay can be altered by adjusting the daisy chain delay modules. The daisy chain is continuously adjusted until the circuit reaches a critical operating condition—a state where it just barely fails to function properly; at this point, the timing margin indicator will display 111.

[0097] Under critical operating conditions, the time constraint becomes: Tdata + Tdaisy = Tclk + T.

[0098] Where Tdaisy is the delay introduced by the daisy chain delay submodule. Based on the relationship between clock period and frequency, Tclk=1 / f, the critical setup time formula can be transformed to obtain the formula for calculating the maximum operating frequency Fmax of the circuit: Fmax=1 / (T-Tdaisy).

[0099] The method described in this application, by gradually adjusting the delay and monitoring the timing margin indicator code, can accurately find the critical operating state of the chip under a preset operating voltage. The maximum operating frequency determined based on the clock cycle and delay under this state accurately reflects the chip's performance upper limit at that voltage, avoiding performance waste or stability issues caused by inaccurate estimation. After determining the maximum operating frequency under the preset operating voltage, the chip control circuit can adaptively adjust the chip's operating frequency within the maximum operating frequency range according to actual operating needs and performance requirements. Furthermore, by combining the maximum operating frequency data under different operating voltages, the selection of the operating voltage can be further optimized to achieve the best balance between chip performance and power consumption.

[0100] In some embodiments, the step of determining the maximum operating frequency at a preset operating voltage based on the clock cycle of the current circuit and the delay of the timing monitoring module may further include: Obtain multiple preset operating voltages and the maximum operating frequency corresponding to each preset operating voltage; generate a frequency-voltage relationship table based on the multiple preset operating voltages and the maximum operating frequency corresponding to each preset operating voltage; the frequency-voltage relationship table is used to adaptively adjust the chip's operating frequency or operating voltage.

[0101] In the above embodiments, the maximum operating frequency of the chip under a preset operating voltage has been determined. To gain a more comprehensive understanding of the chip's performance under different voltages, multiple preset operating voltages can be obtained, and for each preset operating voltage, steps S310-S330 in the previous adaptive frequency and voltage regulation chip control method are repeated to determine the maximum operating frequency corresponding to that preset operating voltage.

[0102] The obtained preset operating voltages and their corresponding maximum operating frequencies are organized to form a frequency-voltage relationship table (F-Vt table).

[0103] The frequency-voltage relationship table visually displays the maximum operating frequency that the chip can achieve at different operating voltages, reflecting the correspondence between the chip's operating frequency and operating voltage. The chip's control module can dynamically adjust the chip's operating frequency or operating voltage based on the actual workload and performance requirements, referring to the frequency-voltage relationship table.

[0104] For example, when a chip needs to handle high-load tasks and has high performance requirements, the control module can select a working voltage from the relationship table that can provide a sufficiently high operating frequency to improve chip performance; when the device is in a low-load operating state, the control module can reduce the operating voltage according to the relationship table, and at the same time appropriately reduce the operating frequency to reduce power consumption and extend the device's battery life.

[0105] It is important to note that calibrating the frequency-voltage (F-Vt) table is crucial for chip performance optimization and power consumption control. By calibrating this table, appropriate threshold voltages can be found for different operating frequencies, thereby reducing power consumption while meeting performance requirements.

[0106] For example, an operating frequency is selected, which can be lower than the previously measured maximum operating frequency. Choosing a suitable operating frequency is to simulate different operating scenarios for the chip in real-world applications. Using a PVT (process, voltage, temperature) sensor, the limiting threshold voltage environment in which the chip can operate normally at the target frequency is tested by adjusting the threshold voltage (VT) without affecting chip performance. The PVT sensor can monitor changes in the chip's process, voltage, and temperature in real time, providing a reference for adjusting the threshold voltage.

[0107] Multiple sets of tests were conducted, and the corresponding limit threshold voltages at different operating frequencies were recorded. By analyzing and processing these test data, a frequency-voltage relationship table (F-Vt table) was calibrated, which reflects the minimum threshold voltage required by the chip at different operating frequencies, so as to achieve a balance between performance and power consumption.

[0108] Furthermore, the calibrated frequency-voltage (F-Vt) table can be written into flash memory as static parameters under laboratory testing conditions. The relevant parameters in the F-Vt table can be read and used during subsequent chip operation. In practical applications, the chip can look up the corresponding threshold voltage from the table based on the current operating frequency, thereby achieving adaptive voltage adjustment.

[0109] In some embodiments, the step following the generation of a frequency-voltage relationship table based on multiple preset operating voltages and the maximum operating frequency corresponding to each preset operating voltage may further include: In response to a low-power task, the initial operating parameters are read from the frequency-voltage relationship table; combined with the timing margin indicator code, the initial operating parameters are down-frequency or down-voltage processed until the timing margin indicator code indicates a critical state, and the target operating parameters of the low-power task are determined to achieve the lowest power consumption.

[0110] In this embodiment, this operation can be triggered when the chip detects that it is currently facing a low-power task, such as when the device is in standby mode or executing a simple background program, which are scenarios with low performance requirements.

[0111] The chip control module reads the initial operating parameters from the previously generated frequency-voltage relationship table.

[0112] Timing margin indicators reflect the chip's current timing margin status in real time. During frequency or voltage reduction, the chip control module continuously monitors this indicator. The control module gradually reduces the operating frequency or voltage. Each adjustment checks the timing margin indicator output by the comparison logic module. If the indicator still indicates sufficient timing margin (e.g., 000 or 001 as mentioned earlier), the frequency or voltage reduction operation continues; if the indicator shows that the timing margin is approaching a critical state, the magnitude of the frequency or voltage reduction is adjusted appropriately to ensure the smoothness of the adjustment process.

[0113] When the timing margin indicator code is set to a critical state (e.g., 011 or 111), it means that the chip's timing margin is nearing its limit. At this point, the current operating frequency and voltage are determined as the target operating parameters for the low-power task. Under these parameters, the chip can meet the basic performance requirements of the low-power task while minimizing power consumption.

[0114] For example, when a GPGPU starts a low-power process, its operating frequency and operating conditions need to be adjusted to reduce power consumption and optimize energy efficiency. The specific process is as follows: 1. Calculate the target frequency: Based on factors such as the computational complexity and data processing volume of the low-power process, calculate the operating frequency required for the process to run normally.

[0115] 2. Reduce operating frequency: Reduce the GPGPU frequency to the target frequency. Since power consumption is positively correlated with frequency, this can directly reduce power consumption.

[0116] 3. Read the minimum operating conditions: Read the minimum operating conditions corresponding to the target frequency from the calibrated frequency-voltage relationship table.

[0117] 4. Initial adjustment: Considering that there may be errors between the frequency-voltage relationship table and the actual situation, in order to ensure the stability of the adjustment, first adjust the working conditions to 1.1 times the corresponding value in the table.

[0118] 5. Approaching the minimum condition: Gradually reduce the operating conditions to approach the minimum value. During this process, pay attention to the timing margin indicator code of the Timingmonitor circuit. If the indicator code is unqualified, the operating conditions need to be appropriately increased.

[0119] 6. Exhaust margin: Continuously adjust and exhaust all timing margins to reduce GPGPU to the lowest possible operating conditions, thereby minimizing power consumption while meeting process requirements.

[0120] In some embodiments, the step following the generation of a frequency-voltage relationship table based on multiple preset operating voltages and the maximum operating frequency corresponding to each preset operating voltage may further include: In response to high-power tasks, the initial operating parameters are read from the frequency-voltage relationship table; the initial operating parameters are then frequency-increased or voltage-increased in conjunction with the timing margin indicator code until the timing margin indicator code indicates a critical state, and the target operating parameters for the high-power task are determined.

[0121] In this embodiment, this operation can be triggered when the chip receives a high-load task with extremely high computing performance requirements, such as running a large game, performing video editing, or executing complex scientific calculations.

[0122] Similar to the above embodiments, this embodiment uses frequency and voltage boosting to significantly improve the chip's computing power and data processing speed during high-power tasks, ensuring that tasks can be completed efficiently.

[0123] For example, when a GPGPU suddenly starts a high-power process, if the current bandwidth cannot meet the process's requirements, the GPGPU needs to be clocked up. The specific process is as follows: 1. Read the maximum operating frequency (Fmax): Read the Fmax corresponding to the current operating conditions from the calibrated frequency-voltage relationship table.

[0124] 2. Determine the processing method based on Fmax: 2.1 If Fmax can meet the process bandwidth requirements, increase the GPGPU operating frequency under current operating conditions. Considering the error between the frequency-voltage relationship table and reality, adjust the frequency data according to actual operating conditions (such as temperature and voltage fluctuations), and gradually adjust it to the target frequency that meets the process requirements. During the process, pay attention to the timing margin indicator code of the Timing Monitor circuit to ensure that the timing is qualified and avoid data transmission errors or circuit failures.

[0125] 2.2 If Fmax cannot meet the bandwidth requirements, increase the operating voltage and frequency of the GPGPU, adopt closed-loop control, monitor the GPGPU performance indicators (such as bandwidth and timing) and operating conditions (such as temperature and voltage) in real time, and dynamically adjust the voltage and frequency to ensure stability and reliability.

[0126] The embodiments of this application provide an adaptive frequency and voltage modulation chip control circuit and method. By simulating the actual critical data path in the chip through a critical path replication submodule, it can accurately reflect the transmission status of key signals within the chip. The daisy-chain delay submodule can apply a configurable delay to the output data signal, simulating timing performance at different time points. Combined with sampling trigger module sampling the delayed data signal and comparison logic module generating timing margin indicator codes, the chip's timing status can be monitored in real time. This allows for timely detection of timing problems during chip operation and rapid adjustments to ensure stable chip operation. Based on the generated timing margin indicator codes, the chip's operating frequency or voltage can be adaptively adjusted. When the chip is under relatively relaxed operating conditions, i.e., with a large timing margin, the chip's operating frequency and voltage can be appropriately reduced to decrease power consumption. Conversely, when the chip requires high performance, the operating frequency and voltage can be increased promptly to meet performance demands. This adaptive adjustment method can significantly reduce the chip's average power consumption and improve energy efficiency while ensuring chip performance.

[0127] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement this without any creative effort.

[0128] Through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus necessary general-purpose hardware platforms, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solutions, in essence or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods described in the various embodiments or some parts of the embodiments.

[0129] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application.

Claims

1. A chip control circuit for adaptive frequency and voltage scaling, characterized by The chip control circuit comprises: a timing monitoring module, which comprises a critical path replica submodule and a daisy chain delay submodule connected in sequence, the critical path replica submodule being used to simulate an actual critical data path in a chip, the daisy chain delay submodule comprising a plurality of delay units connected in sequence, the daisy chain delay submodule being used to apply a delay amount to an output data signal in terms of timing, the delay amount being configurable to simulate timing performance at different time points; a first flip-flop, an output end of which is connected to an input end of the timing monitoring module, and which is used to transmit a data signal to the timing monitoring module under the driving of a clock signal; a sampling flip-flop module, an input end of which is connected to an output end of the timing monitoring module, and which is used to sample the data signal delayed by the timing monitoring module under the driving of the clock signal to obtain a plurality of sampling outputs; a comparison logic module, input ends of which are connected to an output end of the first flip-flop and the plurality of output ends of the sampling flip-flop module respectively, and which is used to generate a multi-bit timing margin indication code through a comparison result; the timing margin indication code being capable of representing a delay state of the timing monitoring module, and being used to adaptively adjust a working frequency or a working voltage of the chip.

2. The adaptive frequency and voltage scaling chip control circuit of claim 1, wherein, The delay unit is an inverter.

3. The adaptive frequency and voltage scaling chip control circuit of claim 1, wherein, The sampling flip-flop module comprises a plurality of sampling flip-flops, and a fixed delay unit is arranged between signal input paths of adjacent sampling flip-flops, so that there is a preset time difference in the time when the data signal reaches the input ends of the respective sampling flip-flops, thereby performing time-sharing sampling on the data signal delayed by the timing monitoring module.

4. The adaptive frequency and voltage scaling chip control circuit of claim 3, wherein, The comparison logic module comprises a plurality of XOR units, each of which is used to compare the output data of the first flip-flop with the output data of a corresponding sampling flip-flop in the sampling flip-flop module to generate one bit of the timing margin indication code.

5. The adaptive frequency and voltage scaling chip control circuit of claim 4, wherein, The fixed delay unit comprises a first fixed delay unit and a second fixed delay unit; an input end of the first fixed delay unit is connected to an output end of the timing monitoring module; an output end of the first fixed delay unit is connected to an input end of the second fixed delay unit. The plurality of XOR units comprise a first XOR unit, a second XOR unit and a third XOR unit; the first XOR unit, the second XOR unit and the third XOR unit are connected to the output end of the first flip-flop respectively. The plurality of sampling flip-flops comprise a first sampling flip-flop, a second sampling flip-flop and a third sampling flip-flop; the first sampling flip-flop is connected to the output end of the timing monitoring module, the clock signal and the first XOR unit respectively; the second sampling flip-flop is connected to the output end of the first fixed delay unit, the clock signal and the second XOR unit respectively; the third sampling flip-flop is connected to the output end of the second fixed delay unit, the clock signal and the third XOR unit respectively.

6. The chip control circuit according to any one of claims 1 to 5, wherein When the timing margin indication code is 000 or 001, it indicates that the current timing margin is sufficient, and the control module of the chip is instructed to increase the working frequency or decrease the working voltage; When the timing margin indication code is 011 or 111, it indicates that the current timing margin is in a critical state, and the control module of the chip is instructed to maintain the current working frequency and working voltage.

7. A chip control method of adaptive frequency and voltage scaling, characterized by, The adaptive frequency and voltage adjustment chip control method using the adaptive frequency and voltage adjustment chip control circuit according to any one of claims 1 to 6 comprises: adjusting the delay amount of the timing monitoring module step by step under a preset working voltage; monitoring the timing margin indication code output by the comparison logic module until the circuit is in a critical working state; determining the maximum working frequency under the preset working voltage based on the clock period of the current circuit and the delay amount of the timing monitoring module.

8. The method of claim 7, wherein the adaptive frequency and voltage scaling of the chip is based on a temperature of the chip. After determining the maximum working frequency under the preset working voltage based on the clock period of the current circuit and the delay amount of the timing monitoring module, the method further comprises: obtaining a plurality of preset working voltages and the maximum working frequency corresponding to each preset working voltage; generating a frequency-voltage relationship table based on the plurality of preset working voltages and the maximum working frequency corresponding to each preset working voltage; the frequency-voltage relationship table is used to adaptively adjust the working frequency or working voltage of the chip.

9. The adaptive frequency and voltage scaling chip control method of claim 8, wherein, After generating the frequency-voltage relationship table based on the plurality of preset working voltages and the maximum working frequency corresponding to each preset working voltage, the method further comprises: in response to a low-power-consumption task, reading an initial working parameter from the frequency-voltage relationship table; in combination with the timing margin indication code, performing frequency reduction or voltage reduction on the initial working parameter until the timing margin indication code indicates a critical state, determining the target working parameter of the low-power-consumption task to achieve the lowest power consumption.

10. The method of claim 8, wherein the adaptive frequency and voltage scaling of the chip is based on a temperature of the chip. After generating the frequency-voltage relationship table based on the plurality of preset working voltages and the maximum working frequency corresponding to each preset working voltage, the method further comprises: in response to a high-power-consumption task, reading an initial working parameter from the frequency-voltage relationship table; in combination with the timing margin indication code, performing frequency increase or voltage increase on the initial working parameter until the timing margin indication code indicates a critical state, determining the target working parameter of the high-power-consumption task.

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