Method for Controlling a Data Storage Device and Associated Flash Memory Controller

Abstract

The present application relates to a method for controlling a data storage device (100). The data storage device (100) includes a flash memory controller (11) and a flash memory module (12). The flash memory controller (11) has a first buffer memory (113) and a second buffer memory (114). The memory module (12) has at least a first memory portion (122) and a second memory portion (123). The method includes: receiving first data from a host device (50); storing the first data in the first buffer memory (113); transferring the first data from the first buffer memory (113) to the first memory portion (122) of the flash memory module (12); and transferring the first data from the first buffer memory (113) to a host memory buffer (52) in the host device (50). The first data corresponds to at least a portion of second data to be written to the second memory portion (123).

Description

Technical Field

[0001] The present application generally relates to a data storage device, a flash memory controller, a host, and a method for controlling a data storage device, a flash memory controller, and a host. Background Art

[0002] In recent years, due to the continuous development of memory technology, various portable or non-portable data storage devices (e.g., Universal Flash Storage (UFS) standard memory cards, Solid State Disks (SSDs), and embedded storage devices compliant with UFS or eMMC specifications) have been widely implemented in many applications. Therefore, access control to the memory in such data storage devices has become a rather hot topic.

[0003] Common NAND flash memories mainly include Single-Level Cell (SLC), Multi-Level Cell (MLC), Triple-Level Cell (TLC), and Quad-Level Cell (QLC) flash memories. Due to its higher storage density and larger memory capacity, QLC flash memory has gradually become a favorable configuration of NAND flash memory.

[0004] The word line of QLC includes four-page storage spaces. If the pages of their storage spaces are not fully written, the NAND flash controller may not be able to obtain correct data from their written pages. Even worse, if the entire block of QLC is not fully written, the NAND flash controller may not be able to obtain correct data from their written pages. Such problems must be solved because they may damage data integrity.

[0005] Therefore, the present application proposes a data storage device, a flash memory controller, a host, and a method for controlling a data storage device, a flash memory controller, and a host that can solve the above problems. Summary of the Invention

[0006] The present application proposes a method for controlling a data storage device. The data storage device includes a flash memory controller and a flash memory module. The flash memory controller has a first buffer memory and a second buffer memory. The memory module has at least a first memory portion and a second memory portion. The method includes: receiving first data from a host device; storing the first data in the first buffer memory; transmitting the first data from the first buffer memory to the first memory portion of the flash memory module; and transmitting the first data from the first buffer memory to a host memory buffer in the host device. The first data corresponds to at least a part of second data to be written to the second memory portion.

[0007] The present application proposes a flash memory controller for controlling a flash memory module having at least a first memory portion and a second memory portion. The flash memory controller includes a first communication interface, a first buffer memory, and a second communication interface. The first communication interface is configured to receive first data from a host device. The first buffer memory is coupled to the first communication interface and is configured to store the first data. The second communication interface is configured to transfer the first data from the first buffer memory to the first memory portion of the flash memory module. The first communication interface is further configured to transfer the first data from the first buffer memory to a host memory buffer of the host device. The first data corresponds to at least a portion of second data to be written to the second memory portion.

[0008] The present application proposes a data storage device including a flash memory module and a flash memory controller. The flash memory module has at least a first memory portion and a second memory portion. The flash memory controller is coupled to the flash memory module. The flash memory controller includes a first communication interface, a first buffer memory, and a second communication interface. The first communication interface is configured to receive first data from a host device. The first buffer memory is coupled to the first communication interface and is configured to store the first data. The second communication interface is configured to transfer the first data from the first buffer memory to the first memory portion of the flash memory module. The first communication interface is further configured to transfer the first data from the first buffer memory to a host memory buffer of the host device. The first data corresponds to at least a portion of second data to be written to the second memory portion.

[0009] The present application proposes a method for controlling a host device. The method includes: transferring first data to a data storage device via a first communication interface; receiving first data from the data storage device via the first communication interface; and storing the received first data in a host memory buffer. The first data corresponds to at least a portion of second data to be written to the data storage device.

[0010] After reading the following detailed description of the preferred embodiments shown in the various figures and diagrams, the objectives of the present application will undoubtedly become apparent to those of ordinary skill in the art. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 A schematic diagram showing a data storage device and a host device according to some embodiments of the present application.

[0012] Figure 2 A schematic diagram showing a write sequence in a data storage device and a host device according to some embodiments of the present application.

[0013] Figure 3 A flowchart showing a method for controlling a data storage device and a host device in a write sequence according to some embodiments of the present application.

[0014] Figure 4 A schematic diagram showing the writing order in a data storage device and a host device according to some embodiments of the present application.

[0015] Figure 5 A flowchart showing a method for controlling a data storage device and a host device according to the writing order according to some embodiments of the present application.

[0016] Figure 6 A schematic diagram showing the reading order in a data storage device and a host device according to some embodiments of the present application.

[0017] Figure 7 A flowchart showing a method for controlling a data storage device and a host device according to the reading order according to some embodiments of the present application.

[0018] Figure 8 A schematic diagram showing the reading order in a data storage device and a host device according to some embodiments of the present application.

[0019] Figure 9 A flowchart showing a method for controlling a data storage device and a host device according to the reading order according to some embodiments of the present application. Detailed Description

[0020] This application claims the priority of U.S. Provisional Patent Application No. 63 / 107,420, filed on October 29, 2020, which is hereby incorporated by reference in its entirety.

[0021] Figure 1 A schematic diagram showing a data storage device 100 and a host device 50 according to some embodiments of the present application. The data storage device 100 may include a portable or non-portable data storage device, such as a memory card conforming to the SD / MMC, CF, MS, or XD standard, a non-volatile (NV) memory device, a flash memory device, or a solid-state drive (SSD). The host device 50 may include a multifunctional mobile phone, a tablet computer, a wearable device, and a personal computer such as a desktop computer or a laptop computer. The data storage device 100 may communicate with the host device 50 via wires, a system bus, or wirelessly. Data may be transmitted between the data storage device 100 and the host device 50.

[0022] As Figure 1As shown, the data storage device 100 may include a memory controller 11 and a memory module 12. The memory controller 11 may communicate with the memory module 12 via wires, a system bus, or wirelessly. The memory controller 11 may be configured to access the memory module 12. The memory module 12 may be configured to store data. The memory controller 11 may include an NV memory controller, a flash memory controller, or the like. The memory module 12 may include an NV memory module, a flash memory module, or the like.

[0023] In some embodiments, the memory controller 11 may write system operation information into the memory module 12, such as redundant array of independent disks (RAID) information, error correction code (ECC) parity, mapping tables, control flags, etc. The system operation information may be added at any step of writing data, such as a data randomization program or the like.

[0024] As Figure 1 shown, the memory controller 11 may include a communication interface 111, a communication interface 112, a buffer memory 113, a buffer memory 114, a microprocessor 115, and a read-only memory (ROM) 115m, wherein these components may be coupled to each other via a bus.

[0025] The host device 50 may indirectly access the memory module 12 in the data storage device 100 by sending a plurality of host device commands and corresponding logical addresses to the memory controller 11. The memory controller 11 may receive the plurality of host device commands and logical addresses via the communication interface 111. The memory controller 110 may translate the plurality of host device commands into memory operation commands, and then control the memory module 12 to perform read, write / program, or erase on memory cells or pages with specific physical addresses within the memory module 12. The physical addresses may correspond to the logical addresses.

[0026] The communication interface 111 can receive or transmit one or more host device commands. The communication interface 111 can receive or transmit data, where the data can include one or more logical addresses or data pages. The communication interface 112 can receive or transmit one or more memory operation commands. The communication interface 112 can receive or transmit data, where the data can include one or more physical addresses or data pages. The communication interface 111 can be a bus protocol for communication from a host device 50, such as an integrated circuit therein, to a microcontroller 115 or buffer memories 113 and 114 of the memory controller 11. The communication interface 112 can be a bus protocol for communication from the memory controller 11 to the memory module 12. The communication interface 111 or the communication interface 112 can conform to a specific communication specification (e.g., Serial Advanced Technology Attachment (SATA) specification, Universal Serial Bus (USB) specification, Peripheral Component Interconnect Express (PCIE) specification) or conform to the Non-Volatile Memory Express (NVMe), and can perform communication based on this specific communication specification. The communication interface 111 can be an NVMe interface. The communication interface 112 can be a flash interface.

[0027] The buffer memory 113 can be implemented by a random access memory (RAM). The buffer memory 114 can be implemented by a random access memory (RAM). The buffer memory 113 can be configured to store information. The buffer memory 113 can be configured to store data pages, or host device commands from the host device 50. The buffer memory 114 can be configured to store information. The buffer memory 114 can be configured to store data pages. The buffer memory 113 or the buffer memory 114 can include a random access memory (RAM).

[0028] The microprocessor 115 can be configured to execute the program code 115c stored in the ROM 115m to control access to the memory module 12. It should be noted that the program code 115c can also be stored in the buffer memory 113, the buffer memory 114, or any type of memory.

[0029] The memory module 12 may include a buffer memory 121 and a plurality of memory portions 12m, and these components may be coupled to each other via a bus. The buffer memory 121 may communicate with a memory controller 11, such as a communication interface 112. The buffer 112 may be configured to store one or more memory operation commands from the memory controller 11. The buffer 112 may be configured to store data including physical addresses from the memory controller 11. The buffer 112 may be configured to store data pages. The number of the memory portions 12m may be greater than 1. The memory portions may include, but are not limited to, a plurality of flash memory chips or dies. The memory portions 12m may include SLC, MLC, TLC, or QLC. For example, each of the memory portions 12m may include a plurality of blocks. A block including N word lines {WL(0), WL(1), WL(2)... WL(N - 3), WL(N - 2), WL(N - 1)} may be regarded as an instance of any of the plurality of blocks, where N is a positive integer. The memory controller 11 may write user data to a page of word lines in a block by using a QLC write mode. In other words, the word lines of QLC may store four pages of user data. In some embodiments, the memory controller 11 may write user data to a page of word lines in a block by using an SLC, MLC, or TLC write mode, and may perform verification of the written data before completing writing to the entire block. In some embodiments, each of the memory portions 12m may act as SLC, MLC, TLC, or QLC. The memory module 12 may include a microprocessor (not shown), and the microprocessor is configured to arrange to operate each of the memory portions 12m in an SLC, MLC, TLC, or QLC operation mode.

[0030] There are various techniques for manufacturing the memory module 12; for example, 2D / planar NAND flash technology in which memory cells are arranged in a single layer, and 3D NAND flash technology in which memory cells are arranged in multiple layers and stacked vertically. According to some embodiments, the memory module 12 may be implemented as a planar NAND flash architecture with a single layer of memory cells. According to some embodiments, the memory module 12 may be implemented as a 3D NAND flash architecture in which memory cells are stacked vertically in multiple layers.

[0031] Still referring to Figure 1, the host device 50 may include a communication interface 51 and a host storage buffer 52. The communication interface 51 may transmit one or more host device commands. The communication interface 51 may receive or transmit data, where the data may include one or more logical addresses or data pages. The communication interface 51 may comply with a specific communication specification (e.g., Serial Advanced Technology Attachment (SATA) specification, Universal Serial Bus (USB) specification, Peripheral Component Interconnect Express (PCIE) specification) or comply with the Non-Volatile Memory Express (NVMe) standard, and may perform communication based on this specific communication specification. The communication interface 51 may be an NVMe interface.

[0032] The host memory buffer (HMB) 52 may be a part of the internal storage of the host device 50 (i.e., the host memory). The HMB 52 may have a capacity of 64 megabytes (MB) or 128 MB or larger. The HMB 52 may include random access memory (RAM) or read-only memory (ROM).

[0033] The HMB 52 may provide random access to blocks of the host memory, which provides access to all components in the HMB 52. On the data storage device side, the HMB 52 may transfer data on the system bus as fast as possible, rather than attempting to optimize the bus bandwidth. On the host side, the HMB 52 and the communication interface 51 may provide low-latency access to memory, which allows for high-performance access to physical memory.

[0034] Figure 2 A schematic diagram showing the write order in a data storage device (e.g., data storage device 100) and a host device (e.g., host device 50) according to some embodiments of the present application. As discussed in the following paragraphs / sections, the operations in the embodiments disclosed in Figure 2 may be controlled by a microprocessor 115 when it executes one or more codes of program code 115c.

[0035] As Figure 2 shown, the host device 50 may transmit data or a host device command to the data storage device 100 (S11). The communication interface 111 of the data storage device 100 may be configured to receive data or a host device command from the host device 50 (S11). The communication interface 111 may be configured to receive data D1 from the host device 50. The data D1 may include a data page. In an alternative embodiment, the data D1 may include a plurality of data pages. The communication interface 111 may be configured to transmit the data D1 to the buffer memory 113 (S12), and the buffer memory is coupled to the communication interface 111 via, for example, a bus. The buffer memory 113 may be configured to store the data D1.

[0036] The buffer memory 113 may be configured to transfer the data D1 to the communication interface 112 (S21). The communication interface 112 may be configured to transfer the data D1 to the buffer memory 121 (S22). The memory section 12m may include one or more memory sections 122 and one or more memory sections 123 (i.e., one or more QLC memory sections). The memory section 123 may include SLC or QLC. The memory section 123 may include SLC. In other words, the memory section 122 may have an SLC operation mode, and the memory section 123 may have a QLC operation mode. The buffer memory 121 is coupled to the memory section 122 and the memory section 123 via, for example, a bus. The buffer memory 121 may be configured to transfer the data D1 to the memory section 122 (S23). In some embodiments, the communication interface 112 may be configured to transfer the data D1 from the buffer memory 113 to one of the memory sections 122 in the memory section 12m of the memory module 12.

[0037] In some embodiments, the microprocessor 115 may be configured to generate a signal indicating that the data D1 is to be written to the memory section 122. The signal may be transmitted to the host device 50 via the communication interface 111 after the data D1 is transferred from the buffer memory 113 to the memory section 122 of the memory module 12.

[0038] The buffer memory 113 may be configured to transfer the data D1 to the communication interface 111 (S31), and then the communication interface 111 may be configured to transfer the data D1 to the communication interface 51 (S32). The communication interface 51 may be configured to transfer the data D1 to the HMB 52 (S33). In some embodiments, the communication interface 111 may be configured to transfer the data D1 from the buffer memory 113 of the memory controller 11 to the HMB 52 of the host device 50.

[0039] HMB 52 can be configured to transfer data D1 to communication interface 51 (S41), and then communication interface 51 can be configured to transfer data D1 to communication interface 111 (S42). The microprocessor 115 can be configured to generate data D2 by modifying data D1, for example, using an error correction code (ECC), parity check technology, or the like. Data D1 can correspond to at least a part of data D2. Data D2 can include a plurality of data pages. Communication interface 111 can be configured to transfer data D2 to buffer memory 114 (S43). In some embodiments, data D2 can be transferred from HMB 52 to buffer memory 114 via communication interface 111. Buffer memory 114 can be configured to transfer data D2 to communication interface 112 (S45). Communication interface 112 can be configured to transfer data D2 to buffer memory 121 (S46). Buffer memory 121 can be configured to transfer data D2 to one of the memory portions 123 (S47). In some embodiments, communication interface 112 can be configured to transfer data D2 from buffer memory 114 to one of the memory portions 123 of memory module 12.

[0040] In some embodiments, the microprocessor 115 can be configured to generate an erase signal indicating the erasure of data D1. Communication interface 111 can be configured to transfer the erase signal to HMB 52 after data D2 has been transferred to memory portion 123. In some embodiments, the transfer rate of data D1 from buffer memory 113 to memory portion 122 of memory portion 12m is greater than the transfer rate of data D2 from buffer memory 114 to memory portion 123 of memory module 12.

[0041] In some comparative embodiments, the memory controller can be configured to perform a write operation for storing one or more data pages from a host device to the QLC memory portion of a memory module. However, the word lines of QLC contain four-page storage space. The write operation of QLC uses different sensing levels (for example, 16 sensing levels with different biases) to define different charge states (for example, 16 charge states), and the write operation of each of the QLC memory portions is performed in sequence. If the four-page storage space is not fully written, the QLC may not store the complete and correct data pages. When problems such as open wordlines or sudden power loss occur, if the write operation has been performed only by writing data pages using the first sensing level, for example, the most significant bit (MSB), the QLC memory portion may not store the complete data pages. Therefore, the data pages that should be stored in the memory module may be lost or damaged. That is, the memory controller can only obtain the written data after the QLC block has been fully written. Therefore, the memory controller should hold the entire data block until the entire QLC block has been successfully written. This will occupy a large amount of memory space.

[0042] In the present application, a dual write operation can be implemented. Data D1 is transferred from the buffer memory 113 to the memory section 122, and data D2 corresponding to data D1 is transferred from the buffer memory 114 to the memory section 123. Data D1 can be stored in the memory section 122 before the write operation of data D2 is completed in the memory section 123. The memory controller 11 can set the write operation of the memory section 122 to have a higher priority than the write operation of the memory section 123 to ensure the latency of the data storage device 100. Thus, the problem of open word lines or sharp power loss can be solved, and the speed and capacity of the data storage device can be maintained. Storing data D1 in the memory section 122 ensures the integrity of the data transferred from the host device 50 to the data storage device 100, and storing the second data D2 in the memory section 123 maintains the capacity of the memory module 12. In addition, data D1 can be stored in the HMB 52 before the write operation of data D2 is completed in the QLC section 123. Thus, the problem of open word lines or sharp power loss can be solved. Storing data D1 in the HMB 52 ensures the integrity of the data transferred from the host device 50 to the data storage device 100. In addition, since data D1 in the HMB 52 can be erased after the transfer of data D2 is completed, the size of the HMB 52 can be relatively small.

[0043] Figure 3 A flowchart showing a method for controlling a data storage device (e.g., data storage device 100) and a host device (e.g., host device 50) according to some embodiments of the present application in the write order is shown. The detailed steps are as follows:

[0044] Step 201: The data storage device 100 can receive data D1 from the host device 50. Data D1 can include data pages. In an alternative embodiment, data D1 can include a plurality of data pages. Data D1 can be received via the communication interface 111.

[0045] Step 203: The data storage device 100 can store data D1 in the buffer memory 113. Data D1 can be transferred from the communication interface 111 to the buffer memory 113.

[0046] Step 205: The data storage device 100 can transfer data D1 from the buffer memory 113 to the memory section 122 of the memory module 12. Data D1 can be transferred via the communication interface 112.

[0047] Step 207: The data storage device 100 can respond to the host device 50 with a signal after transferring data D1 from the buffer memory 113 to the memory section 122 of the memory module 12. The signal indicates that data D1 is written to the memory section 122. The signal can be transferred via the communication interface 111.

[0048] Step 209: The data storage device 100 may transfer the data D1 from the buffer memory 113 to the HMB 52 in the host device 50. The data D1 may be transferred via the communication interface 111.

[0049] Step 211: The data storage device 100 may receive the data D1 from the HMB 52. Additionally, if the data D1 in the HMB 52 is not available, the host device 50 may transfer a request for the data D1 to the data storage device 100.

[0050] Step 213: The data storage device 100 may store the data D2 in the buffer memory 114. The data D1 may correspond to at least a portion of the data D2. The data D2 may be generated by the microprocessor 115 by modifying the data D1 using, for example, an error correction code (ECC), parity check technology, or the like.

[0051] Step 215: The data storage device 100 may transfer the data D2 from the buffer memory 114 to the memory portion 123 of the memory module 12. The data D2 may be transferred via the communication interface 112.

[0052] Step 217: The host device 50 may erase the data D1 from the HMB 52 after the data D2 has been transferred to the memory portion 123. The data storage device 100 may generate an erase signal and transfer the erase signal to the host device 50 via the communication interface 111. The host device 50 may erase the data D1 from the HMB 52 in response to the erase signal. Additionally, the host device 50 may transfer an erase signal indicating the erase of the data D1 to the HMB 52 after the data D2 has been successfully written to the data storage device 100.

[0053] Those skilled in the art will understand from the above application that the order of the above steps may be adjusted, such as adjusting the order of the steps to be performed or adding one or more additional steps.

[0054] Figure 4 A schematic diagram showing the write order in the data storage device 200 and the host device (e.g., the host device 50) according to some embodiments of the present application. As discussed below, the operations related to Figure 4 the embodiments may be controlled by the microprocessor when the microprocessor 115 executes one or more codes of the program code 115c.

[0055] The data storage device 200 is similar to Figure 1 and Figure 2The data storage device 100, except that in addition to the memory controller 11, the data storage device 200 further includes an error correction unit 116. The error correction unit 116 can be coupled to the communication interface 111 and the buffer memory 114 via, for example, a bus. The data D1 can be transmitted from the HMB 52 to the error correction unit 116 via the communication interface 111 (S43'). The error correction unit 116 can be configured to generate the data D2 in response to the error correction of the data D1. The data D2 can be generated based on the error correction of the received plural data D1. The error correction unit 116 can be configured to transmit the data D2 to the buffer memory 114 (S44). The error correction of the data D1 can include ECC, parity check technology or the like. The error correction of the data D1 detects and corrects the corruption of n-bit data occurring in the memory to ensure data integrity. The error correction unit 116 can be a part of the microprocessor 115. The error correction unit 116 can be integrated into the microprocessor 115. In addition, the microprocessor 115 may be able to perform error correction when executing the program code 115c.

[0056] In some comparative embodiments, the stored data page can be directly copied from a memory portion to another memory portion in the memory module. However, the stored data page may contain bits that have flipped to an error state. The stored data page may be incorrect and the memory module may not be able to detect and correct the error. Therefore, the problem of blind copy may occur. In the present application, the data D1 has been detected, corrected, and then translated into the data D2. The present application ensures the integrity of the data from the host device 50 to the memory module 12.

[0057] Figure 5 A flowchart showing a method for controlling a data storage device (e.g., the data storage device 200) and a host device (e.g., the host device 50) in the write order according to some embodiments of the present application.

[0058] Figure 5 The flowchart of the method is similar to Figure 3 the flowchart of the method, except that Figure 5 the method further includes step 219. In step 219, the error correction unit 116 can generate the data D2 based on the error correction of the data D1.

[0059] Those skilled in the art will understand from the above application that the order of the above steps can be adjusted, such as adjusting the order of the steps to be executed or adding one or more additional steps.

[0060] Figure 6 A schematic diagram showing the read order in a data storage device (e.g., the data storage device 100 or 200) and a host device (e.g., the host device 50) according to some embodiments of the present application. As discussed below, compared withFigure 6 Operations related to the embodiments of Figure 6 can be controlled by the microprocessor when the microprocessor 115 executes one or more codes of the program code 115c.

[0061] As Figure 6 As shown in, the host device 50 can send a host device command requesting an access or read operation to the memory module 12 (R11). A read request associated with the data D2 from the host device 50 can be received through the communication interface 111. The communication interface 111 can be configured to transmit the read request to the microprocessor 115 (R12). The microprocessor 115 can be configured to send a memory operation command in response to the read request to detect whether the memory portion 123 of the memory module 12 has been completely written (R13 / R14). The memory module 12 can be configured to provide feedback on the status of the memory portion 123, where the data D2 is designated to be stored by the microprocessor 115 (F11 / F12). The microprocessor 115 can be configured to send a memory device command to access the memory module 12 in response to the status of the memory portion 123 (R21 / R22). If the memory portion 123 of the memory module 12 has not been completely written, the data D1 is transmitted from the memory portion 122 to the memory controller 11 through the communication interface 112 (F21 / F22 / F23). If the memory portion 123 of the memory portion 12m of the memory module 12 has been completely written, the data D2 can be transmitted from the memory portion 123 to the memory controller 11 through the communication interface 112 (F21' / F22 / F23). The microprocessor 115 can be configured to transmit the data D1 or the data D2 to the host device 50 through the communication interface 111 according to the status of the memory portion 123. Thus, when the memory portion 123 has not been completely written, the memory controller 11 can access the data D1 in the memory portion 122, so that the problem of open word lines (i.e., reading incomplete data pages) can be solved. When the memory portion 122 has received four SLC data blocks or the memory portion 123 has been completely written together with the data D2, the memory controller 11 can access the data D2. At the same time, the memory controller 11 can erase the data D1 in the memory portion 122.

[0062] Figure 7 A flowchart showing a method for controlling a data storage device (e.g., the data storage device 100 or the data storage device 200) and a host device (e.g., the host device 50) in a read order according to some embodiments of the present application.

[0063] Those skilled in the art will understand from the above application that the order of the above steps can be adjusted, such as adjusting the order of the steps to be executed or adding one or more additional steps. The detailed steps are as follows:

[0064] Step 401: The data storage device 100 may receive a read request associated with data D2 from the host device 50.

[0065] Step 403: The data storage device 100 may determine whether the memory portion 123 of the memory module 12 is fully written. If the memory portion 123 is fully written, the flow chart proceeds to step 405. If not fully written, the flow chart proceeds to step 407.

[0066] Step 405: The data storage device 100 may transfer data D2 from the memory portion 123 of the memory module 12 to the host device 50.

[0067] Step 407: The data storage device 100 may transfer data D1 from the memory portion 122 of the memory module 12 to the host device 50.

[0068] Those skilled in the art will understand from the above application that the order of the above steps may be adjusted, such as adjusting the order of the steps to be executed or adding one or more additional steps.

[0069] Figure 8 A schematic diagram showing the reading order in a data storage device (e.g., data storage device 100 or 200) and a host device (e.g., host device 50) according to some embodiments of the present application. As discussed below, operations related to Figure 8 the embodiments of may be controlled by the microprocessor when the microprocessor 115 executes one or more codes of the program code 116c.

[0070] As Figure 8 illustrated in, the host device 50 may send a host device command requesting an access or read operation to the memory module 12 (R11). A read request associated with data D2 from the host device 50 may be received via the communication interface. The communication interface 111 may be configured to transfer the read request to the microprocessor 115 (R12). The microprocessor 115 may be configured to send a memory operation command in response to the read request to detect whether the memory portion 123 of the memory module 12 is fully written (R13 / R14). The memory module 12 may be configured to provide feedback on the status of the memory portion 123, where data D2 is designated to be stored by the microprocessor 115 (F11 / F12). If the memory portion 123 of the memory module 12 is not fully written, the memory controller 11 may be configured to send an access request to the HMB 52 via the communication interface 111 (R31 / R32 / R33). Data D1 may be read from the HMB 52 for the host device 50 (F31).

[0071] Figure 9A flowchart showing a method for controlling a data storage device (e.g., data storage device 100 or data storage device 200) and a host device (e.g., host device 50) in reading order according to some embodiments of the present application.

[0072] Figure 9 The flowchart of the method is similar to Figure 8 the flowchart of the method, except that step 407 is replaced with step 409. In step 409, if the memory portion 123 is not fully written with data D2, the host device 50 may access the data D1 in the HMB 52 after receiving a request associated with data D2.

[0073] Those skilled in the art will understand from the above application that the order of the above steps can be adjusted, such as adjusting the order of the steps to be executed or adding one or more additional steps.

[0074] The present application can be further described using the following items:

[0075] 1. A method for controlling an internal storage device, the internal storage device comprising:

[0076] a flash memory controller having a first buffer memory and a second buffer memory; and

[0077] a flash memory module having at least a first memory portion and a second memory portion,

[0078] The method includes:

[0079] receiving first data from a host device;

[0080] storing the first data in the first buffer memory;

[0081] transferring the first data from the first buffer memory to the first memory portion of the flash memory module; and

[0082] transferring the first data from the first buffer memory to a host memory buffer in the host device,

[0083] wherein the first data corresponds to at least a part of second data to be written to the second memory portion.

[0084] 2. The method according to item 1, further comprising:

[0085] receiving first data from the HMB;

[0086] generating second data based on error correction of the first data;

[0087] storing the second data in the second buffer memory; and

[0088] Transfer the second data from the second buffer memory to the second memory portion of the flash memory module.

[0089] 3. The method as recited in item 2, wherein the second data is generated based on error correction of the received plurality of first data.

[0090] 4. The method as recited in item 2, wherein the transfer rate of the first data from the first buffer memory to the first memory portion is greater than the transfer rate of the second data from the second buffer memory to the second memory portion.

[0091] 5. The method as recited in item 2, further comprising:

[0092] After the second data is transferred to the second memory portion, erase the first data from the host memory buffer.

[0093] 6. The method as recited in item 1, further comprising:

[0094] Receive a read request associated with the second data from the host device; and

[0095] If the second memory portion of the flash memory module is fully written, transfer the second data from the second memory portion to the host device;

[0096] If the second memory portion of the flash memory module is not fully written, transfer the first data from the first memory portion of the flash memory module to the host device.

[0097] 7. The method as recited in item 3, wherein the first data includes data pages, and the second data includes a plurality of data pages.

[0098] 8. The method as recited in item 1, further comprising:

[0099] After the first data is transferred from the first buffer memory to the first memory portion of the flash memory module, respond to the host device with a first signal,

[0100] wherein the first signal indicates that the first data is written to the first memory portion.

[0101] 9. The method as recited in item 1, wherein the first memory portion has a first operation mode, and the second memory portion has a second operation mode, wherein the first operation mode is different from the second operation mode.

[0102] 10. The method as recited in item 9, wherein the first memory portion includes quad-level cells (QLC) or single-level cells, and the second memory portion includes QLC.

[0103] 11. A flash memory controller for controlling a flash memory module having at least a first memory portion and a second memory portion, the flash memory controller comprising:

[0104] A first communication interface configured to receive first data from a host device;

[0105] A first buffer memory coupled to the first communication interface and configured to store the first data;

[0106] A second communication interface configured to transfer the first data from the first buffer memory to a first memory portion of a flash memory module;

[0107] wherein the first communication interface is further configured to transfer the first data from the first buffer memory to a host memory buffer of the host device; and

[0108] wherein the first data corresponds to at least a portion of second data to be written to a second memory portion.

[0109] 12. The flash memory controller of item 11, further comprising:

[0110] An error correction unit coupled to the first communication interface, wherein the first data is transferred from the host memory buffer to the error correction unit via the first communication interface, and wherein the error correction unit is configured to generate second data in response to error correction of the first data; and

[0111] A second buffer memory coupled to the error correction unit and the second communication interface, wherein the second buffer memory is configured to store the second data,

[0112] wherein the second communication interface is further configured to transfer the second data from the second buffer memory to a second memory portion of the flash memory module.

[0113] 13. The flash memory controller of item 12, wherein the second data is generated based on error correction of a plurality of received first data.

[0114] 14. The flash memory controller of item 12, wherein a transfer rate of the first data from the first buffer memory to the first memory portion is greater than a transfer rate of the second data from the second buffer memory to the second memory portion.

[0115] 15. The flash memory controller of item 12, wherein the first communication interface is further configured to transfer an erase signal indicating erasure of the first data to the host memory buffer after the second data has been transferred to the second memory portion.

[0116] 16. The flash memory controller of item 11, wherein after receiving a read request associated with the second data from the host device by the first communication interface:

[0117] if the second memory portion of the flash memory module is fully written, the second data is transferred from the second memory portion to the host device;

[0118] If the second memory portion of the flash memory module is not fully written, the first data is transmitted from the first memory portion to the host device via the second communication interface.

[0119] 17. The flash memory controller as recited in item 11, wherein the first data includes data pages, and the second data includes a plurality of data pages.

[0120] 18. The flash memory controller as recited in item 11, wherein

[0121] After the first data is transmitted from the first buffer memory to the first memory portion of the flash memory module, a first signal is transmitted to the host device via the first communication interface,

[0122] wherein the first signal indicates that the first data is written to the first memory portion.

[0123] 19. The flash memory controller as recited in item 1, wherein the first memory portion has a first operation mode, and the second memory portion has a second operation mode, wherein the first operation mode is different from the second operation mode.

[0124] 20. The flash memory controller as recited in item 19, wherein the first memory portion includes QLC or SLC, and the second memory portion includes QLC.

[0125] 21. The flash memory controller as recited in item 11, wherein the first communication interface is a Non-Volatile Memory Express (NVMe) interface.

[0126] 22. The flash memory controller as recited in item 12, wherein the second communication interface is a flash interface.

[0127] 23. A data storage device, comprising:

[0128] A flash memory module having at least a first memory portion and a second memory portion;

[0129] A flash memory controller coupled to the flash memory module, the flash memory controller comprising:

[0130] A first communication interface configured to receive first data from a host device,

[0131] A first buffer memory coupled to the first communication interface and configured to store the first data, and

[0132] A second communication interface configured to transmit the first data from the first buffer memory to the first memory portion of the flash memory module;

[0133] wherein the first communication interface is further configured to transmit the first data from the first buffer memory to a host memory buffer of the host device,

[0134] wherein the first data corresponds to at least a portion of the second data to be written to the second memory portion.

[0135] 24. The data storage device as recited in item 23, wherein the flash memory controller further comprises:

[0136] an error correction unit coupled to the first communication interface, wherein the first data is transmitted from the host memory buffer to the error correction unit via the first communication interface, and wherein the error correction unit is configured to generate the second data in response to error correction of the first data; and

[0137] a second buffer memory coupled to the error correction unit and the second communication interface, wherein the second buffer memory is configured to store the second data,

[0138] wherein the second communication interface is further configured to transmit the second data from the second buffer memory to the second memory portion of the flash memory module.

[0139] 25. The data storage device as recited in item 24, wherein the second data is generated based on error correction of a plurality of received first data.

[0140] 26. The data storage device as recited in item 24, wherein the transmission rate of the first data from the first buffer memory to the first memory portion is greater than the transmission rate of the second data from the second buffer memory to the second memory portion.

[0141] 27. The data storage device as recited in item 24, wherein the first communication interface is further configured to transmit an erase signal indicating erasure of the first data to the host memory buffer after the second data has been transmitted to the second memory portion.

[0142] 28. The data storage device as recited in item 23, wherein after receiving a read request associated with the second data from a host device via the first communication interface:

[0143] if the second memory portion of the flash memory module is fully written, the second data is transmitted from the second memory portion to the host device;

[0144] if the second memory portion of the flash memory module is not fully written, the first data is transmitted from the first memory portion to the host device.

[0145] 29. The data storage device as recited in item 23, wherein the first data includes data pages, and the second data includes a plurality of data pages.

[0146] 30. The data storage device as recited in item 23, wherein

[0147] After the first data is transferred from the first buffer memory to the first memory section of the flash memory module, a first signal is transmitted via a first communication interface to the host device,

[0148] wherein the first signal indicates that the first data is written to the first memory section.

[0149] 31. The data storage device according to item 23, wherein the first memory section has a first operation mode, and the second memory section has a second operation mode, wherein the first operation mode is different from the second operation mode.

[0150] 32. The data storage device according to item 31, wherein the first memory section includes QLC or SLC, and the second memory section includes QLC.

[0151] 33. The data storage device according to item 23, wherein the first communication interface is a Non-Volatile Memory Express (NVMe) interface.

[0152] 34. The data storage device according to item 23, wherein the second communication interface is a flash interface.

[0153] 35. A method for controlling a host device, comprising:

[0154] transmitting first data to a data storage device via a first communication interface;

[0155] receiving the first data from the data storage device via the first communication interface; and

[0156] storing the received first data in a host memory buffer,

[0157] wherein the first data corresponds to at least a part of second data to be written to the data storage device.

[0158] 36. The method according to item 35, further comprising transmitting an erase signal indicating the erase of the first data to the host memory buffer after the second data is successfully written to the data storage device.

[0159] 37. The method according to item 35, further comprising accessing the first data in the host memory buffer after receiving a request associated with the second data if the second data is not fully written.

[0160] 38. The method according to item 37, further comprising transmitting a request for the first data to the data storage device if the first data in the host memory buffer is not available.

[0161] It should be noted that the above disclosure is for illustrative purposes and should not be construed as limiting the present application. Those skilled in the art will readily observe that many modifications and variations of the apparatus and method can be made while retaining the teachings of the present application. Accordingly, the above disclosure should be interpreted as being limited only by the boundaries and scope of the appended claims for patent.

Claims

1. A method for controlling an internal storage device, the internal storage device comprising: a flash memory controller having a first buffer memory and a second buffer memory; and a flash memory module having at least a first memory portion and a second memory portion, the method comprising: receiving first data from a host device; storing the first data in the first buffer memory; transferring the first data from the first buffer memory to the first memory portion of the flash memory module; transferring the first data from the first buffer memory to a host memory buffer in the host device; receiving the first data from the host memory buffer; generating second data based on error correction or parity check techniques of the first data; storing the second data in the second buffer memory; and transferring the second data from the second buffer memory to the second memory portion of the flash memory module, wherein the first data corresponds to at least a portion of the second data to be written to the second memory portion; receiving a read request associated with the second data from the host device; and if the second memory portion of the flash memory module is fully written, transferring the second data from the second memory portion to the host device; if the second memory portion of the flash memory module is not fully written, transferring the first data from the first memory portion of the flash memory module to the host device.

2. The method according to claim 1, wherein the second data is generated based on error correction of a plurality of received first data.

3. The method according to claim 1, wherein the transfer rate of the first data from the first buffer memory to the first memory portion is greater than the transfer rate of the second data from the second buffer memory to the second memory portion.

4. The method according to claim 1, further comprising: erasing the first data from the host memory buffer after the second data is transferred to the second memory portion.

5. The method according to claim 1, wherein the first data comprises data pages, and the second data comprises a plurality of data pages.

6. The method according to claim 1, further comprising: responding to the host device with a first signal after the first data is transferred from the first buffer memory to the first memory portion of the flash memory module, wherein the first signal indicates that the first data is written to the first memory portion.

7. The method according to claim 1, wherein the first memory portion has a first operation mode, and the second memory portion has a second operation mode, wherein the first operation mode is different from the second operation mode.

8. The method according to claim 7, wherein the first memory portion comprises four-level cells or single-level cells, and the second memory portion comprises four-level cells.

9. A flash memory controller for controlling a flash memory module having at least a first memory portion and a second memory portion, the flash memory controller comprising: A first communication interface configured to receive first data from a host device; A first buffer memory coupled to the first communication interface and configured to store the first data; A second communication interface configured to transfer the first data from the first buffer memory to the first memory portion of the flash memory module; Wherein the first communication interface is further configured to transfer the first data from the first buffer memory to a host memory buffer of the host device; An error correction unit coupled to the first communication interface, wherein the first data is transferred from the host memory buffer to the error correction unit via the first communication interface, and wherein the error correction unit is configured to generate second data in response to error correction or parity check techniques of the first data; And A second buffer memory coupled to the error correction unit and the second communication interface, wherein the second buffer memory is configured to store the second data, Wherein the second communication interface is further configured to transfer the second data from the second buffer memory to the second memory portion of the flash memory module, Wherein the first data corresponds to at least a portion of the second data to be written to the second memory portion; and Wherein after receiving a read request associated with the second data from the host device by the first communication interface: If the second memory portion of the flash memory module is fully written, the second data is transferred from the second memory portion to the host device; If the second memory portion of the flash memory module is not fully written, the first data is transferred from the first memory portion to the host device via the second communication interface.

10. The flash memory controller according to claim 9, wherein the second data is generated based on error correction of a plurality of received first data.

11. The flash memory controller according to claim 9, wherein a transfer rate of the first data from the first buffer memory to the first memory portion is greater than a transfer rate of the second data from the second buffer memory to the second memory portion.

12. The flash memory controller according to claim 9, wherein the first communication interface is further configured to transfer an erase signal indicating erasure of the first data to the host memory buffer after the second data is transferred to the second memory portion.

13. The flash memory controller according to claim 9, wherein the first data includes a data page, and the second data includes a plurality of data pages.

14. The flash memory controller according to claim 9, wherein After the first data is transferred from the first buffer memory to the first memory portion of the flash memory module, a first signal is transferred to the host device via the first communication interface, Wherein the first signal indicates writing the first data into the first memory portion.

15. The flash memory controller according to claim 9, wherein the first memory portion has a first operation mode, and the second memory portion has a second operation mode, wherein the first operation mode is different from the second operation mode.

16. The flash memory controller according to claim 15, wherein the first memory portion includes four-bit rank cells or single-bit cells, and the second memory portion includes four-bit rank cells.

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