Cache Media Management

Abstract

Identify an exempt portion of a data cache of a memory subsystem. The exempt portion includes a first set of data blocks including first data written by a host system to the data cache. Identify a collected portion of the data cache of the memory subsystem. The collected portion includes a second set of data blocks including second data written by the host system. Perform a media management operation on the collected portion of the data cache to relocate the second data to a storage region of the memory subsystem having a higher data density than the data cache, wherein the exempt portion of the data cache is exempted from the media management operation.

Description

Technical Field

[0001] Embodiments of the present disclosure generally relate to memory subsystems, and more particularly, to cache media management of memory subsystems. Background Art

[0002] A memory subsystem may include one or more memory devices that store data. The memory devices can be, for example, non-volatile memory devices and volatile memory devices. Generally, a host system can utilize the memory subsystem to store data at and retrieve data from the memory devices. Brief Description of the Drawings

[0003] The present disclosure will be more fully understood from the following detailed description and the accompanying drawings of various embodiments of the present disclosure.

[0004] Figure 1 Illustrate an example computing system that includes a memory subsystem in accordance with some embodiments of the present disclosure.

[0005] Figure 2 Illustrate an example cache management component that controls media management operations associated with a memory subsystem in accordance with some embodiments of the present disclosure.

[0006] Figure 3 Is a graph in accordance with some embodiments of the present disclosure that illustrates example data related to write amplification and the percentage of host data overwritten in a data cache as a function of the size of an exempt portion of the data cache.

[0007] Figure 4 Is a flowchart of another example method for managing media management operations associated with a data cache of a memory subsystem in accordance with some embodiments of the present disclosure.

[0008] Figure 5 Illustrate an example cache management component that controls media management operations associated with a memory subsystem in accordance with some embodiments of the present disclosure.

[0009] Figure 6 Is a flowchart of another example method for managing media management operations associated with a data cache of a memory subsystem in accordance with some embodiments of the present disclosure.

[0010] Figure 7 Is a block diagram of an example computer system in which embodiments of the present disclosure may operate. Detailed Description

[0011] Aspects of the present disclosure relate to cache media management of memory subsystems. A memory subsystem can be a storage device, a memory module, or a combination of a storage device and a memory module. The following is combined withFigure 1 Describes examples of storage devices and memory modules. Generally, a host system can utilize a memory subsystem that includes one or more components, such as a memory device that stores data. The host system can provide data to be stored at the memory subsystem and can request data to be retrieved from the memory subsystem.

[0012] The memory device can be a non-volatile memory device. The non-volatile memory device is a package of one or more dies. Each die can be composed of one or more planes. For some types of non-volatile memory devices (e.g., "NAND" (Negative-AND) devices), each plane consists of a set of physical blocks. Each block consists of a set of pages. Each page consists of a set of memory cells that store data bits. For some memory devices, such as NAND devices, a block is the smallest erasable area, and pages within a block cannot be erased individually. For such devices, an erase operation is performed one block at a time.

[0013] The pages of a block can contain valid data, invalid data, or no data. Invalid data is data that is marked as obsolete because a new version of the data is stored on the memory device. Invalid data includes data that was previously written but is no longer associated with a valid logical address (e.g., the logical address that the host system references in a physical-to-logical (P2L) mapping table). Valid data is the most recent version of such data that is being stored on the memory device. The memory subsystem can mark data as invalid based on information received, for example, from the operating system. Pages that do not contain data contain pages that have been previously erased and have not yet been written to.

[0014] The memory subsystem controller can perform operations for media management algorithms, such as wear leveling, refreshing, garbage collection, erasing, etc. A block can have some pages that contain valid data and some pages that contain invalid data. To avoid waiting for all pages in a block to have invalid data in order to erase and reuse the block, an algorithm hereinafter referred to as "garbage collection" can be invoked to allow the block to be erased and released as a free block for subsequent write operations. Garbage collection is a set of media management operations that includes, for example: selecting a block that contains both valid and invalid data; selecting the pages in the block that contain valid data; copying the valid data to a new location (e.g., a free page in another block); marking the data in the previously selected pages as invalid; and erasing the selected block.

[0015] The following "garbage collection" or "garbage collection operation" refers to selecting a block; rewriting the valid data from the selected block to another block; and erasing all the invalid data and valid data stored at the selected block. The valid data from multiple selected blocks can be copied to a smaller number of other blocks, and the selected blocks can then be erased. Thus, the number of erased blocks can be increased so that more blocks can be available for storing subsequent data from the host system.

[0016] A memory subsystem may include multiple memory devices having one or more arrays of memory cells, such as a low-density storage device having single-level cells (SLCs) or a high-density storage device having multi-level cells (MLCs), triple-level cells (TLCs), or quad-level cells (QLCs). A host system may write data to low-density storage locations of the memory subsystem (e.g., a static SLC cache), which include multiple reserved data blocks (e.g., having a cache size of approximately 6GB) that are typically configured to store host data on a first-in, first-out basis.

[0017] The memory subsystem may implement a garbage collection operation to maintain or produce a continuous supply of free data blocks for host applications to store data. Garbage collection includes the operation of copying valid data from one data block to another. The source data block (e.g., the data block from which valid data is copied) may then be erased and released as a free block for subsequent host writes. This additional rewriting of valid data in a data block during a garbage collection operation causes write amplification. Write amplification may shorten the operational life and affect the performance of the memory subsystem. The memory subsystem may include some amount of additional blocks that exceed the logical size of the memory device exposed as user space. This additional memory space is commonly referred to as over-provisioning (OP). The efficiency of the garbage collection operation may generally vary with the over-provisioning of the memory subsystem. During garbage collection, the additional space from over-provisioning helps reduce write amplification. A larger amount of over-provisioning may reduce write amplification by reducing the number of times garbage collection rewrites valid data within the memory subsystem to free up data blocks.

[0018] Conventionally, during host idle time, a garbage collection operation may be performed to relocate all host data stored in a static SLC cache to a high-density, high-capacity storage device called an XLC (e.g., MLC / TLC / QLC) storage area (e.g., having a storage size of 256GB). The garbage collection operation includes the process of relocating data from one or more source data blocks (e.g., the static SLC cache) to new destination data blocks (e.g., the XLC storage device), with the intended purpose of data consolidation to free up the storage resources of the static SLC cache for subsequent erase and new write processes. During the execution of the garbage collection operation, host data may be copied from one or more NAND locations corresponding to the static SLC cache to another NAND location corresponding to the XLC storage device. Generally, folding is performed to consolidate valid data together (e.g., garbage collection) to free up more space for new writes.

[0019] Relocating valid host data from a static SLC cache to an XLC block causes write amplification on the XLC block. Write amplification (WA) can be represented by the product of the actual data written by the memory subsystem and the logical amount of write data sent from the host system to the memory subsystem.

[0020] Conventional memory subsystems are configured to manage a static SLC cache by relocating or recycling the entire static SLC cache to an XLC block during host idle time. However, performing a garbage collection operation to relocate the entire static SLC cache to an XLC block during idle time may impede the performance of the memory subsystem and reduce the endurance of the XLC memory to which the data is rewritten. For example, garbage collection also involves additional writes by rewriting data from the static SLC cache to an XLC storage area. Performing the additional writes may reduce the bandwidth of the memory subsystem due to consumption of resources (e.g., processing and / or memory). Also, the more writes performed on the memory device (e.g., write amplification), the faster the memory device degrades.

[0021] According to conventional memory subsystems, garbage collecting host data that has been repeatedly and frequently overwritten within a recent time frame may cause the data to be relocated to a high-density storage area that subsequently fails (e.g., the overwritten data). Thus, there are unnecessary costs associated with garbage collecting data that will later fail (be overwritten) to an XLC block. Thus, garbage collection of the entire static SLC cache results in wasted garbage collection activity and unnecessary programming / erase (P / E) cycle overhead, and increases endurance requirements.

[0022] Aspects of the present disclosure address the above and other deficiencies by exempting a portion of the static SLC data from the garbage collection process. The exempted portion of the SLC cache may include a portion of the most recently written data (e.g., newer data) of the SLC cache. In an embodiment, the exempted portion of the static SLC cache data may be identified by a sequence identifier or version number associated with the data. In an embodiment, by exempting newer SLC cache data from the garbage collection process, the newer data that is more easily overwritten by the host system can be maintained in the SLC cache and not garbage collected for storage in the XLC storage area. The collected or non-exempted portion includes the older data of the SLC cache that is subject to the garbage collection operation. According to an embodiment, the size of the exempted portion of the SLC cache may be fixed based on calibration of the overwrite rate relative to the SLC exempted portion size. In another embodiment, the exempted portion size may be dynamically determined and adjusted based on changing workload conditions associated with the host system.

[0023] Advantageously, the management of garbage collection operations as described herein reduces the media management (e.g., garbage collection) effort associated with moving host data from a static SLC cache to an XLC block. The reduced media management effort (e.g., collection of the collected portion rather than the exempt portion) according to embodiments of the present disclosure results in less valid host data being relocated to the XLC block in the SLC cache, thereby reducing the XLC durability requirements and improving XLC write performance. Limiting the performance of garbage collection operations to certain scenarios can improve the durability of the memory device.

[0024] Figure 1 Illustrate an example computing system 100 that includes a memory subsystem 110 according to some embodiments of the present disclosure. The memory subsystem 110 may include media such as one or more volatile memory devices (e.g., memory device 140), one or more non-volatile memory devices (e.g., memory device 130), or a combination of such media.

[0025] The memory subsystem 110 can be a storage device, a memory module, or a hybrid of a storage device and a memory module. Examples of storage devices include solid state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controllers (eMMCs), universal flash storage (UFS) drives, secure digital (SD) cards, and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small DIMMs (SO-DIMMs), and various types of non-volatile dual in-line memory modules (NVDIMMs).

[0026] The computing system 100 can be a computing device such as a desktop computer, a laptop computer, a network server, a mobile device, a vehicle (e.g., an airplane, a drone, a train, an automobile, or other transportation vehicle), an Internet of Things (IoT)-enabled device, an embedded computer (e.g., a computer included in a vehicle, industrial equipment, or a networked commercial device), or such a computing device that includes memory and a processing device.

[0027] The computing system 100 can include a host system 120 coupled to one or more memory subsystems 110. In some embodiments, the host system 120 is coupled to different types of memory subsystems 110. Figure 1 Illustrate an example of a host system 120 coupled to one memory subsystem 110. As used herein, "coupled to" or "coupled with" generally refers to a connection between components, which can be an indirect communication connection or a direct communication connection (e.g., without an intermediate component or device), whether wired or wireless, including connections such as electrical, optical, magnetic, etc.

[0028] The host system 120 may include a processor chipset and a software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more caches, a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller). The host system 120 uses the memory subsystem 110 to write data to and read data from the memory subsystem 110, for example.

[0029] The host system 120 may be coupled to the memory subsystem 110 via a physical host interface. Examples of the physical host interface include but are not limited to a Serial Advanced Technology Attachment (SATA) interface, a Peripheral Component Interconnect Express (PCIe) interface, a Universal Serial Bus (USB) interface, Fibre Channel, Serial Attached SCSI (SAS), Small Computer System Interface (SCSI), a Double Data Rate (DDR) memory bus, a Dual In-line Memory Module (DIMM) interface (e.g., a DIMM socket interface that supports Double Data Rate (DDR)), an Open NAND Flash Interface (ONFI), Double Data Rate (DDR), Low Power Double Data Rate (LPDDR), or any other interface. The physical host interface can be used to transfer data between the host system 120 and the memory subsystem 110. When the memory subsystem 110 is coupled to the host system 120 via a PCIe interface, the host system 120 may further utilize a Non-Volatile Memory Express (NVMe) interface to access components (e.g., the memory device 130). The physical host interface may provide an interface for passing control, address, data, and other signals between the memory subsystem 110 and the host system 120. Figure 1 The memory subsystem 110 is described as an example. In general, the host system 120 may access multiple memory subsystems via the same communication connection, multiple separate communication connections, and / or a combination of communication connections.

[0030] The memory devices 130, 140 may include any combination of different types of non-volatile memory devices and / or volatile memory devices. The volatile memory device (e.g., the memory device 140) may be, but is not limited to, a random access memory (RAM), such as a dynamic random access memory (DRAM) and a synchronous dynamic random access memory (SDRAM).

[0031] Some examples of non-volatile memory devices (e.g., memory device 130) include NAND type flash memories and write-in-place memories, such as three-dimensional cross-point (“3D cross-point”) memory devices, which are cross-point arrays of non-volatile memory cells. The cross-point array of non-volatile memory can perform bit storage based on the change of bulk resistance in combination with a stackable cross-gridded data access array. Additionally, compared with many flash-based memories, cross-point non-volatile memory can perform write-in-place operations, in which non-volatile memory cells can be programmed without pre-erasing the non-volatile memory cells. NAND type flash memories include, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0032] Each of the memory devices 130 may include one or more memory cell arrays. One type of memory cell, such as a single-level cell (SLC), can store one bit per cell. Other types of memory cells, such as multi-level cells (MLC), three-level cells (TLC), and quad-level cells (QLC), can store multiple bits per cell. In some embodiments, each of the memory devices 130 may include one or more memory cell arrays, such as SLC, MLC, TLC, QLC, or any combination thereof. In some embodiments, a particular memory device may include an SLC portion of memory cells, as well as an MLC portion, a TLC portion, or a QLC portion. The memory cells of the memory device 130 can be grouped into pages, which may refer to the logical units of the memory device for storing data. For some types of memories (e.g., NAND), pages can be grouped to form blocks.

[0033] Although non-volatile memory devices such as NAND type memories (e.g., 2D NAND, 3D NAND) and 3D cross-point arrays of non-volatile memory cells are described, the memory device 130 can be based on any other type of non-volatile memory, such as read-only memory (ROM), phase change memory (PCM), select-in-memory, other chalcogenide-based memories, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin transfer torque (STT)-MRAM, conductive-bridge RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), NOR flash memory, and electrically erasable programmable read-only memory (EEPROM).

[0034] The memory subsystem controller 115 (or controller 115 for simplicity) can communicate with the memory device 130 to perform operations such as reading data, writing data, or erasing data at the memory device 130 and other such operations (e.g., in response to commands dispatched by the controller 116 on the command bus). The memory subsystem controller 115 can include hardware such as one or more integrated circuits and / or discrete components, buffer memory, or a combination thereof. The hardware can include digital circuitry with dedicated (i.e., hard-wired) logic to perform the operations described herein. The memory subsystem controller 115 can be a microcontroller, dedicated logic circuitry (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), etc.), or other suitable processor.

[0035] The memory subsystem controller 115 can include a processing device 117 (processor) configured to execute instructions stored in the local memory 119. In the illustrated example, the local memory 119 of the memory subsystem controller 115 includes an embedded memory configured to store instructions for performing various processes, operations, logic flows, and routines that control the operation of the memory subsystem 110 (including handling communication between the memory subsystem 110 and the host system 120).

[0036] In some embodiments, the local memory 119 can include memory registers that store memory pointers, fetched data, etc. The local memory 119 can also include a read only memory (ROM) for storing microcode. Although Figure 1 the illustrated example memory subsystem 110 has been shown as including the memory subsystem controller 115, in another embodiment of the present disclosure, the memory subsystem 110 does not include the memory subsystem controller 115 and can instead rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory subsystem).

[0037] Typically, the memory subsystem controller 115 may receive commands or operations from the host system 120 and may convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory device 130 and / or the memory device 140. The memory subsystem controller 115 may be responsible for other operations such as wear leveling operations, garbage collection operations, error detection and error correction code (ECC) operations, encryption operations, cache operations, and address translation between logical addresses (e.g., logical block addresses (LBAs), namespaces) associated with the memory device 130 and physical addresses (e.g., physical block addresses). The memory subsystem controller 115 may further include host interface circuitry to communicate with the host system 120 via a physical host interface. The host interface circuitry may convert commands received from the host system into commands to access the memory device 130 and / or the memory device 140, and convert responses associated with the memory device 130 and / or the memory device 140 into information for the host system 120.

[0038] In some embodiments, the memory subsystem 110 may use a striping scheme, according to which each data payload (e.g., user data) utilizes multiple dies of the memory device 130 (e.g., a NAND type flash memory device) such that the payload is distributed across a subset of the dies, while the remaining one or more dies are used to store error correction information (e.g., parity bits). Thus, a set of blocks distributed across a set of dies of a memory device using a striping scheme is referred to herein as a "superblock".

[0039] The memory subsystem 110 may also include additional circuitry or components not shown. In some embodiments, the memory subsystem 110 may include a cache or buffer (e.g., DRAM) and address circuitry (e.g., a row decoder and a column decoder) that may receive an address from the memory subsystem controller 115 and decode the address to access the memory device 130.

[0040] In some embodiments, the memory device 130 includes a local media controller 135 that operates in conjunction with the memory subsystem controller 115 to perform operations on one or more memory cells of the memory device 130. An external controller (e.g., the memory subsystem controller 115) may manage the memory device 130 externally (e.g., perform media management operations on the memory device 130). In some embodiments, the memory device 130 is a managed memory device that is an original memory device combined with a local controller (e.g., the local media controller 135) that performs media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device.

[0041] Memory subsystem 110 includes a cache management component 113 that may perform media management operations, such as garbage collection operations, on a first portion (i.e., the collected portion) of the data in the static SLC cache, while a second portion of the data in the static SLC cache is exempt from media management (e.g., garbage collection) (i.e., the exempt portion). In some embodiments, the controller 115 includes at least a portion of the cache management component 113. For example, the controller 115 may include a processor 117 (processing device) configured to execute instructions stored in local memory 119 to perform the operations described herein. In some embodiments, the cache management component 113 is part of the host system 120, an application, or an operating system.

[0042] The cache management component 113 may identify a first portion of the first-in-first-out SLC cache as the portion subject to media management operations (e.g., garbage collection operations). Garbage collection operations are described below as an example of media management operations. The cache management component 113 further identifies a second portion of the SLC cache that is exempt from garbage collection operations. The first portion (i.e., the "collected portion") contains older data in the SLC cache. The second portion (i.e., the "exempt portion") contains newer data in the SLC cache that is not subject to garbage collection operations. Exempting relatively newer data in the SLC cache from garbage collection operations (e.g., data recently sent by the host system to the SLC cache storage device, as identified by a corresponding sequence identifier or version number) avoids unnecessary relocation of host data to the XLC storage device because the probability that the newer data will be overwritten by the host system in a subsequent recent time period may be high.

[0043] Delaying garbage collection of recently written host data stored in the exempt portion reduces the amount of valid data garbage collected into XLC blocks. The cache management component 113 performs garbage collection operations on a smaller data set (i.e., the collected portion) of the SLC cache, thereby reducing the XLC durability requirements.

[0044] In addition, in an embodiment, the cache management component 113 may dynamically determine the size of the exempt portion. For example, the cache management component 113 may adjust the size of the exempt portion of the SLC cache based on one or more parameters or metrics associated with the memory subsystem 110 (e.g., a workload metric associated with the host system).

[0045] Figure 2 An example cache management component 213 that controls garbage collection operations associated with the static SLC cache 230 of a memory subsystem according to some embodiments of the present disclosure is described. As Figure 2As shown, the host system 220 writes host data to the static SLC cache 230 for storage in associated data blocks. In an embodiment, a garbage collection operation is performed in the background to collect or relocate host data from the static SLC cache 230 to the XLC storage area 240 during host idle time. In an embodiment, if an inactive time period is reached (e.g., the host system 220 has no read or write activity), the idle state of the host system may be identified.

[0046] In an embodiment, as Figure 2 shown, the static SLC cache 230 is configured in a first-in, first-out arrangement, where newer host data is stored in a first set of one or more designated blocks (e.g., the topmost block as Figure 2 shown). In an embodiment, each write from the host system 220 is associated with information identifying the relative time of the corresponding write operation. For example, each write operation may be identified by a sequence identifier or version number. Each successive write operation may be identified by an incremented sequence identifier or version number. In an embodiment, the host data stored in the static SLC cache 230 may have an associated time (e.g., the time at which the corresponding host data was written to the static SLC cache), such that the most recently written static SLC data can be identified.

[0047] In an embodiment, the cache management component 213 performs a garbage collection operation that collects data from a first portion (the collected portion 234) of the static SLC cache 230 while exempting a second portion (the exempt portion 232) of the static SLC cache 230 from the garbage collection process. In Figure 2 the embodiment shown, the portion of the static SLC cache 230 that is exempt from the garbage collection process has a fixed size and includes one or more blocks of the SLC cache 230 designated for storing the most recently written static SLC data (e.g., a portion of the newer data) and is referred to as the exempt portion 232. In an embodiment, the size of the exempt portion 232 may be defined by: storage amount (e.g., 512 MB, 1 GB, etc.), the number of blocks of the SLC cache 230 (e.g., two blocks, two and a half blocks, three blocks, etc.), a percentage of the total size of the SLC cache 230, or other metric.

[0048] As Figure 2As shown, the cache management component 213 performs a garbage collection operation to garbage collect data of the collected portion 234 from the static SLC cache 230. The collected data 250 is relocated to the XLC storage area 240, while the data stored in the exempt portion 232 remains in the static SLC cache 230. In an embodiment, host data covered by the host system 220 during a recent time period is saved in the static SLC cache 230. Delaying the garbage collection of this most recently written host data (e.g., until collection during a subsequent garbage collection operation) reduces or minimizes the garbage collection of valid data to the XLC storage area 240. Advantageously, the reduced garbage collection performed by the cache management component 213 reduces the durability requirements of the XLC storage area.

[0049] In an embodiment, considering the amount of host data covered in the static SLC cache and the write amplification of the XLC storage area, the size of the fixed exempt portion 232 is selected to optimize the size of the collected portion 234.

[0050] Figure 3 is a graph 300 according to some embodiments of the present disclosure, which illustrates example data of XLC write amplification 301, and the percentage of host data covered in the static SLC cache 302 as a function of the size of the exempt portion of the static SLC cache 332. In an embodiment, the size of the fixed exempt portion can be optimized considering the amount of collected data (e.g., data 250 collected from Figure 2 the collected portion 234) such that there is sufficient level of SLC cache available for use or release after the garbage collection operation and before subsequent host write activity. In an embodiment, the size of the exempt portion 232 can represent a relatively small portion of the static SLC cache that is not subject to the garbage collection operation, while having a suitable size of the collected portion 234 capable of storing data for subsequent write operations from the host system. Advantageously, establishing the exempt portion 232 can reduce the XLC durability requirements by 20% to 30%.

[0051] In an embodiment, considering setting a sufficient amount of the collected portion of the SLC cache to free up space for data of the next set of write operations, the size of the fixed exempt portion (e.g., Figure 2 the exempt portion 232) can be selected based on the optimization of: the XLC write amplification 301 as a function of the size of the static cache exempt portion (represented by line 301A in Figure 3 ), and the amount of host data covered in the static SLC cache 302 as a function of the size of the static cache exempt portion (represented by Figure 3The line 302A in (is shown). For example, as shown in the graph 300, at a static cache exemption section size of 512 MB, approximately 40% of the host data is identified as being overwritten in the static cache (as shown by point 303) at a write amplification level of approximately 1.45 (as shown by point 304).

[0052] In this example, setting Figure 2 the size of the exemption section 232 in such that due to the garbage collection operation, approximately 60% of the write terabytes (TBW) of the host system are relocated to the XLC storage area 240. As Figure 3 shown, setting a larger static cache exemption section size results in a larger percentage of the host data being overwritten in the static SLC cache and a smaller XLC WA, which reduces the XLC durability requirements.

[0053] In an example, with a fixed static cache exemption section size of 512 MB established, the XLC WA is shown to decrease from 1.74 to 1.45 (e.g., the XLC durability budget is reduced by approximately 18%). In another example, with a fixed static cache exemption section size of 1 GB established, the XLC WA is reduced to 1.3, saving approximately 25% of the XLC durability. It is shown to decrease from 1.74 to 1.45 (e.g., the XLC durability budget is reduced by approximately 18%).

[0054] Figure 4 is a flowchart of an example method 400 in accordance with some embodiments of the present disclosure, the method for identifying a first portion of data blocks in a cache of a memory subsystem to be exempt from garbage collection operations performed on the remaining portion of the cache. Method 400 may be executed by processing logic that may include hardware (e.g., a processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executing on a processing device), or a combination thereof. In some embodiments, method 400 is performed by Figure 1 the cache management component 113 of. Although shown in a particular sequence or order, the order of the process may be modified unless otherwise specified. Accordingly, the illustrated embodiments should be understood only as examples, and the illustrated process may be performed in a different order, and some processes may be performed in parallel. Additionally, one or more processes may be omitted in various embodiments. Thus, not all processes are required in every embodiment. Other process flows are possible.

[0055] At operation 410, the processing device identifies an exempt portion of the data cache of the memory subsystem, where the exempt portion includes a first set of data blocks storing first data written by the host system to the data cache. In an embodiment, the data cache is a low-density storage region, such as a static SLC data cache. The first data stored in the identified exempt portion of the data cache includes relatively new data written by the host system to the SLC data cache. In an embodiment, the exempt portion of the data cache has a fixed size (e.g., a 512 MB portion of a 6 GB data cache). In an embodiment, the size of the exempt portion can be set according to the number of blocks of the data cache, a predetermined size, a predetermined percentage of the total size of the data cache, etc. In an embodiment, the identified exempt portion of the data cache is Figure 2 the exempt portion 232 of

[0056] At operation 420, the processing device identifies a collected portion of the data cache of the memory subsystem, where the collected portion includes a second set of data blocks storing second data written by the host system. In an embodiment, the second data stored in the collected portion of the data cache includes relatively old data written by the host system to the SLC data cache (e.g., the first data written by the host system to the SLC cache is newer than the second data). In an embodiment, the collected portion of the data cache is Figure 2 the collected portion 234 of

[0057] At operation 430, the processing device performs a media management operation on the collected portion of the data cache to relocate the second data to a high data density storage region (e.g., an XCL storage region, such as an MLC / TLC / QLC storage region), where the exempt portion of the data cache is exempt from a garbage collection operation. By way of example, the media management operation can be a garbage collection operation. In an embodiment, exempting the exempt portion of the data cache from the media management operation (e.g., the garbage collection operation) causes the relatively new data in the data cache (e.g., data most recently written by the host system to the data cache) to remain or be maintained in the data cache. Advantageously, this newer or more recently written data remaining in the data cache represents data that is more likely to be overwritten by the host system. In an embodiment, the media management operation can be performed during idle time associated with the host system. In an embodiment, after performing the media management operation, in response to subsequent write activity of the host system generating "newer" host data, the first data can be allocated to one or more data blocks of the collected portion, where the data is subject to a subsequent garbage collection operation.

[0058] Figure 5An example cache management component 513 that controls garbage collection operations associated with a static SLC cache 530 of a control and memory subsystem according to some embodiments of the present disclosure, where the static SLC cache 530 includes a dynamic exemption portion size. As Figure 5 shown, a host system 520 writes host data to the static SLC cache 530 for storage in associated data blocks. In an embodiment, garbage collection operations are performed in the background to collect or relocate host data from the static SLC cache 530 to an XLC storage region 540 during host idle time. In an embodiment, if an inactive time period is reached (e.g., the host system 520 has no read or write activity), the idle state of the host system may be identified.

[0059] In an embodiment, as Figure 5 shown, the static SLC cache 530 is configured in a first-in, first-out arrangement, where newer host data is stored in a first set of one or more designated blocks (e.g., the topmost block as Figure 5 shown). In an embodiment, each write from the host system 520 is associated with information identifying the relative time of the corresponding write operation. For example, each write operation may be identified by a sequence identifier or version number. In an embodiment, the host data stored in the static SLC cache 530 may have an associated time such that the most recently written static SLC data can be identified.

[0060] In an embodiment, the cache management component 513 performs a garbage collection operation that is configured to collect data from a first portion (collected portions 534A, 534B) of the static SLC cache 230 while exempting a second portion (dynamic exemption portions 533A, 533B) of the static SLC cache 530 from the garbage collection process.

[0061] In Figure 5In the embodiments shown, the size of the portion of the static SLC cache 530 that is exempted from the garbage collection process is adjusted or tuned dynamically. In one instance, the size of the exempted portion 530 is adjusted or set based on one or more metrics or measured levels of the memory subsystem. In one instance, the size of the exempted portion 530 is adjusted or set based on the workload level associated with the host system 520. In an embodiment, the dynamic exemption portions 533A, 533B are adjusted based on the workload metrics of the host system 520 to maximize the benefits of reduced XLC WA and endurance requirements. In an embodiment, a baseline or default size value may be established for the dynamically sized exemption portions 533A, 533B and adjusted dynamically based on one or more measurements or metrics (e.g., host workload metrics) monitored and collected by the cache management component 513. Example host workload metrics include but are not limited to host burst size (e.g., the amount of host data written in bursts between host idle events), the amount of valid data garbage collected into the XLC storage region 540, and the amount of host data written directly to the XLC storage region 540 (TWB) (e.g., for a memory subsystem that supports a direct XLC write path). In an embodiment, the baseline size value of the second dynamically sized exemption portion 533B may be the size of the first dynamically sized exemption portion 533A.

[0062] In an embodiment, the size of the dynamic exemption portions 533A, 533B may be calculated according to the following expression:

[0063] Exempted portion size = function (one or more of host burst size, valid data garbage collected into the XLC storage region, host TBW in the XLC storage region, etc.).

[0064] In an embodiment, the dynamic exemption portion has a dynamically controlled or adjusted size that includes one or more blocks of the SLC cache 230 designated to store recently written static SLC data (e.g., a portion of the newer data). As Figure 5 shown, the cache management component 513 may determine the first dynamically sized exemption portion 533A at a first time (T1) in conjunction with a first garbage collection operation at T1. In an embodiment, the dynamically sized exemption portion 533A may include one or more data blocks that start from the topmost data block of the SLC cache 530 (corresponding to the latest host data) and end at a point corresponding to the size of the dynamically sized exemption portion. In Figure 5 the example shown, the dynamically sized exemption portion 533A at T1 corresponds to the two topmost blocks of the SLC cache 530. The remaining portion of the SLC data cache 530 (e.g., the remaining eight blocks) represents the collected portion 534A of the dynamically sized at T1.

[0065] As Figure 5 shown, at T1, an exemption portion 533A of a first dynamic size and a collected portion 534A of a first dynamic size are determined. In an embodiment, the size of the exemption portion 533A, 533B of the dynamic size may be defined based on a storage size or amount (e.g., 512 MB, 1 GB, etc.), the number of blocks of the SLC cache 530 (e.g., two blocks, two half - blocks, three blocks, etc.), a percentage of the total storage size of the SLC cache 530 (e.g., 20% of the total cache size), or other metrics.

[0066] As Figure 5 shown, the cache management component 513 performs a first garbage collection operation such that data stored in the collected portion 534A of the first dynamic size in the static SLC cache 530 is garbage - collected. The first garbage - collected data 550A is relocated to the XLC storage area 540, while the data stored in the exemption portion 533A of the first dynamic size is maintained in the static SLC cache 230 at T1. Since the exemption portion 533A of the first dynamic size is maintained in the data cache 530 at T1, host data that is more likely to be overwritten by the host system 520 in a subsequent recent time period is kept in the static SLC cache 530. Delaying the garbage collection of this recently written host data reduces or minimizes the garbage collection of valid data to the XLC storage area 540.

[0067] In an embodiment, in combination with a subsequent or second garbage collection operation at a second time (T2), a second exemption portion 533B of a second dynamic size and a second collected portion 534B of a second dynamic size are determined. In an embodiment, as described above, the size of the second exemption portion 533B of the dynamic size is determined at least in part based on one or more workload metrics associated with the host system 520. For example, during the time period between T1 and T2, the cache management component 513 may determine that the host system 520 has a reduced host burst size (e.g., a first workload metric) compared to the time period before T1. In this instance, based on the identified workload metric, the cache management component 513 may increase the size of the second exemption portion 533B of the second dynamic size compared to the size of the first exemption portion 533A. In an embodiment, the cache management component 513 performs a second garbage collection operation at T2 such that the second garbage - collected data 550B is relocated to the XLC storage area 540. In an embodiment, data stored in the second exemption portion 533B of the second dynamic size is exempted from the second garbage collection operation performed at T2, and thus, the data is maintained in the data cache 530.

[0068] In an embodiment, in view of updated workload metrics associated with the host system, the cache management component 513 adjusts the second dynamically sized exempt portion 533B and the second dynamically sized collected portion 533B relative to the first dynamically sized exempt portion 533A and the second dynamically sized collected portion 533A, respectively. In an embodiment, in view of the amount of host data overwritten in the static SLC cache and the write amplification of the XLC storage region, the cache management component 513 selects the dynamically sized exempt portions 533A, 533B to optimize the size of the collected portion 234.

[0069] Figure 6 FIG. 600 is a flow diagram of another example method for managing media management operations (e.g., garbage collection operations) to relocate data stored in a static SLC data cache to a higher density data storage region (e.g., an XLC storage region) in accordance with some embodiments of the present disclosure, where the static SLC cache includes the identified dynamically sized exempt portion and the dynamically sized collected portion. Method 600 may be performed by processing logic that may include hardware (e.g., a processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executing on a processing device), or a combination thereof. In some embodiments, method 600 is performed by Figure 1 the cache management component 113 of Figure 5 or the cache management component 513 of

[0070] At operation 610, the processing device determines a size of a first exempt portion of the data cache of the memory subsystem based on one or more first workload metrics associated with the host system. In an embodiment, the one or more first workload metrics may include a host burst size (i.e., the amount of host data written in bursts during the time period between host idle events), the amount of valid data that has been garbage collected to a high data density region (e.g., Figure 2 the XLC storage region 540) during one or more previous media management operations (e.g., garbage collection operations), and the amount of data written directly to the high data density region (e.g., written directly to Figure 5the amount of host data shown in the XLC storage area 540 in []. In an embodiment, the first portion size may be set by adjusting a baseline or default size value up or down according to one or more first workload metrics. In an embodiment, the first exemption portion size may be any suitable size to optimize the write amplification of the XLC storage area and the amount of data overwritten in the data cache. For example, for a 6 GB data cache, the first portion size may be approximately 512 MB.

[0071] At operation 620, the processing device identifies a first exemption portion of the data cache, where the first exemption portion has a first exemption portion size and includes a first set of data blocks storing first data written by the host system to the data cache. In an embodiment, the first exemption portion corresponds to Figure 5 the first dynamically sized exemption portion 533A in [].

[0072] At operation 630, the processing device identifies a first collected portion of the data cache of the memory subsystem, where the first collected portion stores second data written by the host system. In an embodiment, the sum of the first exemption portion size and the size of the first collected portion is equal to the total size of the data cache. Thus, after the first exemption portion has been identified, the first collected portion corresponds to the remaining portion of the data cache. In an embodiment, the first collected portion corresponds to Figure 5 the first dynamically sized collected portion 534A in [], because the size of the first collected portion varies based on the dynamically determined first exemption portion size.

[0073] At operation 640, the processing device performs a first media management operation on the first collected portion of the data cache to relocate the second data to a high data density storage area, where the first exemption portion of the data cache is exempt from the first media management operation. In an embodiment, the first data stored in the first exemption portion is not relocated to the XLC storage area but instead remains in the data cache. In an embodiment, the first media management operation (e.g., a garbage collection operation) corresponds to the garbage collection operation performed at Figure 5 T1 in []. In an embodiment, the second data (relocated to the XLC storage area 540 due to the garbage collection operation) corresponds to Figure 5 the first garbage collection data 550A of []. In an embodiment, the first media management operation (e.g., a garbage collection operation) is performed in response to identifying an idle event associated with the host system.

[0074] At operation 650, the processing device determines a second exempt portion size of the data cache based on one or more second workload metrics associated with the host system. In an embodiment, the one or more workload metrics associated with the host system may vary during an active period of the host system. In an embodiment, in response to an idle event associated with the host system, the processing device may determine updated or new workload metrics (e.g., one or more second workload metrics) for dynamically adjusting the size of the exempt portion of the data cache.

[0075] At operation 660, the processing device identifies a second exempt portion of the data cache, where the second exempt portion has the second exempt portion size and stores third data written by the host system. In an embodiment, the third data includes relatively newer host data (e.g., most recently written data) compared to the data stored in the remaining portion of the data cache. In an embodiment, the second exempt portion corresponds to Figure 5 the second dynamically sized exempt portion 533B.

[0076] At operation 670, the processing device identifies a second collected portion of the data cache of the memory subsystem, where the second collected portion stores fourth data written by the host system. In an embodiment, the second collected portion may be identified as the remaining portion of the data cache (i.e., the rest of the data cache, excluding the second exempt portion). In an embodiment, at least a portion of the fourth data may include first data exempted from a first garbage collection operation. In an embodiment, the second collected portion corresponds to Figure 5 the second dynamically sized collected portion 534B.

[0077] At operation 680, the processing device performs a second media management operation on the second collected portion of the data cache to relocate the fourth data to a high data density storage region, where the second exempt portion of the data cache is exempted from the second media management operation. In an embodiment, the second media management operation (e.g., a garbage collection operation) is a garbage collection operation performed on the second dynamically sized collected portion 534B at T2 for relocating second garbage collection data 550B to Figure 5 the XLC storage region 540 in.

[0078] Figure 7 An example machine of a computer system 700 is described, within which an instruction set executable to cause the machine to perform any one or more of the methods discussed herein may be executed. In some embodiments, the computer system 700 may correspond to a host system (e.g., Figure 1 the host system 120), which includes, is coupled to, or utilizes a memory subsystem (e.g., Figure 1of the memory subsystem 110) or can be used to perform operations of the controller (e.g., execute an operating system to perform operations corresponding to Figure 1 the cache management component 113). In alternative embodiments, the machine can be connected (e.g., networked) to other machines in a LAN, intranet, extranet, and / or the Internet. The machine can operate in the capacity of a server or client machine in a client-server network environment as a peer machine in a peer (or distributed) network environment or as a server or client machine in a cloud computing infrastructure or environment.

[0079] The machine can be a personal computer (PC), tablet PC, set-top box (STB), personal digital assistant (PDA), cellular phone, network appliance, server, network router, switch, or bridge, or any machine capable of executing a set of instructions (sequentially or otherwise) that specify actions to be taken by that machine. Further, although a single machine is illustrated, the term "machine" shall also be taken to include any collection of machines that individually or jointly execute a set of instructions (or multiple sets of instructions) to perform any one or more of the methods discussed herein.

[0080] An example computer system 700 includes a processing device 702, a main memory 704 (e.g., read only memory (ROM), flash memory, dynamic random access memory (DRAM), such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM), etc.), a static memory 706 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system 718, which communicate with each other via a bus 730.

[0081] The processing device 702 represents one or more general-purpose processing devices, such as a microprocessor, a central processing unit, etc. More particularly, the processing device can be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, or a processor implementing other instruction sets, or a processor implementing a combination of instruction sets. The processing device 702 can also be one or more special-purpose processing devices, such as an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), a network processor, etc. The processing device 702 is configured to execute instructions 726 for performing the operations and steps discussed herein. The computer system 700 can further include a network interface device 708 to communicate via a network 720.

[0082] The data storage system 718 may include a machine-readable storage medium 724 (also referred to as a computer-readable medium) having stored thereon one or more sets of instructions 726 or software that embody any one or more of the methods or functions described herein. The instructions 726 may also reside, completely or at least partially, within the main memory 704 and / or within the processing device 702 during execution thereof by the computer system 700, and the main memory 704 and the processing device 702 also constitute machine-readable storage media. The machine-readable storage medium 724, the data storage system 718, and / or the main memory 704 may correspond to Figure 1 the memory subsystem 110.

[0083] In one embodiment, the instructions 726 include instructions for implementing the functionality corresponding to a cache management component (e.g., Figure 1 the cache management component 113). Although the machine-readable storage medium 724 is shown as a single medium in the example embodiment, the term "machine-readable storage medium" should be considered to include a single medium or multiple media that store one or more sets of instructions. The term "machine-readable storage medium" should also be considered to include any medium that is capable of storing or encoding a set of instructions for execution by a machine and that causes the machine to perform any one or more of the methods of the present disclosure. Thus, the term "machine-readable storage medium" should be considered to include, but not be limited to, solid-state memory, optical media, and magnetic media.

[0084] Some portions of the foregoing detailed description have been presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. The algorithms and representations are used by those skilled in the data processing arts to most effectively convey the substance of their work to others skilled in the art. An algorithm is here, and generally, considered to be a self-consistent sequence of operations leading to a desired result. The operations are those requiring physical manipulation of physical quantities. Usually, though not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, combined, compared, and otherwise manipulated. It has proven convenient at times, principally for reasons of common usage, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, etc.

[0085] However, it should be borne in mind that all such and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. The present disclosure may relate to actions and processes of a computer system or similar electronic computing device that manipulate and transform data represented as physical (electronic) quantities within the registers and memories of the computer system into other data similarly represented as physical quantities within the computer system memory or registers or other such information storage systems.

[0086] The present disclosure also relates to an apparatus for performing the operations herein. This apparatus may be specially constructed for the intended purposes, or it may comprise a general purpose computer selectively activated or reconfigured by a computer program stored in a computer. Such a computer program may be stored in a computer readable storage medium, which may be, for example but not limited to, any type of disk (including floppy disks, optical disks, CD-ROMs, and magnetic optical disks), read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic or optical cards, or any type of media suitable for storing electronic instructions, each coupled to a computer system bus.

[0087] The algorithms and displays presented herein are not inherently related to any particular computer or other apparatus. Various general purpose systems may be used with programs in accordance with the teachings herein, or it may prove convenient to construct more specialized apparatus to perform the method. The structure of various of these systems will be presented as will be set forth in the description below. In addition, the present disclosure is not described with reference to any particular programming language. It will be appreciated that a variety of programming languages may be used to implement the teachings of the present disclosure as described herein.

[0088] The present disclosure may be provided as a computer program product or software, which may include a machine readable medium having stored thereon instructions, which can be used to program a computer system (or other electronic devices) to perform a process in accordance with the present disclosure. The machine readable medium includes any mechanism for storing information in a form readable by a machine (e.g., a computer). In some embodiments, the machine readable (e.g., computer readable) medium includes a machine (e.g., computer) readable storage medium such as read only memory (“ROM”), random access memory (“RAM”), magnetic disk storage media, optical storage media, flash memory components, etc.

[0089] In the foregoing specification, embodiments of the present disclosure have been described with reference to specific example embodiments. It will be apparent that various modifications may be made without departing from the broader spirit and scope of the embodiments of the present disclosure as set forth in the appended claims. Accordingly, the specification and drawings are to be regarded as illustrative rather than restrictive.

Claims

1. A method for managing a data cache, comprising: identifying, by a processing device, an exempt portion of the data cache of a memory subsystem, wherein the exempt portion includes a first set of data blocks storing first data written by a host system to the data cache; identifying a collected portion of the data cache of the memory subsystem, wherein the collected portion includes a second set of data blocks storing second data written by the host system; performing a media management operation on the collected portion of the data cache to relocate the second data to a storage area of the memory subsystem having a higher data density than the data cache, wherein the exempt portion of the data cache is exempted from the media management operation; adjusting a first size of the exempt portion based on an amount of host data written in one or more burst writes between a first host idle event and a second host idle event; and in response to a request to perform a write operation, reallocating the first data from the exempt portion of the data cache to a non-exempt portion of the data cache.

2. The method according to claim 1, further comprising maintaining storage of the first data in the data cache after performing the media management operation.

3. The method according to claim 1, wherein the first data includes a set of most recent data written by the host system; and wherein the second data includes data older than the first data.

4. The method according to claim 1, wherein the media management operation is performed in response to identifying an idle event associated with the host system.

5. A system for managing a data cache, comprising: a memory component; and a processing device operatively coupled to the memory component, the processing device for: determining a first exempt portion size of the data cache of the memory subsystem based on one or more first workload metrics associated with a host system; identifying a first exempt portion of the data cache based on the first exempt portion size, wherein the first exempt portion contains a first set of data blocks storing first data written by the host system to the data cache; identifying a first collected portion of the data cache of the memory subsystem, wherein the first collected portion stores second data written by the host system; performing a first garbage collection operation on the first collected portion of the data cache to relocate the second data to a storage area of the memory subsystem having a higher data density than the data cache, wherein the first exempt portion of the data cache is exempted from the first garbage collection operation; adjusting the first exempt portion size based on an amount of host data written in one or more burst writes between a first host idle event and a second host idle event; and in response to a request to perform a write operation, reallocating the first set of data blocks of the first exempt portion of the data cache to a different portion of the data cache subject to a second garbage collection operation.

6. The system according to claim 5, wherein at least one of the one or more first workload metrics includes a host burst size associated with the host system, an amount of valid data relocated into the storage region, or an amount of host data written into the storage region.

7. The system according to claim 5, wherein the data cache includes single-level cells, and the storage region includes one of multi-level cells, triple-level cells, or quadruple-level cells.

8. The system according to claim 5, wherein the processing device is configured to: Identify a first idle event associated with the host system, wherein the first garbage collection operation is performed in response to the first idle event.

9. The system according to claim 5, wherein the processing device is configured to: Identify a second exempt portion of the data cache, wherein the second exempt portion stores third data written by the host system based on a second exempt portion size; and Identify a second collected portion of the data cache of the memory subsystem, wherein the second collected portion stores fourth data written by the host system.

10. The system according to claim 9, wherein the first exempt portion size and the second exempt portion size are different values.

11. The system according to claim 9, wherein the processing device is configured to: Perform a second garbage collection operation on the second collected portion of the data cache to relocate the fourth data to the storage region, wherein the second exempt portion of the data cache is exempted from the second garbage collection operation.

12. The system according to claim 11, wherein the processing device is configured to: Identify a second idle event associated with the host system, wherein the second garbage collection operation is performed in response to the second idle event.

13. A non-transitory computer-readable medium storing instructions that, when executed, cause a processing device to: Identify an exempt portion of a data cache of a memory subsystem, wherein the exempt portion includes a first set of data blocks that includes first data written by a host system into the data cache; Identify a collected portion of the data cache of the memory subsystem, wherein the collected portion includes a second set of data blocks that includes second data written by the host system; Perform a garbage collection operation on the collected portion of the data cache to relocate the second data to a storage region of the memory subsystem having a higher data density than the data cache, wherein the exempt portion of the data cache is exempted from the garbage collection operation; Adjust a first size of the exempt portion based on an amount of host data written in one or more burst writes between a first host idle event and a second host idle event; And In response to a request to perform a write operation, reallocate the first data from the exempt portion of the data cache to a non-exempt portion of the data cache.

14. The non-transitory computer-readable medium according to claim 13, wherein the processing device is further configured to maintain the storage of the first data in the data cache after performing the garbage collection operation.

15. The non-transitory computer-readable medium according to claim 13, wherein a first size of the exemption portion is adjusted after performing the garbage collection operation.

16. The non-transitory computer-readable medium according to claim 13, wherein the first data includes a set of most recent data written by the host system; and wherein the second data includes data older than the first data.

17. The non-transitory computer-readable medium according to claim 13, wherein the garbage collection operation is performed in response to identifying an idle event associated with the host system.

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