Protective encapsulant for chalcogenide materials and method of forming the same

Abstract

This application relates to protective sealants for chalcogenide materials and methods for forming them. Techniques for forming gaskets to protect materials, such as storage element materials, from damage during subsequent operations or stages of a manufacturing process are described. The gaskets can be bonded to the material (e.g., chalcogenide materials) using strong or weak bonding. In some cases, sealant material may be deposited during the etching stage of the manufacturing process to prevent subsequent etching operations from damaging the material that has just been etched.

Description

[0001] Cross-references to related applications

[0002] This patent application is a national phase application of International Patent Application No. PCT / US2020 / 066471 filed by Good et al. on December 21, 2020, entitled “Protective Sealant for Chalcogenide Material and Methods for Forming the Same,” which claims protection for the benefits of U.S. Patent Application No. 16 / 731,963 filed by Good et al. on December 31, 2019, entitled “Protective Sealant for Chalcogenide Material and Methods for Forming the Same,” each of which is assigned to its assignee, and each of which is expressly incorporated herein by reference in its entirety. Technical Field

[0003] The technical field relates to protective sealants for chalcogenide materials and methods for their formation. Background Technology

[0004] Memory devices are widely used to store information in various electronic devices such as computers, wireless communication devices, cameras, digital displays, and the like. Information is stored by programming different states of the memory device. For example, binary devices most commonly store one of two states, typically represented by logic 1 or logic 0. In other devices, more than two states can be stored. To access the stored information, components of the device can read or sense at least one stored state in the memory device. To store information, components of the device can write or program states into the memory device.

[0005] Various types of memory devices exist, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase-change memory (PCM), other chalcogenide-based memories, and other memory devices. Memory devices can be volatile or non-volatile.

[0006] Generally, improving memory devices can include increasing memory cell density, improving read / write speeds, enhancing reliability, extending data retention, reducing power consumption or manufacturing costs, and other methods. Solutions may be needed to save space in the memory array, increase memory cell density, or reduce the overall power consumption of the memory array. Summary of the Invention

[0007] A method is described. The method may include forming a stack of materials comprising a chalcogenide material for storing information and a conductive material; and partially etching the stack of materials as part of an etching stage of a manufacturing process to form a post, the etching stage including: etching the chalcogenide material using a first set of etching parameters to expose the sidewalls of the chalcogenide material; depositing a first sealant material on the sidewalls of the chalcogenide material after or during etching at least a portion of the chalcogenide material to form a first gasket; etching the conductive material using a second set of etching parameters after depositing the first sealant material; and depositing a second sealant material over the post as part of a deposition stage occurring after the etching stage to form a second gasket.

[0008] A method is described. The method may include forming a stack of materials comprising a chalcogenide material for storing information and a conductive material; and, as part of an etching stage of a manufacturing process, etching the stack of materials to form a post, the etching stage including: etching the chalcogenide material using a first set of etching parameters to expose the sidewalls of the chalcogenide material; depositing a first sealant material on the sidewalls of the chalcogenide material after etching to form a first gasket; and, as part of a stage occurring after the etching stage, using a composition that modifies the first gasket using a substitution-based reaction.

[0009] A device is described. The device may include a post comprising a first electrode, a chalcogenide material coupled to the first electrode for storing information, and a second electrode coupled to the chalcogenide material; a first liner coupled to a sidewall of the chalcogenide material and extending between the first electrode and the second electrode; and a second liner coupled to the first liner, the first electrode, and the second electrode of the post, the second liner being a different material from the first liner.

[0010] A method is described. The method may include forming a stack of materials comprising a chalcogenide material for storing information and a conductive material; and partially etching the stack of materials as an etching stage of a manufacturing process to form a post, the etching stage including: etching the chalcogenide material using a first set of etching parameters to expose the sidewalls of the chalcogenide material; depositing a first sealant material on the sidewalls of the chalcogenide material after etching the chalcogenide material to form a first gasket; and etching the conductive material using a second set of etching parameters after depositing the first sealant material.

[0011] A method is described. The method may include forming a stack of materials comprising a chalcogenide material for storing information and a conductive material; and partially etching the stack of materials as an etching stage of a manufacturing process to form a post, the etching stage including: etching the chalcogenide material using a first set of etching parameters to expose the sidewalls of the chalcogenide material; depositing a first sealant material on the sidewalls of the chalcogenide material after etching the chalcogenide material to form a first gasket; etching the conductive material using a second set of etching parameters after depositing the first sealant material; performing a back etching process to remove at least a portion of the first gasket after the etching stage; and depositing the first sealant material after performing the back etching process to repair the first gasket. Attached Figure Description

[0012] Figure 1 Examples of memory arrays that support chalcogenide materials and methods of forming thereof are described herein.

[0013] Figures 2A to 2E Various views of example memory arrays supporting chalcogenide materials and their formation methods are illustrated, based on examples disclosed herein.

[0014] Figure 3 Examples of strong bonding between protective sealants for chalcogenide materials and their formation methods, as illustrated in the examples disclosed herein, are provided.

[0015] Figure 4 Examples of weak bonding situations are illustrated based on the protective sealants supporting chalcogenide materials and their formation methods, as disclosed herein.

[0016] Figures 5 to 8 A flowchart illustrating one or more methods for forming a protective sealant supporting chalcogenide materials, based on examples disclosed herein. Detailed Implementation

[0017] Some memory devices may incorporate chalcogenide materials to serve as storage components for memory cells to store data. As the size of components in memory devices decreases, damage caused by etching some materials can begin to affect the performance of those materials. For example, the effectiveness of a memory cell in storing data can be related to the amount of chalcogenide material in the undamaged or active memory cell. After exposing the sidewalls of the chalcogenide material using an etching operation, subsequent steps (such as etching electrode materials, cleaning stages, deposition stages, or exposure to air) can damage the chalcogenide material and / or mix undesirable chemical components into it, thereby reducing the volume of bulk or active material of the chalcogenide material suitable for storing information. In a more specific instance, if a process damages one micrometer of material, the percentage of bulk or active material damaged will be proportional to the total size of the material. As the size of the material decreases, the percentage of bulk material damaged by a given process can increase.

[0018] This describes techniques for forming gaskets to protect materials, such as memory element materials, from damage during subsequent operations or stages of a manufacturing process. Gaskets can be bonded to materials (e.g., chalcogenide materials) using strong or weak bonds. In some cases, sealant materials may be deposited during the etching stage of the manufacturing process to prevent subsequent etching operations from damaging the material that has just been etched.

[0019] The features of this disclosure were initially described in reference, as in [reference]. Figure 1 The features of this disclosure are described in the context of the memory array described herein. Figures 2A to 4 The context memory array and junction configuration are described herein. These and other features of this disclosure are further illustrated by flowcharts and described with reference to the flowcharts, which relate to, as referenced... Figures 5 to 8 The protective sealant for the chalcogenide material described herein and its formation method.

[0020] Figure 1 Examples of a memory array 100 (e.g., a three-dimensional (3D) memory array) based on a protective sealant for a chalcogenide material and a method of forming thereof, as disclosed herein, are illustrated. The memory array 100 may include a first array or deck 105 of memory cells positioned above a substrate 104 and a second array or deck 108 of memory cells on top of the first array or deck 105 and / or further decks repeating on top of the deck 108.

[0021] Memory array 100 may include word lines 110 (e.g., word lines 110-a and 110-b) and digital lines 115. Memory cells in the first deck 105 and the second deck 108 may each have one or more self-selectable memory cells. Memory cells in the first deck 105 and the second deck 108 may each have zero, one, or more memory cells (e.g., memory cell 125-a and memory cell 125-b, respectively). Although some elements depicted in FIG2 are labeled with numerical indicators, other corresponding elements are not labeled, but in an effort to improve the visibility and clarity of the depicted features, the elements are identical or will be understood to be similar.

[0022] The memory cells of the first deck 105 may include a first electrode 120-a, a memory cell 125-a (e.g., containing a chalcogenide material), and a second electrode 130-a. Similarly, the memory cells of the second deck 108 may include a first electrode 120-b, a memory cell 125-b (e.g., containing a chalcogenide material), and a second electrode 130-b. In some embodiments, the memory cells of the first deck 105 and the second deck 108 may have a common conductive line, such that corresponding memory cells of each deck 105 and 108 can share a bit line 115 or a word line 110. For example, the first electrode 120-b of the second deck 108 and the second electrode 130-a of the first deck 105 may be coupled to the bit line 115 such that the bit line 115 is shared by vertically adjacent memory cells. If the memory array 100 includes more than one deck, the decoder may be located above or below each deck. For example, the decoder may be located above the first deck 105 and above the second deck 108. In some cases, memory cell 125 may be an instance of a phase-change memory cell or a self-selection memory cell.

[0023] In some instances, a memory cell can be programmed by providing an electrical pulse to the cell, which may contain a memory storage element. The pulse may be provided via a first access line (e.g., word line 110) or a second access line (e.g., digital line 115) or a combination thereof. In some cases, after the pulse is provided, ions may migrate within the memory storage element, depending on the polarity of the memory cell. Therefore, the concentration of ions or atoms relative to a first or second side of the memory storage element may be based at least in part on the polarity of the voltage between the first and second access lines. In some cases, asymmetrically shaped memory storage elements may cause ions to be more crowded in portions of the element with a larger area. Certain portions of the memory storage element may have higher resistivity and thus may cause a higher threshold voltage than other portions of the memory storage element. This description of ion migration represents an example of a mechanism for achieving the results described herein in a self-selected memory cell. This example of a mechanism should not be considered limiting. This disclosure also includes other examples of mechanisms for achieving the results described herein in a self-selected memory cell.

[0024] The architecture of the memory array 100 may be referred to as a cross-point architecture. In some cases, in the cross-point architecture, memory cells are formed as follows: Figure 1 The topological intersection between word lines and bit lines is described in the diagram. This intersection architecture can provide relatively high-density data storage with lower manufacturing costs compared to other memory architectures. For example, the intersection architecture can have memory cells with reduced area, and therefore can have increased memory cell density compared to other architectures. For example, compared to other architectures with a memory cell area of ​​6F², such as an architecture with a three-terminal select component, the architecture can have a memory cell area of ​​4F², where F is the minimum feature size. For example, DRAM can use transistors (which are three-terminal devices) as select components for each memory cell, and can have a larger memory cell area compared to the intersection architecture.

[0025] Although Figure 1 The example demonstrates two memory decks, but other configurations are possible. In some instances, a single memory deck for a memory cell can be built on top of substrate 104, which may be referred to as a two-dimensional memory. In some instances, three or four memory decks for a memory cell can be configured in a similar manner in a three-dimensional cross-point architecture.

[0026] In some instances, one or more of the memory decks may include memory cells 125 comprising chalcogenide materials. For example, memory cells 125 may comprise chalcogenide glasses, such as alloys of selenium (Se), tellurium (Te), arsenic (As), antimony (Sb), carbon (C), germanium (Ge), and silicon (Si). In some instances, chalcogenide materials primarily comprising selenium (Se), arsenic (As), and germanium (Ge) may be referred to as SAG alloys. In some instances, SAG alloys may comprise silicon (Si) or indium (In), or combinations thereof, and such chalcogenide materials may be referred to as SiSAG alloys or InSAG alloys, or combinations thereof. In some instances, chalcogenide glasses may contain additional elements, each in atomic or molecular form, such as hydrogen (H), oxygen (O), nitrogen (N), chlorine (Cl), or fluorine (F).

[0027] In some instances, memory cells 125 containing chalcogenide materials can be programmed into a logical state by applying a first voltage. By way of example, when a particular memory cell 125 is programmed, elements within the cell separate, causing ion migration. Depending on the polarity of the voltage applied to the memory cell, ions may migrate toward a specific electrode. For example, in memory cell 125, ions may migrate toward the negative electrode. The memory cell can then be read for sensing by applying a voltage across the cells. The threshold voltage observed during the read operation can be based on the ion distribution within the memory cell and the polarity of the read pulse. In other instances, when a particular memory cell 125 is programmed with a voltage, a structural phase change can be induced in the cell material, thereby making the cell material crystalline or amorphous. The memory cell 125 can be read for sensing the high-resistance state of an amorphous memory cell or the low-resistance state of a crystalline memory cell by applying a voltage across the cells.

[0028] In some cases, as part of the access operation of memory cell 125, a first voltage may be applied to a first conductive line of the decoder. After the first voltage is applied, the first conductive line may be coupled to an access line (e.g., word line 110-a, word line 110-b, or bit line 115) associated with memory cell 125. For example, the first conductive line may be coupled to the access line based on a doped material of the decoder, the doped material extending in a first direction between the first conductive line and the access line.

[0029] In some instances, a first voltage may be applied to the memory cell 125 based on coupling a first conductive line of the decoder to an access line. The decoder may comprise one or more doped materials extending in a first direction away from the surface of the substrate 104 between the first conductive line and the access line of the memory array 100 of the memory cell. In some cases, the decoder may be coupled to the substrate 104.

[0030] Gaskets may be formed in the memory array 100 to protect, for example, the material of memory cells 125 from damage during subsequent operations or stages of the manufacturing process. Gaskets may be bonded to the material using strong or weak bonds (e.g., chalcogenide materials). In some cases, sealant material may be deposited during the etching stage of the manufacturing process to prevent subsequent etching operations from damaging the material that has just been etched.

[0031] Figures 2A to 2E Various views of example memory arrays 200-a, 200-b, 200-c, 200-d, and 200-e are illustrated below, based on examples disclosed herein, during a series of steps or processes that can be performed to form a stacked memory device. Specifically, in Figures 2A to 2E The paper demonstrates a method for protective bonding substitution of chalcogenide unit materials in a memory array structure.

[0032] Various techniques can be used to form the materials or components of the memory array 200. These techniques may include, for example, chemical vapor deposition (CVD), metal-organic chemical vapor deposition (MOCVD), physical vapor deposition (PVD), sputtering deposition, atomic layer deposition (ALD), or molecular beam epitaxy (MBE), as well as other thin film growth techniques. A variety of techniques can be used to remove material, including, for example, chemical etching (also known as “wet etching”), plasma etching (also known as “dry etching”), or chemical mechanical planarization (CMP).

[0033] Although not shown for clarity and ease of illustration, it should be understood that the illustrated array structure is formed over a substrate and, among other things, may include various peripheral and support circuitry systems, such as complementary metal-oxide-semiconductor (CMOS) transistors forming part of column and row driver circuitry and sense amplifier circuitry, and sockets and wiring connecting this circuitry system to the memory array via the columns and rows described above. Additionally, the substrate may comprise one or more memory arrays or "decks" of arrays. As used herein, the term substrate includes a bulk semiconductor substrate and the integrated structures formed thereon.

[0034] Figure 2A A cross-sectional view is shown of a memory array 200-a, illustrating a protective sealant for a chalcogenide material and a method for forming the same, according to examples disclosed herein. The memory array 200-a may comprise a stack 205 of material formed in an earlier processing step. The stack 205 may be configured to ultimately form multiple memory cells, as described herein.

[0035] The material stack 205 may include a variety of materials positioned on top of and adjacent to other materials in the stack 205. The material stack 205 may include oxide material 210, conductive material 215, thin layer material 220, bottom electrode material 225, chalcogenide material 230, top electrode material 235, and one or more hard mask materials 240.

[0036] Oxide material 210 may be positioned at the bottom of material stack 205. In some instances, oxide material 210 may be an example of a substrate associated with a memory cell. Oxide material 210 may be an example of a dielectric material. In some instances, oxide material 210 may be formed over a rigid mask (not shown).

[0037] The conductive material 215 may be operable as an access line for one or more memory cells. In some instances, the conductive material 215 may be an example of a word line associated with a memory cell. In some cases, the conductive material 215 may be coupled to or positioned above the oxide material 210. The conductive material 215 may comprise tungsten or copper, or a combination thereof. In some instances, the conductive material 215 may be used to form conductive lines.

[0038] The thin layer material 220 may be an example of a thin metal layer. The thin layer material 220 may be coupled or positioned above the conductive material 215.

[0039] The bottom electrode material 225 may be an example of an electrical conductor or electrical contact with the chalcogenide material 230. The bottom electrode material 225 may be positioned between the thin layer material 220 and the chalcogenide material 230. In some instances, the bottom electrode material 225 may be coupled to a conductive material 215. In such instances, the thin layer material 220 may not be present in the material stack 205. In some instances, the bottom electrode material 225 may be formed of a carbon-based material or a nitride material. In some cases, the bottom electrode material 225 may be referred to as a conductive material.

[0040] Chalcogenide material 230 is operable to store data based on a voltage applied to it. For example, chalcogenide material 230 is operable to store a first state based on the application of a first voltage pulse and a second state based on the application of a second voltage pulse. Chalcogenide material 230 can be used to form any type of chalcogenide-based memory cell, including phase-change memory cells, self-select memory cells, or another type of memory cell formed using chalcogenides. Chalcogenide material 230 can be coupled to bottom electrode material 225, top electrode material 235, or a combination thereof. Chalcogenide material 230 can be an example of a memory element material. In some cases, chalcogenide material 230 can form a memory element. In some cases, chalcogenide material 230 can form another type of element, such as a selector. In some cases, the features described with reference to chalcogenide material 230 can be applied to other types of materials, including other types of memory element materials.

[0041] The top electrode material 235 may be an example of an electrical conductor or electrical contact with the chalcogenide material 230. The top electrode material 235 may be positioned above the chalcogenide material 230. In some instances, the top electrode material 235 may be formed of a carbon-based material or a nitride material. In some cases, the top electrode material 235 may be referred to as a conductive material.

[0042] A rigid mask material 240 may be positioned above and coupled to a top electrode material 235. The rigid mask material 240 may be an example of an etch mask that protects portions of the underlying material. In such examples, areas under the rigid mask material 240 may be protected from etching during the etching phase of a manufacturing process. For example, one or more trenches 245 may be formed in or between the rigid mask material 240. The trenches 245 may be formed, for example, at least partially using photolithography techniques. The etching operation may remove material using various techniques, including, for example, chemical etching (also known as “wet etching”), plasma etching (also known as “dry etching”), or combinations thereof.

[0043] A manufacturing process for forming an array of memory cells may include a stack 205 of materials forming the memory array 200-a. Memory cells may be formed by the manufacturing process based on the stack 205. The manufacturing process may include one or more stages, each with one or more parameters that can be defined to advance the steps of the manufacturing process. Examples of stages may be one or more etching stages for etching at least a portion of the material, one or more deposition stages for depositing material onto the stack 205, and one or more cleaning stages for removing contaminants from the stack 205 of material. Each stage may include one or more etching processes, one or more deposition processes, or one or more cleaning processes, or combinations thereof. For example, an etching stage of the manufacturing process may include at least two different etching parameters. In such an example, a first set of etching parameters may be used to etch a first material (e.g., chalcogenide material 230), and a second set of etching parameters, different from the first set, may be used to etch a second material (e.g., bottom electrode material 225). Different sets of etching parameters may be used for different materials based on the characteristics of the material. For example, the first material can be softer than the second material, and different parameters can reduce or mitigate unwanted damage to the etched material.

[0044] An etching stage may involve etching multiple materials within stack 205. For example, a single etching stage may involve etching a top electrode material 235, a chalcogenide material 230, and a bottom electrode material 225. Etching may occur from top to bottom, and thus the material at the top of stack 205 (e.g., top electrode material 235) may be exposed to etching chemicals associated with different sets of etching parameters. Etching chemicals used to etch the lower material (e.g., bottom electrode material 225) may damage the higher material (e.g., chalcogenide material 230) if the higher material in stack 205 is softer or less resilient to certain etching chemicals (e.g., chalcogenide material 230) than the lower material in stack 205 (e.g., bottom electrode material 225).

[0045] This document describes techniques for forming a pad on the surface of a chalcogenide material 230 to protect the chalcogenide material 230 from the effects of etching chemicals associated with other processes or from the effects of other chemicals or processes in other stages during the same etching phase. During the etching phase, one or more surfaces of the chalcogenide material 230 may be exposed by the etching process. One or more materials may be deposited on one or more exposed surfaces of the chalcogenide material 230 during the etching phase to form a pad on one or more exposed surfaces of the chalcogenide material 230. In some instances, the pad may create a strong bond with the chalcogenide material 230. In some instances, the pad may create a weak bond with the chalcogenide material 230. In such instances, portions of the pad may be replaced during other processes or stages of the manufacturing process.

[0046] Figure 2B A cross-sectional view of a memory array 200-b illustrating a protective sealant for a chalcogenide material and a method for forming the same, according to examples disclosed herein. Memory array 200-b may be a reference. Figure 2A The described example is a memory array 200-a during an etching stage for etching the stack 205 of materials. For instance, the etching stage may be performed to form lines of chalcogenide material 230 from continuous sheets of material. Creating such lines allows the memory array 200-b to be closer together to have individual memory cells formed of chalcogenide material 230. The etching stage may allow trenches 245 to extend deeper into the stack 205 material, especially in areas not protected by the rigid mask material 240.

[0047] The etching stage may expose the sidewalls of one or more layers of the memory array 200-b. For example, the etching stage may expose one or more sidewalls of the top electrode material 235, the chalcogenide material 230, the bottom electrode material 225, the thin metal layer material 220, or combinations thereof. For example, one or more sidewalls 250 of the chalcogenide material 230 may be exposed by etching. Figure 2B In the example shown, a portion of some of the sidewalls 250 are exposed, while the larger portions of the other sidewalls 250 are exposed. The sidewalls 250 can be fully exposed after the etching stage is complete.

[0048] During the etching stage, different materials in stack 205 can be etched, and these different materials can be removed using different etching parameters or wet or dry etching chemicals. For example, electrode materials 225 and 235 can be formed of a harder material than chalcogenide material 230 and can be etched using a stronger set of parameters or etching chemicals. Because some materials may be etched after others, the etching of subsequent materials can damage previously etched materials.

[0049] As line sizes become smaller in memory devices, damage caused by etching can have a more significant impact. For example, the effectiveness of a memory cell in storing data can be related to the amount of undamaged bulk. After the sidewalls 250 of the chalcogenide material 230 are exposed, subsequent steps (e.g., etching the bottom electrode material 225, a cleaning stage, or a deposition stage) can damage the chalcogenide material and / or mix undesirable chemical components in one or more layers, thereby reducing the volume of the chalcogenide material 230 suitable for storing information. As the material size becomes smaller, the percentage of chalcogenide material bulk damaged by a given process can increase. To mitigate damage to the material after etching, a material (e.g., a sealant material) can be deposited during the etching stage to form a protective liner along the exposed sidewalls of the protected material.

[0050] Sealant material 255 may be deposited into trenches 245 of memory array 200-b. Sealant material 255 may be formed as a protective layer over one or more portions of exposed sidewalls. Sealant material 255 may be formed to a predetermined thickness. Alternatively or additionally, sealant material 255 may comprise silicon.

[0051] The sealant material 255 may contact the first sidewall, second sidewall, and / or bottom wall of each trench 245. After deposition, the sealant material 255 may contact the sidewalls 250 of the chalcogenide material 230. A gasket 270 is formed on the sidewalls 250 of the chalcogenide material 230. Figure 2C (As shown in the diagram) It can protect the chalcogenide material 230 from the effects of various subsequent etching, cleaning, or deposition processes (e.g., continuous plasma polymerization, plasma deposition, etc.) that can degrade the chalcogenide material 230 by damaging the surface and / or mixing undesirable chemical components in one or more layers. The pad 270 can achieve an edge composition on the chalcogenide material 230 through a targeted bonding process, thereby reducing damage that can occur during subsequent processes (e.g., dry etching, plasma etching, wet etching, etc.) by using ion / group cycling. For example, high-energy reactive species such as groups and / or ions can be generated during the etching process. In some cases, group and / or ion transfer can occur (e.g., one or more ions and / or groups can be deposited on one or more edges of the chalcogenide material). Additionally or alternatively, one or more ions and / or groups can be located within the bulk of the chalcogenide material.

[0052] like Figure 2BAs shown, ions 260 and / or groups 265 can be formed on the sidewalls 250 of the chalcogenide material 230 via group substitution processes or reactions to produce a reactive intermediate handle. Ions 260 and / or groups 265 can be deposited to form a pad 270, such as by... Figure 2C As shown. The gasket 270 may be formed on the chalcogenide material 230 to mitigate contamination and / or element loss associated with subsequent stages or operations of the manufacturing process.

[0053] Pad 270 can be used as per reference. Figure 3 The described strong bonding scheme is formed. Alternatively, gasket 270 can be used as referenced. Figure 4 The described weak-bonding scheme is formed. When using a weak-bonding scheme, the composition of one or more portions of the gasket 270 can be modified by subsequent operations in the manufacturing process. In such examples, the sealant material deposited to form the gasket 270 can be configured to be modified by chemical changes in subsequent operations. In some instances of weak bonding, the sidewalls 250 of the chalcogenide material 230 can be oxidized. Later, reduction can occur in the deposition process (e.g., ALD or CVD deposition process).

[0054] Sealant material can be deposited simultaneously with the etching of chalcogenide material 230. In some instances, the sealant material can be deposited after etching chalcogenide material 230 but before etching bottom electrode material 225. During etching of bottom electrode material 225, a gasket 270 formed by the sealant material protects chalcogenide material 230 from damage and / or mixing with undesirable chemical components. Etching of bottom electrode material 225 can occur after the deposition of sealant material. Etching of bottom electrode material 225 can still damage gasket 270 or allow chemical components to mix with gasket 270. In some cases, gasket 270 can be repaired during or after etching bottom electrode material 225 by depositing sealant material (e.g., a third sealant material) to replenish, repair, or add to gasket 270. Gasket 270 can be repaired by depositing additional sealant material after or during any operation or stage of the manufacturing process.

[0055] Figure 2C An example cross-sectional view of a memory array 200-c, illustrating a protective sealant for a chalcogenide material and a method for forming the same, according to examples disclosed herein. The memory array 200-c may be used as a reference. Figure 2BThe described example is a memory array 200-b after an etching and / or wet cleaning process has been performed on portions of the material stack 205. As part of the etching stage, one or more pads 270 are formed on the sidewalls 250 of the chalcogenide material 230. The pads 270 (e.g., engineered sidewalls of the chalcogenide material 230) can be examples of self-assembled monolayers (SAMs) or covalently bonded atoms or compounds, further referenced. Figure 3 and 4 The following description is provided. Alternatively or concurrently, the pad 270 may be a film comprising one or more SAMs. The pad 270 may extend between the top electrode material 235 (e.g., a first conductive material) and the bottom electrode material 225 (e.g., a second conductive material). For example, the pad 270 may be formed on one or more edges of the chalcogenide material 230.

[0056] The memory array 200-c with pad 270 can be referenced after the etching stage. Figure 3 The strong bonding condition described occurs. Alternatively, the memory array 200-c with pad 270 can be manufactured after the cleaning stage of the manufacturing process, as referenced. Figure 4 This occurs under the described weak bonding condition.

[0057] The cleaning phase of the manufacturing process may include a wet cleaning process to remove one or more materials from the material stack 205. During etching and other processes, various materials or contaminants may remain on the material stack 205. To remove those materials or contaminants from the stack 205, the stack 205 may be washed with various chemicals or immersed in various chemicals.

[0058] As part of a weak bonding scenario, the chemicals used in the wet cleaning process can be manipulated to alter the composition of the gasket 270. In some instances, the wet cleaning process can replace the bonding of one or more weakly etched ends with oxidation. In such instances, the cleaning stage can oxidize at least partially the gasket. In some instances, the gasket 270 is configured to protect the chalcogenide material 230 from reaction during the cleaning and deposition stages that occur after the etching stage.

[0059] Figure 2D An example cross-sectional view of a memory array 200-d, illustrating a protective sealant for supporting chalcogenide materials and a method for forming the same, according to examples disclosed herein. The memory array 200-d may be a reference. Figure 2C An example of a memory array 200-c following a deposition pad 275 is described. In some cases, pad 275 may be an example of a sacrificial pad.

[0060] Gasket 275 (e.g., a second gasket) may be coupled to gasket 270, top electrode material 235, bottom electrode material 225, rigid mask material 240, conductive material 215, thin layer material 220, or a combination thereof. Gasket 275 may be a different material than gasket 270. In some cases, a second gasket may be an instance of gasket 275. Gasket 275 may be configured to protect portions of stack 205 from the effects of subsequent operations or stages of the manufacturing process. For example, gasket 275 may protect portions of stack 205 from subsequent etching stages, subsequent cleaning stages, or subsequent sealing stages, or combinations thereof. In some cases, gasket 275 may be removed before the manufacturing process is completed. In some cases, gasket 275 may not be removed before the manufacturing process is completed.

[0061] Figure 2E An example cross-sectional view of a memory array 200-e, illustrating a protective sealant for supporting chalcogenide materials and a method for forming the same, according to examples disclosed herein. The memory array 200-e may be a reference. Figure 2D The described example is of a memory array 200-d after depositing a sealant material to form a second gasket 280. Memory array 200-e illustrates an example of a wedge-shaped pillar-like structure. In some cases, memory array 200-e may be formed as a vertical pillar-like structure. For example, forming a second gasket on memory array 200-d can create a vertical pillar-like structure. In other examples, such as those shown by memory array 200-e, the pillar-like structure may be wedge-shaped (e.g., due to a certain isotropic nature of the etching).

[0062] The second pad 280 may be formed over pad 270 or pad 275, top electrode material 235, bottom electrode material 225, hard mask material 240, conductive material 215, thin layer material 220, oxide material 210, or a combination thereof. The second pad 280 may be a different material than pad 270. In some instances, the second pad 280 may be an example of a silicon nitride pad.

[0063] To form memory array 200-e, memory array 200-d may undergo various operations or stages. For example, an etching operation (e.g., a portion of an etching stage) may be applied to memory array 200-d to remove some of the conductive material 215 to form conductive lines (e.g., word lines). This etching process may expose one or more sidewalls of the conductive material 215 or one or more walls of the oxide material 210, or combinations thereof. During the etching step, portions or combinations of the hard mask material 240 or the pad 275 may be removed. A cleaning operation (e.g., a portion of a cleaning stage) may be applied to the memory array after the etching operation to remove contaminants. A deposition operation (e.g., a portion of a deposition stage) may be applied to the memory array to form a second pad 280. The deposition operation may seal the resulting stack of materials.

[0064] To obtain the final pillar structure of the memory array 200, one or more additional operations may be performed. For example, a filler material may be deposited in the trench 245. In some instances, the hard mask material 240 may be removed to expose the top electrode material 235. In some instances, a conductive material (not shown) may be deposited to form digital lines. In some instances, the pillars may be defined in a second direction perpendicular to the first direction by removing portions of the conductive material forming the digital lines, the top electrode material 235, the chalcogenide material 230, the bottom electrode material 225, or a combination thereof. During etching in the second direction, reference may be used. Figures 2A to 2E The described method protects the sidewalls of the chalcogenide material with a liner material, and additional liner materials can be used.

[0065] Figures 2A to 2E A process flow for forming a memory array is described, comprising an etching stage for opening chalcogenide material 230, a subsequent cleaning stage, a deposition stage for depositing pad 275, a subsequent etching stage, a cleaning stage, and a deposition stage for sealing the stack (e.g., depositing a second pad 280). Other process flows utilizing the same characteristics of pad 270 are also possible.

[0066] In some instances of the process flow used to form a memory array, the process flow may not include the deposition pad 275. In such instances, the etching stage, cleaning stage, and deposition stage may be completed in a single sequence.

[0067] In some instances of process flows used to form memory arrays, the process flow may include an etching stage where in-situ etching chemistry techniques can be employed throughout the process to protect one or more features of the memory array. In such instances, the pad 270 may be repaired after the operation or stage is completed, or may be repaired simultaneously with the etching stage and / or other stages.

[0068] In some instances of the process flow used to form a memory array, the process flow may include an etch-back process, in which the pad 270 is completely removed after the etching stage. In such instances, pad 270 may be repaired during the cleaning stage and / or during the deposition stage. In such cases, the manufacturing system may be configured to perform an etch-back process to remove at least a portion of the first pad after the etching stage, and to deposit a first sealant material to repair the first pad after performing the etch-back process.

[0069] Figure 3 Examples of strong bonding configuration 300 for a protective sealant supporting a chalcogenide material and its formation method, as disclosed herein, are illustrated. Strong bonding configuration 300 for gasket 270 includes forming a strong bond with chalcogenide material 230.

[0070] Box 305 includes a first representation 310 of a variety of possible chemical compositions of the chalcogenide material 230 before the deposition of the sealant material to form the gasket 270 and a second representation 315 of a variety of possible chemical compositions of the sidewalls 250 of the chalcogenide material 230 after the deposition of the sealant material.

[0071] For reference Figure 2B As described, the bulk material may be associated with chalcogenide material 230, and in this example may include one or more chalcogenide elements or compounds, such as one or more Ge, As, Se and / or In, as well as other elements. Chemical pathways introduced into the strong bonding condition may occur during the etching stage. In this example, the deposition process may introduce chemically active ions, groups, and / or compounds into the exposed bulk material. Feed gases (e.g., C2H2, CH4, CF3I, or AsH3, and other gases) may be introduced during the deposition process to form strongly bonded and reactive edge compositions, such as SAM, along one or more surfaces of the bulk material. During this process, preferred elements may be deposited on one or more surfaces of the bulk material. For example, if the bulk material comprises T or Q, then organic T compound (TC) or organic Q compound (QC) compounds may be formed, respectively. In another example, if the bulk material comprises X or Y, then XI or XY bonds may be formed at the edges, respectively. For example, if the bulk material includes Ge or Se, then organogermanium (GeC) or organoselenium (SeC) compounds can be formed, respectively. In another example, if the bulk material includes As or In, then AsI or InAs bonds can be formed at the edges, respectively. The bulk may include one or more elements from Groups 13, 14, 15, 16, and / or 17 of the International Union of Applied Chemistry and Pure Chemicals (IUPAC) periodic table, issued on December 1, 2018.

[0072] In this example, the strong bond formed during the dry etching step can have a bond dissociation energy greater than 439 kJ / mol. The edge can serve as a reactive intermediate; for example, a subsequent wet cleaning process can introduce hydroxyl groups (OH), thereby further altering the edge composition. Box 320 contains a representation of a variety of possible chemical compositions of the chalcogenide material 230 and / or the liner 270 after the cleaning stage. For example, intermediate edge compositions such as T-COH, Q-IOH, T-COH, or QY-OH can be formed. For example, intermediate edge compositions such as GeCOH, AsIOH, SeCOH, or InAsOH can be formed. The hydroxyl groups can further undergo a substitution reaction, wherein the hydroxyl groups are replaced with silicon nitride during the deposition operation (e.g., ALD or CVD). In some cases, the deposition operation can be configured to deposit a reference. Figure 2D The gasket 275 is described. In some cases, the deposition operation may be configured to deposit sealant material to form a reference. Figure 2E The second gasket 280 is described. In this way, an initial strong bond is maintained, thereby forming engineered sidewalls with compositions of T-CNSi, X-INSi, Q-CNSi, and / or YX-NSi (as referenced). Figures 2C to 2E (As described). In more specific instances, initial strong bonding can be maintained, thereby forming engineered sidewalls with compositions of GeCNSi, AsINSi, SeCNSi, and / or InAsNSi. Box 325 includes a representation of a variety of possible chemical compositions of chalcogenide material 230 and / or gasket 270 after the deposition or sealing stage.

[0073] Figure 4 Examples of weak bonding scenarios 400 for protective sealants supporting chalcogenide materials and their formation methods, as disclosed herein, are illustrated. The weak bonding scenario 400 for gasket 270 includes forming a weak bond with chalcogenide material 230.

[0074] Box 405 includes a first representation 410 of a variety of possible chemical compositions of the chalcogenide material 230 before the deposition of the sealant material to form the gasket 270 and a second representation 415 of a variety of possible chemical compositions of the sidewalls 250 of the chalcogenide material after the deposition of the sealant material.

[0075] For reference Figure 2B and Figure 3As described, the bulk material may be associated with chalcogenide material 230, and in this example, may contain T, X, Q, and / or Y (e.g., Ge, As, Se, and / or In). In this example, chemical bonding may form on the chalcogenide material 230 during the etching stage and during other stages. In this example, the bulk material may be exposed to one or more hydrogen halides (e.g., HBr) during the etching operation, thus generating reactive handles that are readily chemically substituted during subsequent oxidation steps. The reactive handles in this step can be considered as weakly bonded materials to be exchanged during the cleaning and / or deposition stages. In some examples, weak bonding can be understood as chemically bonded species associated with a bonding dissociation energy of less than 439 kJ / mol. As shown, the bulk material may include one or more elements from Groups 13, 14, 15, 16, and / or 17 of the IUPAC periodic table published on December 1, 2018.

[0076] For example, by exposing the surface of a bulk material (e.g., chalcogenide material 230) to HBr, Br-terminated surfaces (e.g., TBr, XBr, QBr, YBr, GeBr, AsBr, SeBr, InBr, etc.) can be created. During a cleaning step (e.g., an oxidation step), the Br-terminated surfaces (edges) can be exposed to hydroxyl groups, thus allowing Br atoms to be replaced by hydroxyl groups during the substitution reaction (e.g., or Box 420 represents a representation of a variety of possible chemical compositions of the chalcogenide material 230 and / or liner 270 after the cleaning stage. Following this step, the hydroxyl-terminated surfaces of the bulk may undergo a reduction reaction during a deposition stage (e.g., ALD or CVD) to replace the hydroxyl groups, thereby forming engineered sidewalls (see reference). Figures 2C to 2E In some cases, the deposition operation can be configured to use a deposition reference. Figure 2D The gasket 275 is described. In some cases, the deposition operation may be configured to deposit sealant material to form a reference. Figure 2E The second gasket 280 is described. The engineered sidewalls may have compositions of TNSi, XNSi, QNSi and / or YNSi or GeNSi, AsNSi, SeNSi and / or InNSi, as well as other compositions. Box 425 includes a representation of a variety of possible chemical compositions of the chalcogenide material 230 and / or gasket 270 after the deposition or sealing stage.

[0077] Figure 5A flowchart illustrating one or more methods 500 for creating a protective sealant for supporting chalcogenide materials according to aspects of the present invention and a method for forming the same. Operation of method 500 may be implemented by a manufacturing system or one or more controllers associated with the manufacturing system. In some instances, one or more controllers may execute a set of instructions to control one or more functional elements of the manufacturing system to perform the described functions. Alternatively or concurrently, one or more controllers may use dedicated hardware to perform aspects of the described functions.

[0078] At 505, method 500 may include forming a stack of materials comprising a chalcogenide material for storing information and / or a switching device and a conductive material. Operation of 505 may be performed according to the method described herein.

[0079] At 510, method 500 may include a stack of partially etched material as an etching stage of a manufacturing process to form a guide post. Operation of 510 may be performed according to the methods described herein.

[0080] At 515, method 500 may include, as part of an etching stage, etching the chalcogenide material using a first set of etching parameters to expose the sidewalls of the chalcogenide material. The operation at 515 may be performed according to the method described herein.

[0081] At 520, method 500 may include, as part of an etching stage, depositing a first sealant material onto the sidewalls of the chalcogenide material to form a first gasket after or during etching at least a portion of the chalcogenide material. Operation 520 may be performed according to the methods described herein.

[0082] At 525, method 500 may include, as part of an etching stage, etching the conductive material using a second set of etching parameters after depositing the first sealant material. The operation at 525 may be performed according to the method described herein.

[0083] At 530, method 500 may include depositing a second sealant material over the post as part of a deposition stage that occurs after the etching stage to form a second liner. Operation 530 may be performed according to the method described herein.

[0084] In some instances, the apparatus as described herein may perform one or more methods, such as method 500. The apparatus may include features, components, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for forming a stack of materials comprising a chalcogenide material and a conductive material for storing information, or for partially etching the stack of materials as part of an etching stage of a manufacturing process to form a post. The etching stage may include: etching the chalcogenide material using a first set of etching parameters to expose the sidewalls of the chalcogenide material; depositing a first sealant material on the sidewalls of the chalcogenide material after or during etching at least a portion of the chalcogenide material to form a first pad; and etching the conductive material using a second set of etching parameters after depositing the first sealant material. The apparatus may also include features, components, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for depositing a second sealant material over the post as part of a deposition stage occurring after the etching stage to form a second pad.

[0085] Some examples of the methods 500 and apparatus described herein may further include operations, features, components, or instructions for depositing a third sealant material after etching a conductive material to repair a first liner coupled to the sidewall of a chalcogenide material, wherein the deposition of a second sealant material may be based on the deposition of a third sealant material after etching the conductive material.

[0086] In some examples of the methods 500 and apparatus described herein, the deposition of the first sealant material may further include operations, features, components, or instructions for depositing one or more elements configured to bond with the chalcogenide material to form the first gasket. In some examples of the methods 500 and apparatus described herein, the one or more elements comprise functional groups or ionic or reactive compounds. In some examples of the methods 500 and apparatus described herein, the one or more elements comprise one or more halogen elements.

[0087] Some examples of the methods 500 and apparatus described herein may further include operations, features, components, or instructions for cleaning the guide post using a wet cleaning process as part of a cleaning phase that occurs after the etching phase, wherein the deposition of a second sealant material occurs after the cleaning phase.

[0088] In some examples of the methods 500 and apparatus described herein, the first pad may be configured to protect the chalcogenide material from reaction during the cleaning and deposition stages that occur after the etching stage. In some examples of the methods 500 and apparatus described herein, the first pad may be configured to protect the chalcogenide material from the effects of one or more processes used as part of the etching stage for etching subsequent materials. In some examples of the methods 500 and apparatus described herein, the etching stage comprises a dry etching process. In some examples of the methods 500 and apparatus described herein, the second pad comprises silicon nitride.

[0089] Figure 6 A flowchart illustrating one or more methods 600 of a protective sealant supporting a chalcogenide material and a method for forming the same, according to aspects of the present invention, is shown. Operation of method 600 may be implemented by a manufacturing system or one or more controllers associated with the manufacturing system. In some instances, one or more controllers may execute a set of instructions to control one or more functional elements of the manufacturing system to perform the described functions. Alternatively or additionally, one or more controllers may use dedicated hardware to perform aspects of the described functions.

[0090] At 605, method 600 may include forming a stack of materials comprising a chalcogenide material and / or a switching material and a conductive material for storing information. Operation of 605 may be performed according to the methods described herein.

[0091] At 610, method 600 may include a stack of partially etched material as an etching stage of a manufacturing process to form a guide post. Operation of 610 may be performed according to the method described herein.

[0092] At 615, method 600 may include, as part of an etching stage, etching the chalcogenide material using a first set of etching parameters to expose the sidewalls of the chalcogenide material. The operation at 615 may be performed according to the method described herein.

[0093] At 620, method 600 may include, as part of an etching stage, depositing a first sealant material onto the sidewalls of the chalcogenide material after etching to form a first gasket. The operation at 620 may be performed according to the method described herein.

[0094] At 625, method 600 may include, as part of an etching stage, a stage occurring after the etching stage, using a substitution-based reaction to modify the composition of the first pad. Operation 625 may be performed according to the methods described herein.

[0095] In some instances, the apparatus as described herein may perform one or more methods, such as method 600. The apparatus may include features, components, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for forming a stack of materials comprising a chalcogenide material and a conductive material for storing information, and as part of an etching stage of a manufacturing process, etching the stack of materials to form a post. The etching stage may include: etching the chalcogenide material using a first set of etching parameters to expose the sidewalls of the chalcogenide material; depositing a first sealant material on the sidewalls of the chalcogenide material after etching to form a first gasket; and, as part of the etching stage, as part of a stage occurring after the etching stage, using a composition of the first gasket based on a substitution reaction to modify it.

[0096] Some examples of the method 600 and apparatus described herein may further include operations, features, components, or instructions for depositing a second sealant material over the guide post to form a second gasket as part of a deposition phase occurring after the etching phase, wherein the composition of the first gasket is altered during the deposition phase and the phase includes the deposition phase. Some examples of the method 600 and apparatus described herein may further include operations, features, components, or instructions for cleaning the guide post using a wet cleaning process as part of a cleaning phase occurring after the etching phase, wherein the composition of the first gasket is altered during the cleaning phase and the phase includes the cleaning phase.

[0097] In some examples of the method 600 and apparatus described herein, the deposition of the first sealant material may further include operations, features, components, or instructions for oxidizing the surface of the sidewalls of the chalcogenide material. In some examples of the method 600 and apparatus described herein, the etching stage may further include operations, features, components, or instructions for etching the conductive material using a second set of etching parameters as part of the etching stage and after the deposition of the first sealant material, wherein the composition of the first gasket may be based on etching the conductive material.

[0098] In some examples of the method 600 and apparatus described herein, the deposition of the first sealant material may further include operations, features, components, or instructions for depositing one or more elements configured to bond with the chalcogenide material to form the first gasket. In some examples of the method 600 and apparatus described herein, the one or more elements comprise one or more ions.

[0099] Figure 7A flowchart illustrating one or more methods 700 for a protective sealant supporting a chalcogenide material and a method for forming the same, according to aspects of the present invention, is shown. Operation of method 700 may be implemented by a manufacturing system or one or more controllers associated with the manufacturing system. In some instances, one or more controllers may execute a set of instructions to control one or more functional elements of the manufacturing system to perform the described functions. Alternatively or concurrently, one or more controllers may use dedicated hardware to perform aspects of the described functions.

[0100] At 705, method 700 may include forming a stack of materials comprising a chalcogenide material and a conductive material for storing information. Operation at 705 may be performed according to the method described herein.

[0101] At 710, method 700 may include a stack of partially etched material as an etching stage of a manufacturing process to form a guide post. Operation of 710 may be performed according to the methods described herein.

[0102] At 715, method 700 may include, as part of an etching stage, etching the chalcogenide material using a first set of etching parameters to expose the sidewalls of the chalcogenide material. The operation at 715 may be performed according to the method described herein.

[0103] At 720, method 700 may include, as part of an etching stage, depositing a first sealant material onto the sidewalls of the chalcogenide material after etching to form a first gasket. Operation 720 may be performed according to the methods described herein.

[0104] At 725, method 700 may include, as part of an etching stage, etching the conductive material using a second set of etching parameters after depositing the first sealant material. The operation at 725 may be performed according to the methods described herein.

[0105] In some instances, the apparatus as described herein may perform one or more methods, such as method 700. The apparatus may include features, components, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for forming a stack of materials comprising a chalcogenide material and a conductive material for storing information, and as part of an etching stage of a manufacturing process, etching the stack of materials to form a post. The etching stage may include: etching the chalcogenide material using a first set of etching parameters to expose the sidewalls of the chalcogenide material; depositing a first sealant material on the sidewalls of the chalcogenide material after etching the chalcogenide material to form a first gasket; and etching the conductive material using a second set of etching parameters after depositing the first sealant material.

[0106] Some examples of the method 700 and apparatus described herein may further include operations, features, components, or instructions for cleaning the guide post using a wet cleaning process as part of a cleaning phase that occurs after the etching phase. In some examples of the method 700 and apparatus described herein, a first gasket may be configured to protect the chalcogenide material from reaction during the cleaning phase and other phases that occur after the etching phase.

[0107] In some examples of the method 700 and apparatus described herein, the deposition of the first sealant material may further include operations, features, components, or instructions for depositing one or more elements configured to bond with a chalcogenide material to form a first gasket. In some examples of the method 700 and apparatus described herein, the one or more elements comprise functional groups or ionic or reactive compounds. In some examples of the method 700 and apparatus described herein, the one or more elements comprise one or more halogen elements.

[0108] Figure 8 A flowchart illustrating one or more methods 800 for a protective sealant supporting a chalcogenide material and a method for forming the same, according to aspects of the present invention, is shown. Operation of method 800 may be implemented by a manufacturing system or one or more controllers associated with the manufacturing system. In some instances, one or more controllers may execute a set of instructions to control one or more functional elements of the manufacturing system to perform the described functions. Alternatively or concurrently, one or more controllers may use dedicated hardware to perform aspects of the described functions.

[0109] At 805, method 800 may include forming a stack of materials comprising a chalcogenide material and a conductive material for storing information. Operation of 805 may be performed according to the methods described herein.

[0110] At 810, method 800 may include a stack of partially etched material as an etching stage of a manufacturing process to form a guide post. Operation of 810 may be performed according to the method described herein.

[0111] At 815, method 800 may include, as part of an etching stage, etching the chalcogenide material using a first set of etching parameters to expose the sidewalls of the chalcogenide material. The operation at 815 may be performed according to the method described herein.

[0112] At 820, method 800 may include, as part of an etching stage, depositing a first sealant material onto the sidewalls of the chalcogenide material after etching to form a first gasket. Operation 820 may be performed according to the methods described herein.

[0113] At 825, method 800 may include, as part of an etching stage, etching the conductive material using a second set of etching parameters after depositing the first sealant material. The operation at 825 may be performed according to the method described herein.

[0114] At 830, method 800 may include performing a re-etching process to remove at least a portion of the first pad after the etching stage. The operation at 830 may be performed according to the method described herein.

[0115] At 835, method 800 may include depositing a first sealant material to repair the first gasket after performing the etch-back process. The operation at 835 may be performed according to the method described herein.

[0116] In some instances, the apparatus as described herein may perform one or more methods, such as method 800. The apparatus may include features, components, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for forming a stack of materials comprising a chalcogenide material and a conductive material for storing information, and for partially etching the stack of materials as part of an etching stage of a manufacturing process to form a post. The etching stage may include: etching the chalcogenide material using a first set of etching parameters to expose the sidewalls of the chalcogenide material; depositing a first sealant material on the sidewalls of the chalcogenide material after etching to form a first gasket; and etching the conductive material using a second set of etching parameters after depositing the first sealant material. The apparatus may also include a back-etching process for performing an etching process after the etching stage to remove at least a portion of the first gasket and for depositing the first sealant material after performing the back-etching process to repair the features, components, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor).

[0117] Some examples of the method 800 and apparatus described herein may further include operations, features, components, or instructions for cleaning the guide post using a wet cleaning process as part of a cleaning phase that occurs after the etching phase, wherein the back etching process occurs after the guide post has been cleaned using the wet cleaning process. Some examples of the method 800 and apparatus described herein may further include operations, features, components, or instructions for depositing a second sealant material over the guide post to form a second gasket as part of a deposition phase that occurs after depositing a first sealant material to repair a first gasket.

[0118] In some examples of the method 800 and apparatus described herein, the deposition of the first sealant material may further include operations, features, components, or instructions for depositing one or more elements configured to bond with the chalcogenide material to form the first gasket. In some examples of the method 800 and apparatus described herein, the first gasket may be configured to protect the chalcogenide material from the effects of one or more processes used as part of an etching stage for etching subsequent materials. In some examples of the method 800 and apparatus described herein, the etching stage includes a dry etching process.

[0119] It should be noted that the methods described above describe possible implementations, and the operations and steps can be rearranged or otherwise modified, and other implementations are possible. Furthermore, portions of two or more of the methods may be combined.

[0120] A device is described. The device may include: a post having a first electrode, a chalcogenide material coupled to the first electrode for storing information, and a second electrode coupled to the chalcogenide material; a first pad coupled to a sidewall of the chalcogenide material and extending between the first and second electrodes; and a second pad coupled to the first pad, the first electrode, and the second electrode of the post, the second pad being a different material from the first pad. Some examples of the device may include conductive wires coupled to the first electrode of the post. Some examples of the device may include a thin layer positioned between the conductive wires and the first electrode of the post.

[0121] The information and signals described herein can be represented using any of a variety of different techniques and skills. For example, data, instructions, commands, information, signals, bits, symbols, and chips that permeate the foregoing description can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, light fields or light particles, or any combination thereof. Some diagrams may illustrate signals as single signals; however, those skilled in the art will understand that the signals may represent a bus of signals, wherein the bus may have various bit widths.

[0122] The terms "electronic communication," "conductive contact," "connection," and "coupling" can refer to a relationship between components that supports the flow of signals between them. Components are considered to be in electronic communication with each other (or in conductive contact with each other, connected to each other, or coupled to each other) if any conductive path exists between them that can support the flow of signals between them at any given time. At any given time, the conductive path between components that are in electronic communication with each other (or in conductive contact with each other, connected to each other, or coupled to each other) can be open or closed depending on the operation of the device containing the connected component. The conductive path between connected components can be a direct conductive path between the components, or an indirect conductive path between connected components that may include intermediate components such as switches, transistors, or other components. In some instances, the signal flow between connected components can be interrupted for a period of time, for example, using one or more intermediate components such as switches or transistors.

[0123] The term "coupling" refers to a shift in conditions from an open-circuit relationship between components where signals cannot currently travel between components via conductive paths to a closed-circuit relationship where signals can travel between components via conductive paths. When a component, such as a controller, couples other components together, that component initiates a change that allows signals to flow between the other components via conductive paths that were previously not permitted.

[0124] The term "isolation" refers to a relationship between components under which a signal is currently unable to flow between them. If an open circuit exists between components, then those components are isolated from each other. For example, two components separated by a switch positioned between them are isolated from each other when the switch is open. When a controller isolates two components, the controller affects the change that prevents signals from flowing between the components using previously permitted conductive paths.

[0125] As used herein, the term "layer" or "level" refers to a hierarchy or sheet of geometry (e.g., relative to a substrate). Each layer or level may have three dimensions (e.g., height, width, and depth) and may cover at least a portion of a surface. For example, a layer or level may be a three-dimensional structure in which two dimensions are greater than the third, such as a thin film. A layer or level may contain different elements, components, and / or materials. In some instances, a layer or level may consist of two or more sublayers or sublevels.

[0126] As used in this article, the term “generally” means that the modified characteristic (e.g., a verb or adjective modified by the term “generally”) does not have to be an absolute value but is close enough to achieve the advantage of the characteristic.

[0127] As used herein, the term "electrode" can refer to an electrical conductor and, in some instances, can serve as an electrical contact with another component of a memory cell or memory array. Electrodes can include traces, wires, conductive lines, conductive layers, or the like that that provide a conductive path between elements or components of the memory array.

[0128] The device comprising the memory array discussed herein can be formed on semiconductor substrates such as silicon, germanium, silicon-germanium alloys, gallium arsenide, gallium nitride, etc. In some instances, the substrate is a semiconductor wafer. In other instances, the substrate can be an epitaxial layer of semiconductor material on a substrate such as silicon on glass (SOG) or silicon on sapphire (SOP), or another substrate. The conductivity of the substrate or subregions of the substrate can be controlled by doping with various chemical species including, but not limited to, phosphorus, boron, or arsenic. Doping can be performed during the initial formation or growth of the substrate by ion implantation or by any other doping method.

[0129] The switching components or transistors discussed herein may represent field-effect transistors (FETs) and include a three-terminal device comprising a source, a drain, and a gate. The terminals may be connected to other electronic components via a conductive material (e.g., a metal). The source and drain may be conductive and may comprise heavily doped (e.g., degenerate) semiconductor regions. The source and drain may be separated by lightly doped semiconductor regions or channels. If the channel is n-type (i.e., most carriers are signals), then the FET may be called an n-type FET. If the channel is p-type (i.e., most carriers are holes), then the FET may be called a p-type FET. The channel may be covered by an insulating gate oxide. The conductivity of the channel can be controlled by applying a voltage to the gate. For example, applying a positive or negative voltage to an n-type FET or a p-type FET, respectively, makes the channel conductive. When a voltage greater than or equal to the transistor's threshold voltage is applied to the transistor's gate, the transistor may be "on" or "on". When a voltage less than the transistor's threshold voltage is applied to the transistor's gate, the transistor may be "off" or "off-start".

[0130] The descriptions herein, illustrated in conjunction with the accompanying drawings, depict exemplary configurations and do not represent all instances that are implementable or within the scope of the claims. The term "exemplary" as used herein means "serving as an example, illustration, or description" and does not imply "preferred" or "superior to other instances." Detailed descriptions include specific details to provide an understanding of the described techniques. However, these techniques may be practiced without these specific details. In some cases, well-known structures and devices are shown in block diagram form to avoid obscuring the concept of the described instances.

[0131] In the accompanying drawings, similar components or features may have the same reference numerals. Additionally, various components of the same type can be distinguished by adding a dash after the reference numeral and a second numeral to differentiate between similar components. If only the first reference numeral is used in the specification, the description applies to any of the similar components that have the same first reference numeral but are independent of the second reference numeral.

[0132] The information and signals described herein can be represented using any of a variety of different techniques and skills. For example, data, instructions, commands, information, signals, bits, symbols, and chips that permeate the foregoing description can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, light fields or light particles, or any combination thereof.

[0133] The various illustrative blocks and modules described in connection with this invention may be implemented or performed by a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general-purpose processor may be a microprocessor, but in alternative examples, the processor may be any processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors incorporating a DSP core, or any other such configuration).

[0134] The functions described herein can be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions can be stored on or transmitted via a computer-readable medium as one or more instructions or code. Other examples and implementations are within the scope of this invention and the appended claims. For example, due to the nature of software, the functions described above can be implemented using software executed by a processor, hardware, firmware, hardwired, or any combination thereof. Features implementing the functions can also be physically located in various locations, including distributed so that portions of the functions are implemented in different physical locations. Furthermore, as used herein (included in the claims), “or” when used in a list of items (e.g., a list of items ending with phrases such as “at least one of” or “one or more of”) indicates an inclusive list such that, for example, a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Furthermore, as used herein, the phrase “based on” should not be considered a reference to a set of closing conditions. For example, an exemplary step described as "based on condition A" may be based on both condition A and condition B without departing from the scope of the invention. In other words, as used herein, the phrase "based on" should be interpreted in the same way as the phrase "at least partially based on".

[0135] Computer-readable media includes both non-transitory computer storage media and communication media, with communication media encompassing any medium that facilitates the transfer of a computer program from one place to another. Non-transitory storage media can be any available medium accessible by a general-purpose or special-purpose computer. By way of example, and not limitation, non-transitory computer-readable media may include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), compact optical disc (CD) ROM or other optical disc storage devices, magnetic disk storage devices or other magnetic storage devices, or any other non-transitory medium that can be used to carry or store desired program code components in the form of instructions or data structures and is accessible by a general-purpose or special-purpose computer, or a general-purpose or special-purpose processor. Furthermore, any connection is appropriately referred to as computer-readable media. For example, if software is transmitted from a website, server, or other remote source using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technology (e.g., infrared, radio, and microwave), then coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technology (e.g., infrared, radio, and microwave) is included in the definition of media. As used herein, disks and optical discs include CDs, laser discs, optical discs, digital versatile discs (DVDs), floppy disks, and Blu-ray discs, where disks typically reproduce data magnetically, while optical discs reproduce data optically using lasers. Combinations of these are also included within the scope of computer-readable media.

[0136] The description herein is provided to enable those skilled in the art to make or use the invention. Various modifications to the invention will be apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the scope of the invention. Therefore, the invention is not limited to the examples and designs described herein, but should be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method for fabricating a memory device, comprising: forming a stack of materials including a chalcogenide material for storing information and a conductive material; etching the stack of materials as part of an etch phase of a fabrication process to form a pillar, the etch phase comprising: etching the chalcogenide material using a first set of etch parameters to expose sidewalls of the chalcogenide material; depositing a first sealant material on the sidewalls of the chalcogenide material after or during etching at least a portion of the chalcogenide material to form a first liner; and etching the conductive material using a second set of etch parameters after depositing the first sealant material; depositing a third sealant material after etching the conductive material to repair the first liner coupled with the sidewalls of the chalcogenide material; and based at least in part on depositing the third sealant material, depositing a second sealant material over the pillar as part of a deposition phase occurring after the etch phase to form a second liner.

2. The method of claim 1, wherein depositing the first sealant material further comprises: depositing one or more elements configured to bond with the chalcogenide material to form the first liner.

3. The method of claim 2, wherein the one or more elements comprise a radical form or an ion or a reactive compound.

4. The method of claim 2, wherein the one or more elements comprise one or more halogen elements.

5. The method of claim 1, further comprising: cleaning the pillar using a wet cleaning process as part of a cleaning phase occurring after the etch phase, wherein depositing the second sealant material occurs after the cleaning phase.

6. The method of claim 5, wherein the first liner is configured to protect the chalcogenide material from reacting during the cleaning phase and the deposition phase occurring after the etch phase.

7. The method of claim 1, wherein the first liner is configured to protect the chalcogenide material from one or more processes used to etch subsequent materials as part of the etch phase.

8. The method of claim 1, wherein the etch phase comprises a dry etch process.

9. The method of claim 1, wherein the second liner comprises silicon nitride.

10. A method for fabricating a memory device, comprising: forming a stack of materials including a chalcogenide material for storing information and a conductive material; etching the stack of materials as part of an etch phase of a fabrication process to form a pillar, the etch phase comprising: etching the chalcogenide material using a first set of etch parameters to expose sidewalls of the chalcogenide material; depositing a first sealant material on the sidewalls of the chalcogenide material after etching the chalcogenide material to form a first liner; and altering a composition of the first liner using a substitution-based reaction as part of a phase occurring after the etch phase.

11. The method of claim 10, further comprising: depositing a second encapsulant material over the pillar as part of a deposition phase occurring after the etching phase to form a second liner, wherein altering the composition of the first liner occurs during the deposition phase and the phase comprises the deposition phase.

12. The method of claim 10, further comprising:

12. The method of claim 10, further comprising: cleaning the pillar using a wet clean process as part of a cleaning phase occurring after the etching phase, wherein altering the composition of the first liner occurs during the cleaning phase and the phase comprises the cleaning phase.

13. The method of claim 10, wherein depositing the first encapsulant material further comprises: oxidizing a surface of the sidewall of the chalcogenide material.

14. The method of claim 10, wherein the etching phase further comprises: etching the conductive material using a second set of etching parameters as part of the etching phase and after depositing the first encapsulant material, wherein altering the composition of the first liner is based at least in part on etching the conductive material.

15. The method of claim 10, wherein depositing the first encapsulant material further comprises: depositing one or more elements configured to bond with the chalcogenide material to form the first liner.

16. The method of claim 15, wherein the one or more elements comprise one or more ions.

17. A memory device, comprising: a pillar comprising a first electrode, a chalcogenide material coupled with the first electrode for storing information, and a second electrode coupled with the chalcogenide material; a first liner coupled with a sidewall of the chalcogenide material and extending between the first electrode and the second electrode; a second liner coupled with the first liner, the first electrode, and the second electrode of the pillar, the second liner being a different material than the first liner; a conductive line coupled with the first electrode of the pillar; and a thin layer positioned between the conductive line and the first electrode of the pillar.

18. A method for fabricating a memory device, comprising: forming a stack of materials comprising a chalcogenide material for storing information and a conductive material; etching the stack of materials as part of an etching phase of a fabrication process to form a pillar, the etching phase comprising: etching the chalcogenide material using a first set of etching parameters to expose a sidewall of the chalcogenide material; depositing a first encapsulant material on the sidewall of the chalcogenide material after etching the chalcogenide material to form a first liner; and etching the conductive material using a second set of etching parameters after depositing the first encapsulant material; and depositing a second encapsulant material after etching the conductive material to repair the first liner coupled with the sidewall of the chalcogenide material.

19. The method of claim 18, further comprising: cleaning the pillar using a wet clean process as part of a cleaning phase occurring after the etching phase.

20. The method of claim 19, wherein the first liner is configured to protect the chalcogenide material from reacting during the cleaning phase and other phases that occur after the etch phase.

21. The method of claim 18, wherein depositing the first sealant material further comprises: depositing one or more elements configured to bond with the chalcogenide material to form the first liner.

22. The method of claim 21, wherein the one or more elements comprise a radical form.

23. The method of claim 21, wherein the one or more elements comprise one or more halogen elements.

24. A method for fabricating a memory device, comprising: forming a stack of materials including a chalcogenide material for storing information and a conductive material; etching the stack of materials as part of an etch phase of a fabrication process to form a pillar, the etch phase comprising: etching the chalcogenide material using a first set of etch parameters to expose a sidewall of the chalcogenide material; depositing a first sealant material on the sidewall of the chalcogenide material after etching the chalcogenide material to form a first liner; and etching the conductive material using a second set of etch parameters after depositing the first sealant material; performing a re-etch process that removes at least a portion of the first liner after the etch phase; and depositing the first sealant material to repair the first liner after performing the re-etch process.

25. The method of claim 24, further comprising: cleaning the pillar using a wet cleaning process as part of a cleaning phase that occurs after the etch phase, wherein performing the re-etch process occurs after cleaning the pillar using the wet cleaning process.

26. The method of claim 24, further comprising: depositing a second sealant material over the pillar to form a second liner as part of a deposition phase that occurs after depositing the first sealant material to repair the first liner.

27. The method of claim 24, wherein depositing the first sealant material further comprises: depositing one or more elements configured to bond with the chalcogenide material to form the first liner.

28. The method of claim 24, wherein the first liner is configured to protect the chalcogenide material from one or more processes used to etch subsequent materials as part of the etch phase.

29. The method of claim 24, wherein the etch phase comprises a dry etch process.

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