Chip pin testing circuit and device

Abstract

The application discloses a chip pin test circuit and equipment, and relates to the technical field of integrated circuits.The circuit comprises a common resistance, a level output module and a connectivity test module; the first end of the common resistance is used as an IO port, and the second end of the common resistance is grounded; the first input end of the level output module is used for inputting a level control signal, and the output end of the level output module is connected with the IO port; the input end of the connectivity test module is used for inputting a switch control signal, the input and output ends of the connectivity test module are connected with the IO port, and the output end of the connectivity test module is used for outputting a test result.The chip pin test circuit and equipment disclosed by the application use the common resistance as the pull-down resistance of the level output module, and also use the common resistance as one of the connectivity branches of the connectivity test module, so that the circuit structure can be simplified, and the cost can be reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of integrated circuits, in particular to a chip pin testing circuit and device. BACKGROUND

[0002] With the development of integrated circuit technology, integrated circuit chips are applied to various industries. Before the integrated circuit chips are shipped, the chip pins of the integrated circuit chips need to be tested by using corresponding testing devices so as to remove defective products. However, the circuit structure of the current testing devices is relatively complex, resulting in high cost. SUMMARY

[0003] The present application aims to at least solve one of the problems in the prior art. To this end, the present application provides a chip pin testing circuit which can simplify the circuit.

[0004] The present application also provides a chip pin testing device comprising the chip pin testing circuit.

[0005] According to the chip pin testing circuit of the embodiment of the present application, the first end of the common resistor is used as an IO port, the second end of the common resistor is grounded, the first input end of the level output module is used for inputting a level control signal, the output end of the level output module is connected with the IO port, the input end of the continuity testing module is used for inputting a switch control signal, the input and output end of the continuity testing module is connected with the IO port, and the output end of the continuity testing module is used for outputting a test result.

[0006] According to the chip pin testing circuit of the embodiment of the present application, the IO port is used for connecting the chip pin, the level control signal is used for controlling the level output module to output a level driving signal to the chip pin, the continuity testing module is used for testing the continuity of the chip pin, the common resistor is used as a pull-down resistor of the level output module and a continuity branch of the continuity testing module, the level output module can output a driving level signal to the chip pin by making the level output module and the continuity testing module share the common resistor, the continuity testing module can test the continuity of the chip pin, and meanwhile, the number of components is reduced, the circuit structure is simplified, and the cost is reduced.

[0007] According to some embodiments of the present application, the connectivity test module comprises a signal detection unit, a signal generation unit and a switch control unit, an input end of the switch control unit serving as an input end of the connectivity test module, the switch control unit being configured to control the signal generation unit to output a test signal, an output end of the signal generation unit being connected to the IO port, an input end of the signal detection unit being connected to the IO port, and an output end of the signal detection unit serving as an output end of the connectivity test module, so as to facilitate the connectivity test module to test the chip pins.

[0008] According to some embodiments of the present application, the signal generation unit comprises a sine wave generation circuit, an output end of the sine wave generation circuit being connected to the IO port through the switch control unit, so as to facilitate the signal detection unit to output a corresponding waveform, thereby facilitating the connectivity of the chip pins to be confirmed.

[0009] According to some embodiments of the present application, the signal generation unit comprises a constant current source circuit, an output end of the constant current source circuit being connected to the IO port, and a control end of the constant current source being connected to a control end of the switch control unit, so as to facilitate the signal detection unit to output a corresponding voltage, thereby facilitating the connectivity of the chip pins to be confirmed.

[0010] According to some embodiments of the present application, the level control signal comprises a first level signal and a second level signal, the level output module comprises a first comparison unit, a second comparison unit and a NOR unit, a first input end of the first comparison unit being configured to input the first level signal, a second input end of the second comparison unit being configured to input the second level signal, a second input end of the first comparison unit and a first input end of the second comparison unit being configured to input a first reference voltage signal, a negative power supply end of the first comparison unit and a negative power supply end of the second comparison unit being configured to input a first voltage signal with a voltage amplitude less than zero, an output end of the first comparison unit being connected to a first input end of the NOR unit, an output end of the second comparison unit being connected to a second input end of the NOR unit, and an output end of the NOR unit being connected to the IO port, so as to output a corresponding drive level signal.

[0011] According to some embodiments of the present application, a positive power supply end of the first comparison unit is configured to input a second voltage signal, and a positive power supply end of the second comparison unit is configured to input a third voltage signal, the second voltage signal having an amplitude greater than or less than that of the third voltage signal, so as to realize a three-state logic output.

[0012] According to some embodiments of the present application, the chip pin testing device further comprises a logic receiving module, a first input end of the logic receiving module is connected with the IO port, a second input end of the logic receiving module is used for inputting a second reference voltage signal, and an output end of the logic receiving module is used for outputting a logic receiving result, so as to detect the logic output function of the chip pin.

[0013] According to some embodiments of the present application, the second reference voltage signal comprises a fourth voltage signal and a fifth voltage signal, the logic receiving result comprises a first receiving result and a second receiving result, the logic receiving module comprises a third comparison unit and a fourth comparison unit, a first input end of the third comparison unit and a first input end of the fourth comparison unit are both connected with the IO port, a second input end of the third comparison unit is used for inputting the fourth voltage signal, a second input end of the fourth comparison unit is used for inputting the fifth voltage signal, an output end of the third comparison unit is used for outputting the first receiving result, and an output end of the fourth comparison unit is used for outputting the second receiving result, so as to detect the logic output function of the chip pin.

[0014] According to some embodiments of the present application, the logic receiving module further comprises a first clamping unit and a second clamping unit, the output end of the third comparison unit outputs the first receiving result through the first clamping unit, and the output end of the fourth comparison unit is used for outputting the second receiving result through the second clamping unit, so as to limit the amplitude of the first receiving result and the second receiving result.

[0015] According to another aspect of the embodiments of the present application, a chip pin testing device comprises the chip pin testing circuit as described above.

[0016] Additional aspects and advantages of the present application will be in part apparent and in part pointed out hereinafter. BRIEF DESCRIPTION OF DRAWINGS

[0017] The above and / or additional aspects and advantages of the present application will become apparent and be readily appreciated from the following description, including the appended drawings.

[0018] Figure 1 A schematic diagram of a chip pin of an integrated circuit chip in the related art;

[0019] Figure 2 A circuit block diagram of a chip pin testing circuit according to an embodiment of the present application;

[0020] Figure 3 A circuit block diagram of a continuity testing module of the chip pin testing circuit shown in FIG. 4; Figure 2 A circuit block diagram of a continuity testing module of the chip pin testing circuit shown in FIG. 4;

[0021] Figure 4A circuit block diagram of a connectivity test module of a chip pin test circuit according to some embodiments of the present application;

[0022] Figure 5 A circuit block diagram of a chip pin test circuit according to some embodiments of the present application; Figure 2 A circuit block diagram of a chip pin test circuit according to some embodiments of the present application;

[0023] Figure 6 A circuit block diagram of a chip pin test circuit according to some embodiments of the present application; Figure 5

[0024] Figure 7 A circuit block diagram of a chip pin test circuit according to some embodiments of the present application;

[0025] Figure 8 A circuit block diagram of a chip pin test circuit according to some embodiments of the present application.

[0026] Reference signs are as follows:

[0027] Common resistance 100, level output module 200, line or unit 210, connectivity test module 300, signal detection unit 310, constant current source circuit 321, sine wave generation circuit 322, switch control unit 330, logic receiving module 400, first clamping unit 410, second clamping unit 420. DETAILED DESCRIPTION

[0028] Embodiments of the present application are described in detail below with reference to the accompanying drawings, in which examples of the embodiments are shown, wherein the same or similar reference signs represent the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and cannot be understood as a limitation of the present application.

[0029] In the description of the present application, it should be understood that the orientation description, such as the orientation or position relationship indicated by up, down, front, back, left, right, etc. is based on the orientation or position relationship shown in the drawings, and is only for the convenience of describing the present application and simplifying the description, and therefore cannot be understood as a limitation of the present application.

[0030] In the description of the present application, the meaning of several is one or more, the meaning of multiple is two and more than two, greater than, less than, more than, etc. are understood as not including the number, above, below, etc. are understood as including the number. If the first, second is described, it is only for the purpose of distinguishing technical features, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features or the order of indicated technical features.

[0031] ​In the description of the present application, unless otherwise explicitly defined, the words such as setting, installing, connecting and the like should be understood in a broad sense, and the person skilled in the art can determine the specific meaning of the above words in the present application in combination with the specific content of the technical solution.

[0032] High level refers to high voltage opposite to low level.

[0033] Low level refers to low voltage opposite to high level.

[0034] In the related art, referring to Figure 1 , a chip pin of an integrated circuit chip is provided with a first diode connected reversely to ground, that is, the anode of the first diode is connected to ground, and the cathode of the first diode is connected to the chip pin, for example, Figure 1 diode D7 in as the first diode.

[0035] Referring to Figure 2 , the chip pin test circuit provided by an embodiment of the present application comprises a common resistance 100, a level output module 200 and a connectivity test module 300; a first end of the common resistance 100 is used as an IO port, and a second end of the common resistance 100 is connected to ground; a first input end of the level output module 200 is used for inputting a level control signal, and an output end of the level output module 200 is connected to the IO port; an input end of the connectivity test module 300 is used for inputting a switch control signal, an input / output end of the connectivity test module 300 is connected to the IO port, and an output end of the connectivity test module 300 is used for outputting a test result.

[0036] The IO port is used for connecting the chip pin; the level control signal is used for controlling the level output module 200 to output a level driving signal to the chip pin; the connectivity test module 300 is used for testing the connectivity of the chip pin; the common resistance 100 is used as a pull-down resistance of the level output module 200, so that the output end of the level output module 200 has a stable level state; the common resistance 100 is also used as one of the connectivity branches of the connectivity test module 300, and during the connectivity test, based on whether the chip pin is faulty, the voltage received by the common resistance 100 is also different, so as to output a corresponding test result. By making the level output module 200 and the connectivity test module 300 share the common resistance 100, the level output module 200 can output a driving level signal to the chip pin, the connectivity test module 300 can test the connectivity of the chip pin, at the same time, it is beneficial to reduce the number of components, thereby being beneficial to simplify the circuit structure and reduce the cost, in addition, it is also convenient to integrate the level output module 200 and the connectivity test module 300 into one, and convenient to miniaturization and use.

[0037] It should be noted that referring to Figure 1 and Figure 2In the embodiment, the input and output of the connectivity test module 300 is connected with the IO port, and the chip pin to be tested is connected with the IO port. When the connectivity of the chip pin is normal, the chip pin and the IO port are connected, and a connectivity branch is formed between the chip pin and the IO port. The connectivity branch is connected with the common resistance 100 in parallel, and the voltage is loaded on the first diode and the common resistance 100. The IO port is in the first voltage state, and the connectivity test module 300 can output the first voltage state as the test result. When the connectivity of the chip pin is abnormal, the chip pin and the IO port are disconnected, and no connectivity branch is formed between the chip pin and the IO port. The voltage is loaded on the common resistance 100, the IO port is in the second voltage state, and the connectivity test module 300 can output the second voltage state as the test result. By taking the common resistance 100 as one of the connectivity branches of the connectivity test module 300, the IO port can be in the first voltage state or the second voltage state, and the connectivity test module 300 outputs the corresponding test result.

[0038] With reference to Figure 3 Or Figure 4 The connectivity test module 300 includes a signal detection unit 310, a signal generation unit (not shown in the figure) and a switch control unit 330. The input of the switch control unit 330 is the input of the connectivity test module 300. The switch control unit 330 is used to control the signal generation unit to output the test signal. The output of the signal generation unit is connected with the IO port. The input of the signal detection unit 310 is connected with the IO port. The output of the signal detection unit 310 is the output of the connectivity test module 300. The signal generation unit is used to generate the test signal for testing the chip pin, such as the sine wave and the constant current. The switch control unit 330 is used to control the signal generation unit to output the test signal. The signal detection unit 310 is used to detect the voltage state of the IO port.

[0039] When the connectivity test of the chip pin is needed, the switch control unit 330 makes the signal generation unit output the corresponding test signal, and the test signal passes through the chip pin or the common resistance 100, so that the IO port is in the first voltage state or the second voltage state, and the signal detection unit 310 outputs the corresponding test result, and the connectivity test is completed.

[0040] With reference to Figure 6 , Figure 7 Or Figure 8The signal detection unit 310 comprises a comparator U5, a resistor R3, a resistor R6 and a resistor R7, a first end of the resistor R3 is grounded, a second end of the resistor R3 is connected with a non-inverting input terminal of the comparator U5, a first end of the resistor R6 is connected with an output terminal of the comparator U5, a second end of the resistor R6 is connected with an inverting input terminal of the comparator U5, the output terminal of the comparator U5 is an output terminal of the signal detection unit 310, a first end of the resistor R7 is an input terminal of the signal detection unit 310, and a second end of the resistor R7 is connected with the non-inverting input terminal of the comparator U5 or the inverting input terminal of the comparator U5. Wherein, the comparator U5 obtains the voltage state of the IO port through the resistor R7, when the second end of the resistor R7 is connected with the inverting input terminal of the comparator U5, the comparator U5 outputs the voltage state after inverting as the test result; when the second end of the resistor R7 is connected with the non-inverting input terminal of the comparator U5, the comparator U5 outputs the voltage state as the test result.

[0041] With reference to Figure 3 and Figure 6 With a specific example, the signal generation unit comprises a constant current source circuit 321, an output terminal of the constant current source circuit 321 is connected with the IO port, and a controlled end of the constant current source is connected with a control terminal of the switch control unit 330.

[0042] Specifically, the constant current source circuit 321 comprises a transistor Q1, a transistor Q2 and a resistor R8, a collector of the transistor Q1 is an output terminal of the constant current source circuit 321, a base of the transistor Q1 is connected with a base of the transistor Q2, a collector of the transistor Q2 and a first end of the resistor R8 respectively, a second end of the resistor R8 is grounded, and an emitter of the transistor Q1 and an emitter of the transistor Q2 are both used for inputting a sixth voltage signal.

[0043] The switch control unit 330 comprises a transistor Q3, a transistor Q4, a resistor R9, a resistor R10 and a resistor R11, an emitter of the transistor Q4 is used for inputting a seventh voltage signal, a base of the transistor Q4 is connected with a first end of the resistor R11, a second end of the resistor R11 is used for inputting a switch control signal, a collector of the transistor Q4 is connected with a first end of the resistor R10 and a first end of the resistor R9, a second end of the resistor R9 is connected with a base of the transistor Q3, an emitter of the transistor Q3 and a second end of the resistor R10 are both used for inputting the sixth voltage signal, and a collector of the transistor Q3 is connected with a first end of the resistor R8.

[0044] The amplitude of the sixth voltage signal can be-5V, and the amplitude of the seventh voltage signal can be 3.3V. The output end of the constant current source circuit 321 is used to output a constant current. When the switch control signal is a low-level signal, the triode Q3 and the triode Q4 are turned on, the triode Q1 and the triode Q2 are turned off, and the collector of the triode Q1 is in a high resistance state. At this time, the constant current source circuit 321 is closed by the switch control unit 330, and the constant current is stopped from being output. At this time, the connectivity test module 300 stops working. When the switch control signal is a high-level signal, the triode Q3 and the triode Q4 are turned off, the triode Q1 and the triode Q2 are turned on, and the constant current flowing through the collector of the triode Q2 is the same as the constant current flowing through the collector of the triode Q1.

[0045] When the constant current source circuit 321 can output a constant current, and the connectivity of the chip pin is normal, the constant current can flow from the anode of the first diode, i.e. the ground end, to the emitter of the triode Q1 through the cathode of the first diode and the collector of the triode Q1 in sequence. In this example, the voltage amplitude of the emitter of the triode Q1 is-5V, and the voltage drop of the first diode can be between 0.4V and 0.8V. Therefore, the voltage amplitude of the input end of the signal detection unit 310 is between-0.8V and-0.4V.

[0046] When the constant current source circuit 321 can output a constant current, and the connectivity of the chip pin is abnormal, the constant current can flow from the second end of the common resistance 100, i.e. the ground end, to the emitter of the triode Q1 through the first end of the common resistance 100 and the collector of the triode Q1 in sequence. In this example, the voltage amplitude of the emitter of the triode Q1 is-5V, and the constant current flowing through the common resistance 100 will generate a large voltage drop on the common resistance 100, for example, a voltage drop of 4.9V. Therefore, the voltage amplitude of the first end of the common resistance 100 is less than-0.8V and close to-5V, so that the voltage amplitude of the input end of the signal detection unit 310 is between-5V and-0.8V.

[0047] In the above example, the signal detection unit 310 can output the input in reverse. That is, when the test result output by the output end of the signal detection unit 310 is between 0.4V and 0.8V, the connectivity of the chip pin is normal, and when the test result output by the output end of the signal detection unit 310 is between 0.8V and 5V, the connectivity of the chip pin is abnormal. In the above example, the circuit structure of the connectivity test module 300 is simple, and the common resistance 100 can be shared with the level output module 200, so as to use the common resistance 100 as one of the connectivity branches of the connectivity test module 300, which is beneficial to simplify the circuit and reduce the cost.

[0048] Referring to Figure 4 and Figure 7With another specific example, the signal generating unit includes a sine wave generating circuit 322, and an output end of the sine wave generating circuit 322 is connected with the IO port through the switch control unit 330.

[0049] Specifically, the switch control unit 330 includes a relay K1, a transistor Q5 and a resistor R12, a base of the transistor Q5 is connected with a first end of the resistor R12, a second end of the resistor R12 is used for inputting a switch control signal, an emitter of the transistor Q5 is grounded, a collector of the transistor Q5 is connected with a first end of a coil of the relay K1, a second end of the coil of the relay K1 is used for connecting a power supply, a first end of a switch of the relay K1 is connected with an output end of the sine wave generating circuit 322, and a second end of the switch of the relay K1 is connected with the IO port.

[0050] The sine wave generating circuit 322 is used for generating a sine wave signal; when the switch control signal is a low-level signal, the switch of the relay K1 is opened, and the continuity test module 300 stops working; when the switch control signal is a high-level signal, the switch of the relay K1 is closed, and the sine wave signal generated by the sine wave generating circuit 322 can be loaded to the chip pin, and the continuity test module 300 normally works.

[0051] When the continuity test module 300 normally works and the continuity of the chip pin is normal, in a positive half cycle of the sine wave signal, the sine wave signal flows from the output end of the sine wave generating circuit 322, through the first end of the switch of the relay K1, the second end of the switch of the relay K1 and the first end of the common resistor 100, to the second end of the common resistor 100, at this time, the input end of the signal detection unit 310 inputs the positive half cycle of the sine wave; in a negative half cycle of the sine wave signal, the sine wave signal flows from the positive pole of the first diode, i.e. the ground end, through the negative pole of the first diode, the second end of the switch of the relay K1 and the first end of the switch of the relay K1, to the output end of the sine wave generating circuit 322, at this time, since the voltage drop of the first diode is small, the voltage amplitude of the first diode is close to the voltage amplitude of the ground end, i.e. the voltage amplitude of the first diode is close to zero, and thus the voltage amplitude of the input end of the signal detection unit 310 is close to zero.

[0052] When the connectivity test module 300 is working normally, and the connectivity of the chip pin is abnormal, in the negative half cycle of the sine wave signal, the flow path of the sine wave signal changes, the sine wave signal flows from the second end of the common resistance 100, i.e. the ground end, to the output end of the sine wave generation circuit 322 through the first end of the common resistance 100, the second end of the switch of the relay K1, and the first end of the switch of the relay K1 in turn. At this time, due to the large voltage drop of the common resistance 100, the voltage amplitude at the first end of the common resistance 100 is close to the voltage amplitude at the output end of the sine wave generation circuit 322, and the input end of the signal detection unit 310 inputs the negative half cycle of the sine wave, i.e. the signal detection unit 310 can output a complete sine wave in one cycle of the sine wave signal.

[0053] It should be noted that in some embodiments, with reference to Figure 8 , the above-mentioned relay K1 can be replaced by an analog switch M1.

[0054] In the above example, the signal detection unit 310 can output the input in phase, i.e. when the output end of the signal detection unit 310 outputs the positive half cycle of the sine wave in the positive half cycle of the sine wave signal, and the voltage amplitude of the output is close to zero or the voltage amplitude of the output is zero in the negative half cycle of the sine wave signal, the connectivity of the chip pin is normal; when the output end of the signal detection unit 310 outputs a complete sine wave in one cycle of the sine wave signal, the connectivity of the chip pin is abnormal. In the above example, the circuit structure of the connectivity test module 300 is simple, and the common resistance 100 can be shared with the level output module 200, so as to use the common resistance 100 as one of the connectivity branches of the connectivity test module 300, which is beneficial to simplify the circuit and reduce the cost.

[0055] With reference to Figure 6 , Figure 7 or Figure 8 , the level control signal includes a first level signal and a second level signal, and the level output module 200 includes a first comparison unit (not shown in the figure), a second comparison unit (not shown in the figure), and a line or unit 210, the first input end of the first comparison unit is used for inputting the first level signal, the second input end of the second comparison unit is used for inputting the second level signal, the second input end of the first comparison unit and the first input end of the second comparison unit are used for inputting the first reference voltage signal, the negative power supply end of the first comparison unit and the negative power supply end of the second comparison unit are used for inputting the first voltage signal with a voltage amplitude less than zero, the output end of the first comparison unit is connected with the first input end of the line or unit 210, the output end of the second comparison unit is connected with the second input end of the line or unit 210, and the output end of the line or unit 210 is connected with the IO port.

[0056] The first level signal is used to control the output of the first comparison unit, and the second level signal is used to control the output of the second comparison unit; and the line or unit 210 is used to perform line or processing on the output of the first comparison unit and the output of the second comparison unit to obtain the level driving signal.

[0057] When the positive power supply end of the first comparison unit and the positive power supply end of the second comparison unit input the same voltage signal, and the voltage signal can be used as a low level signal, the output end of the line or unit 210 can output a low level signal, or the output end of the line or unit 210 can be in a high resistance state; when the positive power supply end of the first comparison unit and the positive power supply end of the second comparison unit input the same voltage signal, and the voltage signal can be used as a high level signal, the output end of the line or unit 210 can output a high level signal, or the output end of the line or unit 210 can be in a high resistance state.

[0058] The level output module 200 is used to make the IO port in a high resistance state, or make the IO port output a high level signal or a low level signal, so as to test the logic function of the chip pin, and the level output module 200 and the connectivity test module 300 share the common resistance 100, so that the common resistance 100 is used as a pull-down resistance when the level output module 200 works, which is beneficial to simplify the circuit structure and reduce the cost.

[0059] It should be noted that the first reference voltage signal is used as the reference voltage of the first comparison unit and the second comparison unit, and the first reference voltage signal is used to compare with the input first level signal or the second level signal; the voltage amplitude of the first reference voltage signal is less than zero; the absolute value of the voltage amplitude of the first reference voltage signal is greater than the voltage amplitude of the low level signal and less than the voltage amplitude of the high level signal.

[0060] The first comparison unit and the second comparison unit can both use a voltage comparator, for example, referring to Figures 6 to 8 The voltage comparator U1 is used as the first comparison unit, and the voltage comparator U2 is used as the second comparison unit; the first input end of the first comparison unit can be used as the non-inverting input end of the first comparison unit, or can be used as the inverting input end of the first comparison unit; the second input end of the second comparison unit can be used as the non-inverting input end of the second comparison unit, or can be used as the inverting input end of the second comparison unit; when the first input end of the first comparison unit is used as the non-inverting input end of the first comparison unit, the second input end of the second comparison unit can also be used as the non-inverting input end of the second comparison unit; when the first input end of the first comparison unit is used as the inverting input end of the first comparison unit, the second input end of the second comparison unit can also be used as the inverting input end of the second comparison unit.

[0061] It should be noted that the first comparison unit and the second comparison unit can also use integrated chips with comparison functions, such as integrated chips such as LM324, LM339, or LM393.

[0062] Referring to Figures 6 to 8 , the positive power supply end of the first comparison unit is used to input the second voltage signal, and the positive power supply end of the second comparison unit is used to input the third voltage signal. The voltage amplitude of the second voltage signal is greater than or less than the voltage amplitude of the third voltage signal. Among them, the voltage amplitude of the second voltage signal is not the same as the voltage amplitude of the third voltage signal, so as to make the line or unit 210 can output high level signal or low level signal.

[0063]

[0064] Table 1

[0065] For example, referring to the above table 1, in table 1, the voltage amplitude of the second voltage signal is greater than the voltage amplitude of the third voltage signal, and the second voltage signal can be as a high level signal, and the third voltage signal can be as a low level signal. The line or unit 210 can output high level signal or low level signal, or the output end of the line or unit 210 can be in high resistance state.

[0066] By making the output end voltage state of the line or unit 210 can be switched between high level, low level and high resistance state, so as to realize the output of three state logic of IO port, so as to drive the chip pin to be in high level state, low level state or high resistance state, so as to test the logic function of the chip pin.

[0067] It should be noted that, referring to Figure 6 and Figure 7 , the line or unit 210 includes diode D1 and diode D2, the anode of diode D1 as the first input end of the line or unit 210, the anode of diode D2 as the second input end of the line or unit 210, the cathode of diode D1 and the cathode of diode D2 are connected, and the cathode of diode D1 and the cathode of diode D2 are connected. The cathode of diode D2 is used as the output end of the line or unit 210.

[0068] It should be noted that, referring to Figure 8In some embodiments, the line or unit 210 includes a transistor Q6 and a transistor Q7, a base of the transistor Q6 is connected with a collector of the transistor Q6, and the base of the transistor Q6 and the collector of the transistor Q6 are collectively as a first input terminal of the line or unit 210, a base of the transistor Q7 is connected with a collector of the transistor Q7, and the base of the transistor Q7 and the collector of the transistor Q7 are collectively as a second input terminal of the line or unit 210, an emitter of the transistor Q6 is connected with an emitter of the transistor Q7, and the emitter of the transistor Q6 and the emitter of the transistor Q7 are collectively as an output terminal of the line or unit 210.

[0069] With reference to Figure 5 , the chip pin test circuit further includes a logic receiving module 400, a first input terminal of the logic receiving module 400 is connected with the IO port, a second input terminal of the logic receiving module 400 is used for inputting a second reference voltage signal, and an output terminal of the logic receiving module 400 is used for outputting a logic receiving result. Wherein, the logic receiving module 400 is used for receiving a logic signal output by the chip pin and outputting the logic receiving result, and the logic receiving result is used for indicating a voltage state of the chip pin; specifically, a signal input by the first input terminal of the logic receiving module 400 is compared with the second reference voltage signal input by the second input terminal of the logic receiving module 400, and a comparison result obtained is as the logic receiving result. The logic signal is converted into the logic receiving result by the logic receiving module 400, so as to facilitate detection of the voltage state of the chip pin. In addition, the common resistance 100 can be used as a voltage dividing resistance of the logic receiving module 400, which is conducive to simplifying the circuit structure and reducing the cost.

[0070] It should be noted that the voltage state of the chip pin can be a high level state, a low level state or a high resistance state. Before detecting the voltage state of the chip pin by the logic receiving module 400, the output terminal of the level output module 200 is in a high resistance state under the control of the level control signal, so that the voltage state of the input terminal of the logic receiving module 400 is determined by the voltage state of the chip pin.

[0071] With reference to Figures 6 to 8 , the second reference voltage signal includes a fourth voltage signal and a fifth voltage signal, the logic receiving result includes a first receiving result and a second receiving result, and the logic receiving module 400 includes a third comparison unit (not shown in the figure) and a fourth comparison unit (not shown in the figure), a first input terminal of the third comparison unit and a first input terminal of the fourth comparison unit are both connected with the IO port, a second input terminal of the third comparison unit is used for inputting the fourth voltage signal, a second input terminal of the fourth comparison unit is used for inputting the fifth voltage signal, an output terminal of the third comparison unit is used for outputting the first receiving result, and an output terminal of the fourth comparison unit is used for outputting the second receiving result.

[0072] The third comparison unit is configured to compare the fourth voltage signal and the logic signal output by the chip pin to obtain and output a first receiving result; and the fourth comparison unit is configured to compare the fifth voltage signal and the logic signal output by the chip pin to obtain and output a second receiving result. The first receiving result is used to indicate a comparison result between the fourth voltage signal and the logic signal output by the chip pin; the second receiving result is used to indicate a comparison result between the fifth voltage signal and the logic signal output by the chip pin; and the first receiving result and the second receiving result constitute a logic receiving result, so that the logic receiving result can indicate the voltage state of the chip pin, i.e., the logic receiving result indicates that the voltage state of the chip pin is a high level state, a low level state or a high impedance state.

[0073]

[0074] Table 2

[0075] Referring to Figure 6 and Table 2, OUT1 represents the first receiving result in Table 2, and OUT2 represents the second receiving result in Table 2.

[0076] In addition, the common resistance 100 can be used as a voltage dividing resistance of the third comparison unit and the fourth comparison unit, which is beneficial to simplify the circuit structure and reduce the cost.

[0077] It should be noted that the third comparison unit and the fourth comparison unit can both be voltage comparators, for example, referring to Figures 6 to 8 , the voltage comparator U3 is used as the third comparison unit, and the voltage comparator U4 is used as the fourth comparison unit; or the third comparison unit and the fourth comparison unit can be integrated chips with comparison functions, such as integrated chips LM324, LM339 or LM393.

[0078] Referring to Figures 6 to 8The logic receiving module 400 further comprises a first clamping unit 410 and a second clamping unit 420, the output end of the third comparison unit outputs a first receiving result through the first clamping unit 410, and the output end of the fourth comparison unit is used for outputting a second receiving result through the second clamping unit 420. The first clamping unit 410 is used for clamping the output of the third comparison unit, so that the voltage amplitude of the first receiving result is located in a suitable voltage range, so as to avoid that the voltage amplitude of the first receiving result is too high, for example, the voltage amplitude of the first receiving result is located in 3.3V; the second clamping unit 420 is used for clamping the output of the fourth comparison unit, so that the voltage amplitude of the second receiving result is located in a suitable voltage range, so as to avoid that the voltage amplitude of the second receiving result is too high, for example, the voltage amplitude of the second receiving result is located in 3.3V. Through the first clamping unit 410 and the second clamping unit 420, the voltage amplitude of the first clamping unit 410 and the voltage amplitude of the second clamping unit 420 are located in a suitable voltage range, so that subsequent circuit modules can be accessed according to actual needs to read the logic receiving result, that is, to avoid that the voltage amplitude of the logic receiving result is too high and damages the subsequent circuit modules accessed according to actual needs.

[0079] It should be noted that, referring to Figure 6 and Figure 7 , the first clamping unit 410 comprises a diode D3 and a resistor R1, the first end of the resistor R1 is used for inputting a clamping voltage, the second end of the resistor R1 is connected with the anode of the diode D3, the cathode of the diode D3 is connected with the output end of the third comparison unit, and the second end of the resistor R1 and the anode of the diode D3 are used as the output end of the first clamping unit 410, and the circuit structure of the second clamping unit 420 can be the same as that of the first clamping unit 410. The clamping voltage can be 3.3V or 5V, etc.

[0080] It should be noted that, referring to Figure 8 In some embodiments, the first clamping unit 410 comprises a triode Q8 and a resistor R13, the first end of the resistor R13 is used for inputting a clamping voltage, the second end of the resistor R13 is connected with the base of the triode Q8 and the collector of the triode Q8, and the second end of the resistor R13 is used as the output end of the first clamping unit 410, the emitter of the triode Q8 is connected with the output end of the third comparison unit, and the circuit structure of the second clamping unit 420 can be the same as that of the first clamping unit 410.

[0081] Another aspect of the embodiment of the present application provides a chip pin test device comprising the chip pin test circuit.

[0082] The contents in the chip pin test circuit embodiment are applicable to the chip pin test device embodiment, the chip pin test device embodiment specifically implements the same functions as the chip pin test circuit embodiment specifically implements, and achieves the same beneficial effects as the chip pin test circuit embodiment achieves.

[0083] The embodiments of the present application are described in detail above with reference to the drawings, but the present application is not limited to the above-described embodiments, and various changes can be made within the knowledge of those skilled in the art without departing from the spirit of the present application.

Claims

1. A chip pin testing circuit, characterized in that, include: A common resistor, the first end of which serves as an I / O port, and the second end of which is grounded; A level output module, wherein the first input terminal of the level output module is used to input a level control signal, and the output terminal of the level output module is connected to the IO port; A connectivity test module, wherein the input terminal of the connectivity test module is used to input switch control signals, the input and output terminals of the connectivity test module are connected to the IO port, and the output terminal of the connectivity test module is used to output test results; The connectivity test module includes a signal detection unit, a signal generation unit, and a switch control unit. The input terminal of the switch control unit serves as the input terminal of the connectivity test module. The switch control unit is used to control the signal generation unit to output a test signal. The output terminal of the signal generation unit is connected to the I / O port. The input terminal of the signal detection unit is connected to the I / O port. The output terminal of the signal detection unit serves as the output terminal of the connectivity test module. The signal generation unit includes a constant current source circuit or a sine wave generation circuit; When the signal generation unit includes a constant current source circuit, the constant current source circuit includes transistors Q1 and Q2 and resistor R8. The collector of transistor Q1 serves as the output terminal of the constant current source circuit. The base of transistor Q1 is connected to the base of transistor Q2, the collector of transistor Q2, and the first terminal of resistor R8, respectively. The second terminal of resistor R8 is grounded. The emitters of transistors Q1 and Q2 are both used to input a sixth voltage signal. The switch control unit includes transistors Q3 and Q4 and resistor R9. Resistors R10 and R11 are used. The emitter of transistor Q4 is used to input the seventh voltage signal. The base of transistor Q4 is connected to the first end of resistor R11. The second end of resistor R11 is used to input the switch control signal. The collector of transistor Q4 is connected to the first ends of resistor R10 and resistor R9. The second end of resistor R9 is connected to the base of transistor Q3. The emitter of transistor Q3 and the second end of resistor R10 are both used to input the sixth voltage signal. The collector of transistor Q3 is connected to the first end of resistor R8. When the signal generation unit includes a sine wave generating circuit, the output terminal of the sine wave generating circuit is connected to the IO port through the switch control unit. The switch control unit includes a relay K1, a transistor Q5, and a resistor R12. The base of the transistor Q5 is connected to the first end of the resistor R12, and the second end of the resistor R12 is used to input a switch control signal. The emitter of the transistor Q5 is grounded, and the collector of the transistor Q5 is connected to the first end of the coil of the relay K1. The second end of the coil of the relay K1 is used to connect to the power supply. The first end of the switch of the relay K1 is connected to the output terminal of the sine wave generating circuit 322, and the second end of the switch of the relay K1 is connected to the IO port.

2. The chip pin testing circuit according to claim 1, characterized in that, The level control signal includes a first level signal and a second level signal. The level output module includes a first comparison unit, a second comparison unit, and a line-or-interchange unit. The first input terminal of the first comparison unit is used to input the first level signal, and the second input terminal of the second comparison unit is used to input the second level signal. Both the second input terminal of the first comparison unit and the first input terminal of the second comparison unit are used to input a first reference voltage signal. Both the negative power supply terminal of the first comparison unit and the negative power supply terminal of the second comparison unit are used to input a first voltage signal with a voltage amplitude less than zero. The output terminal of the first comparison unit is connected to the first input terminal of the line-or-interchange unit, the output terminal of the second comparison unit is connected to the second input terminal of the line-or-interchange unit, and the output terminal of the line-or-interchange unit is connected to the IO port.

3. The chip pin testing circuit according to claim 2, characterized in that, The positive power supply terminal of the first comparison unit is used to input a second voltage signal, and the positive power supply terminal of the second comparison unit is used to input a third voltage signal. The voltage amplitude of the second voltage signal is greater than or less than the voltage amplitude of the third voltage signal.

4. The chip pin testing circuit according to claim 1, characterized in that, It also includes a logic receiving module, the first input terminal of which is connected to the IO port, the second input terminal of which is used to input a second reference voltage signal, and the output terminal of which is used to output the logic receiving result.

5. The chip pin testing circuit according to claim 4, characterized in that, The second reference voltage signal includes a fourth voltage signal and a fifth voltage signal. The logic reception result includes a first reception result and a second reception result. The logic reception module includes a third comparison unit and a fourth comparison unit. The first input terminal of the third comparison unit and the first input terminal of the fourth comparison unit are both connected to the IO port. The second input terminal of the third comparison unit is used to input the fourth voltage signal. The second input terminal of the fourth comparison unit is used to input the fifth voltage signal. The output terminal of the third comparison unit is used to output the first reception result. The output terminal of the fourth comparison unit is used to output the second reception result.

6. The chip pin testing circuit according to claim 5, characterized in that, The logic receiving module further includes a first clamping unit and a second clamping unit. The output of the third comparison unit outputs the first receiving result through the first clamping unit, and the output of the fourth comparison unit is used to output the second receiving result through the second clamping unit.

7. A chip pin testing device, characterized in that, Includes a chip pin test circuit as described in any one of claims 1 to 6.

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