EUV photomask manufacturing method

Abstract

This invention provides a method for manufacturing an EUV photomask. A neutral beam atomic layer etching (NBE) process is used at least at room temperature to etch an absorption layer to form a first pattern, minimizing thermal stress-induced defects and reducing plasma-induced damage during etching, thereby reducing defects in the final EUV photomask. Further, a room-temperature jet vapor deposition (JVDC) process is used to form reflective film stacks and absorption layers on the EUV photomask preform, further minimizing thermal stress-induced defects. In addition, a combination of room-temperature NBE, JVDC, and organic solvent removal of the photoresist layer can minimize thermal stress-induced defects and eliminate plasma-induced damage to the greatest extent possible, thus reducing defects on the EUV photomask to a minimum.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit manufacturing technology, and in particular to a method for manufacturing an EUV photomask. Background Technology

[0002] With the continuous development of the integrated circuit manufacturing industry, advanced lithography technologies such as extreme ultraviolet lithography (EUVL) have been widely used. Among these, the EUV photomask is a crucial component in the lithography process. The lithography process typically involves first coating a photoresist layer, such as photoresist, onto the wafer surface. After the photoresist layer dries, the pattern on the EUV photomask is exposed onto the photoresist layer using a specific light source (e.g., extreme ultraviolet light, EUV) through an exposure device. Subsequently, the exposed photoresist layer is developed with a developer. The developed photoresist pattern is then used as a mask to perform etching and other processes on the wafer, ultimately transferring the pattern from the EUV photomask to the wafer.

[0003] Therefore, it is crucial to manufacture EUV photomasks with low defects and high performance. Summary of the Invention

[0004] The purpose of this invention is to provide a method for manufacturing an EUV photomask that can produce a low-defect, high-performance EUV photomask.

[0005] To achieve the above objectives, the present invention provides a method for manufacturing an EUV photomask, comprising:

[0006] Fabricate an EUV mask preform and form a patterned hard mask layer on the EUV mask preform;

[0007] Using the patterned hard mask layer as a mask, the EUV mask preform is etched at room temperature using a first neutral beam atomic layer etching process to form a first pattern in the EUV mask preform.

[0008] Optionally, the step of forming a patterned hard mask layer on the EUV mask blank includes:

[0009] A hard mask layer is deposited on the EUV mask preform and a first photoresist layer is coated on it;

[0010] The first photoresist layer is exposed and developed to pattern the first photoresist layer;

[0011] Using the patterned first photoresist layer as a mask, the hard mask layer is etched to the top surface of the EUV mask blank at room temperature using a second neutral beam atomic layer etching process, and the first photoresist layer is removed at room temperature to form a patterned hard mask layer.

[0012] Optionally, the step of removing the first photoresist layer at room temperature includes: first peeling off the first photoresist layer with an organic solvent at room temperature, and then rinsing it with deionized water by spraying.

[0013] Optionally, the EUV mask preform includes a reflective film stack layer, a capping layer, and an absorption layer sequentially stacked on a first surface of the substrate. The reflective film stack layer includes alternating layers of a first reflective film and a second reflective film. The first pattern is formed in the absorption layer or in the absorption layer and the capping layer.

[0014] Optionally, at least one of the layers of the reflective film stack, the capping layer, the absorbing layer, and the hard mask layer is formed using a jet vapor deposition process at room temperature.

[0015] Optionally, after forming the first pattern, the method for manufacturing the EUV photomask further includes:

[0016] A second photoresist layer is coated on the hard mask layer and the EUV mask blank, and the second photoresist layer is exposed and developed to pattern the second photoresist layer.

[0017] Using the patterned second photoresist layer as a mask, the hard mask layer and the EUV mask blank surrounding the first pattern are etched at room temperature using a third neutral beam atomic layer etching process. The etching stops on the first surface of the substrate to form a second pattern in the EUV mask blank.

[0018] Remove the second photoresist layer at room temperature.

[0019] Optionally, the step of removing the second photoresist layer at room temperature includes: first peeling off the second photoresist layer with an organic solvent at room temperature, and then rinsing with deionized water by spraying.

[0020] Optionally, the material of the first reflective film includes molybdenum, the material of the second reflective film includes silicon, the number of layers of the first reflective film in the reflective film stack layer is 30 to 60, the material of the cover layer includes at least one of ruthenium, ruthenium alloy and ruthenium oxide, the absorber layer is a composite structure of single-layer film or multi-layer film stack, the material of the absorber layer includes tantalum-based material and / or chromium-based material, and the material of the hard mask layer includes chromium-based material or silicon-based material.

[0021] Optionally, the EUV mask preform further includes a back conductive layer formed on the second surface of the substrate.

[0022] Optionally, the back conductive layer is formed using a jet vapor deposition process at room temperature.

[0023] Compared with the prior art, the technical solution of the present invention has at least one of the following beneficial effects:

[0024] 1. At least at room temperature, use Neutral Beam Atomic Layer Etching (NB-ALE) to etch the EUV mask preform to form a first pattern. This minimizes thermal stress-induced defects and reduces plasma-induced damage during etching, thereby improving the charge effect and UV damage to the pattern edges of the reflective film stack and absorber layers. It also improves the uniformity, profile, symmetry, and smoothness of the pattern's critical dimension (CD), thus reducing defects in the final EUV photomask.

[0025] 2. Further, a jet vapor deposition (JVD) process at room temperature is used to form reflective film stacks and absorber layers to minimize thermal stress-induced defects.

[0026] 3. Further, photoresist stripping is performed at room temperature using organic solvents to minimize thermal stress-induced defects and eliminate plasma-induced damage to the greatest extent possible.

[0027] 4. Neutral beam atomic layer etching, jet vapor deposition, organic solvent removal of photoresist layer, and etching and photoresist removal performed at room temperature, compared with existing EUV photomask manufacturing methods, have optimized process parameters and improved the uniformity of key dimensions, topography, symmetry, and smoothness of pattern edges. The combination of these techniques can minimize the degree of defects in the final EUV photomask. Attached Figure Description

[0028] Figure 1 This is a schematic diagram of the cross-sectional structure of an existing EUV photomask.

[0029] Figure 2 This is a flowchart of a method for manufacturing an EUV photomask according to the first embodiment of the present invention.

[0030] Figures 3 to 7 This is a cross-sectional structural diagram of the manufacturing method of the EUV photomask according to the first specific embodiment of the present invention.

[0031] Figure 8 This is a simplified structural diagram of the equipment used in the neutral beam atomic layer etching process in the manufacturing method of the EUV photomask according to the first embodiment of the present invention.

[0032] Figure 9 This is a simplified structural diagram of the equipment used to remove the photoresist layer in the manufacturing method of the EUV photomask according to the first embodiment of the present invention.

[0033] Figure 10 This is a flowchart of a method for manufacturing an EUV photomask according to the second embodiment of the present invention. Detailed Implementation

[0034] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the invention. However, it will be apparent to those skilled in the art that the invention can be practiced without one or more of these details. In other instances, certain technical features well-known in the art have not been described to avoid confusion with the invention. It should be understood that the invention can be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, providing these embodiments will make the disclosure thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, for clarity, the dimensions of layers and regions, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0035] It should be understood that when an element or layer is referred to as "on" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, parts, and / or processes, these elements, components, areas, layers, parts, and / or processes should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, part, and / or process from another element, component, area, layer, part, and / or process. Therefore, without departing from the teachings of this invention, the first element, component, area, layer, part, and / or process discussed below may be referred to as a second element, component, area, layer, part, and / or process.

[0036] Spatial relation terms such as “below,” “under,” “below,” “below,” “above,” “on the top,” “on the bottom,” “front,” “back,” etc., are used herein for convenience of description to describe the relationship of one element or feature shown in the figure to other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below other elements,” “under them,” “on the bottom,” or “on its back” will be oriented “above,” “top,” or “right” of the other elements or features. Therefore, the exemplary terms “below,” “under,” and “on its back” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0037] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0038] As described in the background section, it is crucial to manufacture low-defect, high-performance EUV photomasks.

[0039] Taking EUV photomasks as an example, they are key components of EUV lithography (EUVL) systems. EUV lithography employs a scanner that uses light from the extreme ultraviolet (EUV) region (i.e., the exposure light), with wavelengths ranging from approximately 1 nm to approximately 100 nm, for example, 13.5 nm. Because optical materials are opaque to EUV radiation, EUV photomasks are reflective masks. The preform of an EUV photomask typically consists of a substrate (such as glass or quartz), a stack of reflective films (e.g., alternating stacks of molybdenum (Mo) and silicon (Si), also known as a reflective structure), and an absorption layer (which can be a single layer or multiple layers). The reflective film stack reflects the exposure light, while the absorption layer absorbs the exposure light and is etched into the specified patterns required for integrated circuit manufacturing (i.e., circuit patterns). The absorption layer has low EUV reflectivity, for example, less than 3-5%.

[0040] Please refer to the following: Figure 1A known method for manufacturing an EUV photomask includes the following steps:

[0041] 1. Manufacturing the EUV mask blank. Specifically, the following operations are performed in sequence:

[0042] 1.1 Provide a substrate 100 and perform wet cleaning on the substrate 100;

[0043] 1.2 Molybdenum (Mo) films and silicon (Si) films are alternately deposited on substrate 100 using conventional deposition methods such as sputtering, chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), and plasma enhanced ALD (PEALD) to form a reflective film stack layer 101.

[0044] 1.3, A capping layer 102 is deposited on the top surface of the reflective film stack layer 101 using conventional deposition methods such as sputtering, CVD, PECVD, ALD, and PEALD;

[0045] 1.4. An absorber layer 103 is deposited on the top surface of the capping layer 102 using conventional deposition methods such as sputtering, CVD, PECVD, ALD, and PEALD. The material can be, for example, chromium (Cr)-based or tantalum (Ta)-based. The absorber layer 103 can be a single-layer structure or a multilayer film stacked structure.

[0046] 1.5, a hard mask layer (not shown) is deposited on the top surface of the absorber layer 103 using conventional deposition methods such as CVD, PECVD, ALD, and PEALD;

[0047] 1.6. A back conductive layer 105 is deposited on the bottom surface of the substrate 100 using conventional deposition methods such as CVD, PECVD, ALD, and PEALD.

[0048] 2. Manufacturing of the first pattern 103a. Specifically, the following operations are performed in sequence:

[0049] 2.1 Coating and baking photoresist (PR, not shown), and exposing and developing the photoresist by laser, electron beam or ion beam, etc., to form a patterned photoresist layer;

[0050] 2.2 Using a patterned photoresist layer as a mask, a hard mask layer is plasma etched, with the etching stopping at the top surface of the absorption layer 103;

[0051] 2.3. The photoresist layer is dry-ashed with oxygen (O2) plasma, and then wet-stripped with various organic acids and inorganic sulfuric acid and H2O2 at high temperature. After that, it is rinsed with isopropanol (IPA) and CO2 to remove the photoresist layer.

[0052] 2.4 Dry plasma etching of the absorber layer 103, with etching stopping at the top surface of the capping layer 102, to form a desired first pattern 103a in the absorber layer 103, the first pattern 103a being a pattern of circuits and / or devices required for integrated circuit manufacturing.

[0053] 3. Manufacturing the second pattern 104. Specifically, the following operations are performed in sequence:

[0054] 3.1 Coating and baking photoresist (PR, not shown), and exposing and developing the photoresist by laser, electron beam or ion beam, etc., to form a patterned photoresist layer;

[0055] 3.2 Using a patterned photoresist layer as a mask, wet or dry plasma etching is performed on the absorption layer 103 and the reflective film stack layer 102 surrounding the first pattern 103a. The etching stops on the top surface of the substrate 100 to form a second pattern 104, which is a border pattern required for integrated circuit manufacturing.

[0056] 3.3. The photoresist layer is dry-ashed with oxygen (O2) plasma, and then wet-stripped with various organic acids and inorganic sulfuric acid and H2O2 at high temperature. After that, it is rinsed with isopropanol (IPA) and CO2 to remove the photoresist layer.

[0057] 4. Cleaning, inspection and transportation.

[0058] To reduce defects in EUV photomasks, Lawrence Livermore National Laboratory (US) employed ion beam deposition (IBD) to replace conventional deposition processes such as sputtering, CVD, PECVD, ALD, and PEALD in forming the various layers of the reflective film stack 101. Because IBD offers advantages such as cleaner and more controllable ions, the number of defects below 130 nm in the reflective film stack 101 can be reduced to less than 0.1 defects / cm². 2 This improves the yield rate of EUV photomasks.

[0059] However, the above methods still cannot be used to create higher-performance EUV photomasks.

[0060] The inventors discovered that EUV lithography is highly sensitive to defects in the EUV photomask blank and the EUV photomask itself. Specific sources of these defects include: a) defects introduced by the substrate 100; b) defects introduced by the deposition of each film layer, such as thermal stress-induced defects during the deposition of each layer of the reflective film stack 101; c) defects introduced by the manufacturing processes of the first and second patterns, such as defects caused by the use of charged ions or plasma during etching, resulting in charge effects and ultraviolet (UV) damage to the pattern edges of the reflective film stack and absorption layers, as well as thermal stress-induced defects caused by excessively high etching temperatures; d) defects introduced by the consistency of critical dimensions, topographic contours, symmetry, and smoothness of the pattern edges of the first and second patterns.

[0061] However, in existing EUV photomask manufacturing processes, firstly, whether using conventional deposition processes such as sputtering, CVD, PECVD, ALD, and PEALD, or IBD processes to deposit the reflective film stack 101 and absorber layer 103, the deposition temperature (200-500 degrees Celsius) introduces thermal stress during film deposition, leading to significant thermal stress-induced defects. Secondly, in the manufacturing of the first and second patterns, plasma etching is typically used to etch the reflective film stack and absorber layer. The photoresist layer is difficult to remove due to the high temperature of the plasma etching process (typically 100-300 degrees Celsius). Therefore, it is prone to thermal stress-induced defects and plasma-induced damage defects during etching. Thirdly, during the fabrication of the first and second patterns, further removal of the photoresist layer is required via oxygen plasma ashing and high-temperature acid-wet stripping (various acids, H2O2). Oxygen plasma ashing easily leads to plasma-induced damage defects, and high-temperature (100-200 degrees Celsius) acid-wet stripping also easily leads to thermal stress-induced defects.

[0062] Based on this, the method for manufacturing an EUV photomask of the present invention uses neutral beam atomic layer etching (NB-ALE) technology at least at room temperature to etch an EUV photomask blank to form a first pattern, thereby reducing plasma-induced damage defects and thermal stress-induced defects during the etching process. This improves the charge effect and ultraviolet damage caused to the pattern edges of the reflective film stack layer and the absorber layer in the EUV photomask blank, and improves the uniformity, contour, symmetry and smoothness of the key dimensions of the pattern and the pattern edges, thereby reducing the defects of the final EUV photomask.

[0063] Furthermore, a jet vapor deposition (JVD) method at room temperature is used to form a reflective film stack and an absorber layer on the EUV mask preform. Additionally, photoresist stripping is performed at room temperature using organic solvents to minimize charged ion or charged plasma-induced damage and thermal stress-induced defects.

[0064] The following combination Figures 2 to 9 The invention provides a detailed explanation of the method for manufacturing an EUV photomask, using specific embodiments and a method for manufacturing an EUV photomask as an example.

[0065] First Embodiment

[0066] Please refer to Figure 2 This embodiment provides a method for manufacturing an EUV photomask, which includes the following steps:

[0067] S11, an EUV mask preform is manufactured using a conventional deposition process, and a patterned hard mask layer is formed on the EUV mask preform;

[0068] S12, using the patterned hard mask layer as a mask, the EUV mask blank is etched at room temperature using a first neutral beam atomic layer etching process to form a first pattern in the EUV mask blank;

[0069] S13, a second photoresist layer is coated on the hard mask layer and the EUV mask blank, and the second photoresist layer is exposed and developed to pattern the second photoresist layer.

[0070] S14, using the patterned second photoresist layer as a mask, the hard mask layer and the EUV mask blank surrounding the first pattern are etched at room temperature using a third neutral beam atomic layer etching process to form the second pattern in the EUV mask blank;

[0071] S15, Remove the second photoresist layer at room temperature.

[0072] Please refer to Figure 3 In step S11, firstly, the manufactured mask blank is a blank for an EUV photomask. The EUV mask blank includes a substrate 200 and a reflective film stack layer 201, a capping layer 202, and an absorption layer 203 sequentially stacked on the first surface of the substrate 200. The specific manufacturing process includes the following steps:

[0073] First, a substrate 200 is provided, preferably a material with low thermal expansion and high thermal conductivity, such as low thermal expansion glass or quartz, specifically quartz glass, glass-ceramic (Zerodur), ultra-low coefficient of thermal expansion quartz glass (ULE, also known as zero expansion glass), etc. In some embodiments, the low thermal expansion glass can transmit visible wavelengths, a portion of the infrared wavelengths close to the visible spectrum (near-infrared), and a portion of the ultraviolet wavelengths. Further, the substrate 200 can absorb extreme ultraviolet wavelengths and deep ultraviolet wavelengths close to the extreme ultraviolet.

[0074] Then, a reflective film stack 201 is formed on the first surface of the substrate 200 (referred to as the front side of the substrate 200) using a conventional deposition process. Typically, the reflective film stack 201 is required to have high reflectivity for exposure light of a specific wavelength, for example, a reflectivity of over 60% for extreme ultraviolet light at 13.5 nm, preferably over 65%. In this embodiment, the reflective film stack 201 is mainly composed of alternating layers of a first reflective film (not shown) and a second reflective film (not shown). The number of layers of the first reflective film is, for example, 40 to 50, and the film thickness is, for example, 3 nm to 4 nm. The first and second reflective films can be any suitable material capable of having high reflectivity (e.g., over 70%) for extreme ultraviolet light of a specific wavelength (e.g., 13.5 nm). For example, the material of the first reflective film is silicon (Si), and the material of the second reflective film is molybdenum (Mo). Another example is that the material of the first reflective film is Mo, and the material of the second reflective film is beryllium (Be). Specifically, the first and second reflective films can be alternately formed using any suitable conventional deposition process such as sputtering (PVD), CVD, PECVD, ALD, PEALD, or IBD, thereby forming the desired reflective film stack 201. To minimize thermal stress-induced defects during the formation of the reflective film stack 201, the deposition temperature of each layer in the reflective film stack 201 is kept as close to room temperature as possible, for example, controlled between room temperature and 100°C.

[0075] Next, a capping layer 202 is formed on the top surface of the reflective film stack 201 using any suitable conventional deposition process such as sputtering (PVD), CVD, PECVD, ALD, PEALD, or IBD. The capping layer 202 is used to prevent the reflective film stack 201 from being damaged by the etching process. Its material may include at least one of ruthenium (Ru), ruthenium alloys (e.g., RuB, RuSi, or RuNb), or ruthenium oxide (e.g., RuO2 or RuNbO). It can be a single-layer film structure or a multi-layer film structure, and the thickness of the capping layer 202 is, for example, 2 nm to 4 nm. In other embodiments of the present invention, when the top layer of the reflective film stack 201 is silicon, the fabrication of the capping layer 202 may be omitted; or, when forming the reflective film stack 201, an additional silicon film (i.e., the first reflective film at the top layer) may be deposited as the capping layer 202.

[0076] Subsequently, an absorption layer 203 is formed on the top surface of the capping layer 202 using any suitable conventional deposition process such as sputtering (PVD), CVD, PECVD, ALD, PEALD, or IBD. The absorption layer 203 can be a single-layer film structure or a composite structure composed of multiple stacked films, and its material includes at least one of cobalt (Co), tellurium (Te), hafnium (Hf), nickel (Ni), tantalum (Ta), chromium (Cr), tantalum-based materials, and chromium-based materials. The total thickness of the absorption layer 203 is, for example, 50 nm to 75 nm. When the absorption layer 203 is a composite structure composed of multiple stacked films, the thickness of each single layer is, for example, 3 nm to 6 nm. To minimize thermal stress-induced defects during the formation of the reflective film stack layer 201, the deposition temperature of each film layer in the absorption layer 203 is kept as close to room temperature as possible, for example, controlled between room temperature and 100°C.

[0077] Subsequently, a hard mask layer 204 is formed on the top surface of the absorber layer 203 using any suitable conventional deposition process such as sputtering, CVD, PECVD, ALD, PEALD, or IBD. The hard mask layer 204 can be made of at least one of tantalum (Ta), tantalum-based materials (e.g., tantalum boride TaB, tantalum oxide TaO, tantalum nitride TaN, tantalum boron oxide TaBO, or tantalum boron nitride TaBN), silicon, silicon-based materials (e.g., silicon nitride SiN or silicon oxynitride SiON), ruthenium, or ruthenium-based materials (e.g., ruthenium boride RuB), and the thickness of the hard mask layer 204 is, for example, 4 nm to 20 nm.

[0078] Next, a back conductive layer 205 is deposited on the second surface of the substrate 200 (which is disposed opposite to the first surface of the substrate 200 and can be referred to as the back surface of the substrate 200) using any suitable conventional deposition process such as sputtering, evaporation, CVD, PECVD, ALD, PEALD, molecular beam epitaxy, or IBD. The material of the back conductive layer 205 may include at least one conductive material selected from chromium, chromium-based materials (e.g., chromium nitride CrN or chromium oxynitride CrON), tantalum, or tantalum-based materials (e.g., tantalum boride TaB, tantalum oxide TaO, tantalum nitride TaN, tantalum boron oxide TaBO, or tantalum boron nitride TaBN, etc.). The thickness of the back conductive layer 205 is, for example, 60 nm to 75 nm.

[0079] This completes the fabrication of the EUV mask blank in step S11.

[0080] It should be understood that in this embodiment, the back conductive layer 205 is formed after the deposition of the hard mask layer 204. However, the technical solution of the present invention is not limited to this. In other embodiments of the present invention, the deposition of the back conductive layer 205 can be performed before the deposition of the reflective film stack layer 201, or after the deposition of the reflective film stack layer 201 and before the deposition of the capping layer 202, or after the deposition of the capping layer 202 and before the deposition of the absorption layer 203, or after the deposition of the absorption layer 203 and before the deposition of the hard mask layer 204.

[0081] Please continue to refer to Figure 3 and Figure 4 In step S11, after depositing the hard mask layer 204, the following process is performed:

[0082] First, a first photoresist layer 206 is coated, and the first photoresist layer 206 is exposed and developed to pattern the first photoresist layer 206.

[0083] Then, using the patterned first photoresist layer 206 as a mask, the hard mask layer 204 is etched to the top surface of the EUV mask blank (i.e., the top surface of the absorption layer 203) using a second neutral beam atomic layer etching process at room temperature (typically 5°C to 35°C, preferably 20°C to 25°C) to transfer the patterned first photoresist layer 206 into the hard mask layer 204, forming a patterned hard mask layer 204'. This second neutral beam atomic layer etching process at room temperature can avoid plasma-induced damage defects generated on the EUV mask blank by the etching process, and keep the EUV mask blank at room temperature to avoid thermal stress-induced defects caused by the etching process, thereby reducing defects related to the first pattern in the manufacturing of EUV photomasks.

[0084] Subsequently, the first photoresist layer 206 is removed at room temperature (typically 5°C to 35°C, preferably 20°C to 25°C). Specifically, please refer to further details... Figure 9 At room temperature, in a wet stripping apparatus, the first photoresist layer 206 is first peeled off using an organic solvent, then rinsed with deionized water, and finally rotary dried. The removal of the first photoresist layer 206 is performed at room temperature and under acid-free conditions for the EUV mask preform. This process is plasma-free (no charge defects), room temperature process (no thermal stress-induced defects), and corrosion-free. Therefore, it can further reduce defects related to the first pattern (including thermal stress-induced defects and plasma-induced damage defects) in EUV photomask manufacturing.

[0085] Please refer to Figure 5 In step S12, using a patterned hard mask layer 204' as a mask, the absorption layer 203 is etched to the top surface of the capping layer 202 or the top surface of the reflective film stack layer 201 at room temperature (typically 5°C to 35°C, preferably 20°C to 25°C) using a first neutral beam atomic layer etching process, to form a first pattern 203a in the absorption layer 203. The first pattern 203a is a pattern of circuits and / or devices required for integrated circuit manufacturing. This room temperature first neutral beam atomic layer etching process can avoid plasma-induced damage defects generated on the EUV mask blank by the etching process, and keep the EUV mask blank at room temperature to avoid thermal stress-induced defects caused by the etching process. This reduces defects related to the first pattern 203a in EUV photomask manufacturing, making the uniformity of the CD and edge contour of the first pattern 203a superior to the first pattern produced by plasma etching process in the prior art.

[0086] Please refer to Figure 6 In step S13, a second photoresist layer 207 is coated on the patterned hard mask layer 204' and the EUV mask blank, and the second photoresist layer 207 is exposed and developed to pattern the second photoresist layer 207. The patterned second photoresist layer 207 can protect the formation area of ​​the first pattern 203a of the EUV mask blank and expose the area of ​​the EUV mask blank to be formed with the second pattern, which is located on the periphery of the first pattern 203a.

[0087] Please refer to Figure 6 and Figure 7In step S14, using the patterned second photoresist layer 207 as a mask, the hard mask layer 204', absorption layer 203, capping layer 202, and reflective film stack layer 201 are etched at room temperature using a third neutral beam atomic layer etching process. The etching stops on the first surface of the substrate 200, forming a second pattern 208, thereby obtaining an EUV photomask, wherein the second pattern 208 serves as the border of the EUV photomask. This room-temperature third neutral beam atomic layer etching process avoids plasma-induced damage defects on the EUV photomask caused by the etching process and keeps the EUV photomask blank at room temperature, avoiding thermal stress-induced defects caused by the etching process, thereby reducing defects related to the second pattern 208 in the manufacturing of the EUV photomask.

[0088] Please refer to Figure 6 and Figure 7 In step S15, the second photoresist layer 207 is removed at room temperature. Specifically, please refer to further details. Figure 9 At room temperature, in a wet stripping apparatus, the second photoresist layer 207 is first peeled off using an organic solvent, then rinsed with deionized water, and finally rotary dried. The removal of the second photoresist layer 206 is performed on the EUV mask preform at room temperature and under acid-free conditions. This process is plasma-free (no charge defects), room temperature process (no thermal stress-induced defects), and corrosion-free. Therefore, it can further reduce defects related to the first pattern (including thermal stress-induced defects and plasma-induced damage defects) in EUV photomask manufacturing.

[0089] It should be noted that the neutral beam atomic layer etching processes used in this embodiment, such as the first, second, and third neutral beam atomic layer etching processes, can all utilize neutral beam sources derived from pulsed modulated plasma (switching time, for example, 50 μs). For details, please refer to... Figure 8As shown, a carbon ion accelerating upper electrode 401 is located at the top of the quartz plasma chamber 400, and a carbon ion accelerating lower electrode 402 is located at the bottom of the quartz plasma chamber 400. A halogen gas with a high electron affinity (e.g., Cl2, Br2, or F2) is introduced from the carbon ion accelerating upper electrode 401 (shower head). In an inductively coupled plasma (ICP) 30 pulsed for 50 μs, electrons 301 lose energy during the "off" period and dissociate and attach to the halogen gas with a high electron affinity (e.g., Cl2, Br2, or F2). The halogen atoms with attached electrons are accelerated and pass through the aperture (1 mm in diameter and 10 mm in length) in the lower carbon ion accelerating lower electrode 402. During the passage through the aperture, they collide with the sidewall of the aperture of the lower carbon ion accelerating lower electrode 402 and are neutralized, thereby forming a neutral beam source 302. A neutral beam source 302 enters the atomic layer etching chamber 403 to etch the EUV mask preform or the hard mask layer on the EUV mask preform placed on the substrate 404. Neutral beam (NB) atomic layer etching can suppress the formation of defects and damage at the surface atomic layer level and allows ideal surface chemical reactions to occur at room temperature. Therefore, fabricating the first and second patterns of an EUV photomask using neutral beam atomic layer etching (NB-ALE) at room temperature is free from plasma charge effects and thermal stress, thus minimizing pattern-related defects in EUV photomask manufacturing. The resulting pattern exhibits superior uniformity, morphology, symmetry, and edge smoothness compared to traditional plasma etching.

[0090] As described above, the EUV photomask manufacturing method of this embodiment uses neutral beam atomic layer etching (NB-ALE) technology at least at room temperature to etch the EUV photomask blank to form a first pattern, replacing the process of using plasma etching to manufacture the first pattern in the prior art. This reduces plasma-induced damage defects and thermal stress-induced defects during the etching process, thereby improving the charge effect and ultraviolet damage caused to the pattern edges of the reflective film stack layer and the absorber layer of the EUV photomask blank, improving the uniformity, contour, symmetry and smoothness of the key dimensions of the pattern, and thus reducing the defects of the final EUV photomask.

[0091] Second Embodiment

[0092] Please refer to Figure 10 This embodiment provides a method for manufacturing an EUV photomask, which includes the following steps:

[0093] S21, an EUV mask preform is manufactured by a jet vapor deposition (JVD) process at room temperature, and a patterned hard mask layer is formed on the EUV mask preform;

[0094] S22, using the patterned hard mask layer as a mask, the EUV mask blank is etched at room temperature using a first neutral beam atomic layer etching process to form a first pattern in the EUV mask blank;

[0095] S23, a second photoresist layer is coated on the hard mask layer and the EUV mask blank, and the second photoresist layer is exposed and developed to pattern the second photoresist layer.

[0096] S24, using the patterned second photoresist layer as a mask, the hard mask layer and the EUV mask blank surrounding the first pattern are etched at room temperature using a third neutral beam atomic layer etching process to form the second pattern in the EUV mask blank;

[0097] S25, Remove the second photoresist layer at room temperature.

[0098] Please refer to Figure 3 Compared with step S11 in the first embodiment, the manufacturing method of EUV photomask in this embodiment is the same as step S12, step S23 is the same as step S13, step S24 is the same as step S14, and step S25 is the same as step S15. Therefore, steps S22 to S25 can be referred to the description of steps S12 to S15 in the first embodiment, and will not be repeated here.

[0099] The difference between the EUV photomask manufacturing method of this embodiment and step S11 of the first embodiment is that the deposition of each film layer deposited on the substrate 200 and the hard mask layer 204 in the EUV mask blank in step S21 is replaced by conventional deposition processes such as sputtering, CVD, PECVD, ALD, PEALD, and IBD with JVD process at room temperature.

[0100] Specifically, in this embodiment, the EUV mask preform manufactured in step S21 includes a substrate 200 and a reflective film stack layer 201, a capping layer 202, and an absorption layer 203 sequentially stacked on the first surface of the substrate 200, and also includes a back conductive layer 205 stacked on the second surface of the substrate 200. A hard mask layer 206 is also deposited on the top surface of the absorption layer 203. The specific manufacturing process includes the following steps:

[0101] First, a substrate 200 is provided, and a first reflective film and a second reflective film are alternately formed on the first surface of the substrate 200 (which may be referred to as the front side of the substrate 200) by a JVD process at room temperature (typically 5°C to 35°C, preferably 20°C to 25°C), thereby forming a reflective film stack layer 201.

[0102] Next, a cover layer 202 is formed on the top surface of the reflective film stack layer 201 by a JVD process at room temperature (usually 5°C to 35°C, preferably 20°C to 25°C).

[0103] Subsequently, an absorbent layer 203 is formed on the top surface of the cover layer 202 by a JVD process at room temperature (usually 5°C to 35°C, preferably 20°C to 25°C).

[0104] Then, a hard mask layer 204 is formed on the top surface of the absorber layer 203 by a JVD process at room temperature (typically 5°C to 35°C, preferably 20°C to 25°C).

[0105] Next, a back conductive layer 205 is deposited on the second surface of the substrate 200 (which is disposed opposite to the first surface of the substrate 200 and can be referred to as the back surface of the substrate 200) by a JVD process at room temperature (typically 5°C to 35°C, preferably 20°C to 25°C).

[0106] This completes the fabrication of the EUV mask blank in step S11.

[0107] It should be understood that in this embodiment, the back conductive layer 205 is formed after the deposition of the hard mask layer 204. However, the technical solution of the present invention is not limited to this. In other embodiments of the present invention, the deposition of the back conductive layer 205 can be performed before the deposition of the reflective film stack layer 201, or after the deposition of the reflective film stack layer 201 and before the deposition of the capping layer 202, or after the deposition of the capping layer 202 and before the deposition of the absorption layer 203, or after the deposition of the absorption layer 203 and before the deposition of the hard mask layer 204.

[0108] Please continue to refer to Figure 3 and Figure 4 In step S21, after depositing the hard mask layer 204, the following process is performed:

[0109] First, a first photoresist layer 206 is coated, and the first photoresist layer 206 is exposed and developed to pattern the first photoresist layer 206.

[0110] Then, using the patterned first photoresist layer 206 as a mask, the hard mask layer 204 is etched to the top surface of the EUV mask blank (i.e., the top surface of the absorption layer 203) using a second neutral beam atomic layer etching process at room temperature (typically 5°C to 35°C, preferably 20°C to 25°C) to transfer the patterned first photoresist layer 206 into the hard mask layer 204, forming a patterned hard mask layer 204'. This second neutral beam atomic layer etching process at room temperature can avoid plasma-induced damage defects generated on the EUV mask blank by the etching process, and keep the EUV mask blank at room temperature to avoid thermal stress-induced defects caused by the etching process, thereby reducing defects related to the first pattern in the manufacturing of EUV photomasks.

[0111] Subsequently, the first photoresist layer 206 is removed at room temperature (typically 5°C to 35°C, preferably 20°C to 25°C). Specifically, please refer to further details... Figure 9 At room temperature, in a wet stripping apparatus, the first photoresist layer 206 is first peeled off using an organic solvent, then rinsed with deionized water, and finally rotary dried. The removal of the first photoresist layer 206 is performed at room temperature and under acid-free conditions for the EUV mask preform. This process is plasma-free (no charge defects), room temperature process (no thermal stress-induced defects), and corrosion-free. Therefore, it can further reduce defects related to the first pattern (including thermal stress-induced defects and plasma-induced damage defects) in EUV photomask manufacturing.

[0112] It should be noted that jet vapor deposition (JVD) is a novel technology for preparing thin films of metals, semiconductors, dielectrics, and organic materials. In JVD, an inert carrier gas supersonic jet can be formed through a nozzle, which can deliver the corresponding reactive source gas onto a stationary or moving substrate 200 via thermal evaporation, sputtering, or microwave discharge. Furthermore, the unique feature of the JVD process in this embodiment is that, during deposition, a neutral beam of atoms is used to form the desired thin film at room temperature. Therefore, compared to conventional deposition processes (e.g., CVD, PECVD, ALD, sputtering, IBD, etc.) used in the first embodiment, there are no defects caused by plasma charge effects or thermal stress.

[0113] Compared to the first embodiment, this embodiment combines the effects of neutral beam jet vapor deposition (JVD) and neutral beam atomic layer deposition (NB-ALE) processes, as well as the removal of photoresist layers under room temperature and acid-free conditions, to achieve minimum internal stress (i.e., minimum thermal stress-induced defects) and minimum plasma-induced damage defects, ultimately minimizing the defect level of the EUV photomask.

[0114] It should be understood that in other embodiments of the present invention, when the performance of the required EUV photomask is relatively low, conventional photoresist removal processes can be used to remove the corresponding photoresist layer, or plasma etching processes can be used to etch the hard mask layer to form a patterned hard mask layer, or conventional plasma etching processes can be used in the fabrication of the second pattern, or some of the films in the reflective film stack layer, capping layer, absorption layer, back conductive layer, and hard mask layer can be replaced by room temperature jet vapor deposition (JVD) processes, etc.

[0115] Furthermore, the technical solution of the present invention is not limited to the manufacture of EUV photomasks, but can also be applied to the manufacture of DUV (deep ultraviolet) photomasks, etc., and can also reduce the defects of DUV (deep ultraviolet) photomasks.

[0116] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the scope of the present invention.

Claims

1. A method for manufacturing an EUV photomask, characterized in that, include: An EUV mask preform is fabricated, and a patterned hard mask layer is formed on the EUV mask preform at room temperature using a second neutral beam atomic layer etching process. Using the patterned hard mask layer as a mask, the EUV mask preform is etched at room temperature using a first neutral beam atomic layer etching process to form a first pattern in the EUV mask preform.

2. The method for manufacturing an EUV photomask as described in claim 1, characterized in that, The step of forming a patterned hard mask layer on the EUV mask preform includes: A hard mask layer is deposited on the EUV mask preform and a first photoresist layer is coated on it; The first photoresist layer is exposed and developed to pattern the first photoresist layer; Using the patterned first photoresist layer as a mask, the hard mask layer is etched to the top surface of the EUV mask blank at room temperature using a second neutral beam atomic layer etching process, and the first photoresist layer is removed at room temperature to form a patterned hard mask layer.

3. The method for manufacturing an EUV photomask as described in claim 2, characterized in that, The steps for removing the first photoresist layer at room temperature include: first, peeling off the first photoresist layer with an organic solvent at room temperature, and then rinsing with deionized water by spraying.

4. The method for manufacturing an EUV photomask as described in claim 2, characterized in that, The EUV mask preform includes a reflective film stack layer, a capping layer, and an absorption layer sequentially stacked on a first surface of a substrate. The reflective film stack layer includes alternating layers of a first reflective film and a second reflective film. The first pattern is formed in the absorption layer or in the absorption layer and the capping layer.

5. The method for manufacturing an EUV photomask as described in claim 4, characterized in that, At least one of the layers of the reflective film stack, the capping layer, the absorbing layer, and the hard mask layer is formed using a jet vapor deposition process at room temperature.

6. The method for manufacturing an EUV photomask as described in claim 5, characterized in that, After forming the first pattern, the method for manufacturing the EUV photomask further includes: A second photoresist layer is coated on the hard mask layer and the EUV mask blank, and the second photoresist layer is exposed and developed to pattern the second photoresist layer. Using the patterned second photoresist layer as a mask, the hard mask layer and the EUV mask blank surrounding the first pattern are etched at room temperature using a third neutral beam atomic layer etching process. The etching stops on the first surface of the substrate to form a second pattern in the EUV mask blank. Remove the second photoresist layer at room temperature.

7. The method for manufacturing an EUV photomask as described in claim 6, characterized in that, The steps for removing the second photoresist layer at room temperature include: first, using an organic solvent to peel off the second photoresist layer at room temperature, and then rinsing with deionized water by spraying.

8. The method for manufacturing an EUV photomask as described in claim 5, characterized in that, The first reflective film is made of molybdenum, the second reflective film is made of silicon, the number of layers of the first reflective film in the reflective film stack is 30 to 60, the material of the cover layer is at least one of ruthenium, ruthenium alloy and ruthenium oxide, the absorption layer is a composite structure of single-layer film or multi-layer film stack, the material of the absorption layer is tantalum-based material and / or chromium-based material, and the material of the hard mask layer is chromium-based material or silicon-based material.

9. The method for manufacturing an EUV photomask as described in claim 4, characterized in that, The EUV mask preform also includes a back conductive layer formed on the second surface of the substrate.

10. The method for manufacturing an EUV photomask as described in claim 9, characterized in that, The back conductive layer is formed using a jet vapor deposition process at room temperature.

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