Computing device and cache-based lru algorithm optimization method

Abstract

The application discloses a Cache-based LRU algorithm optimization method, which can improve the hit rate of mcu accessing Cache data, and a computing device comprises an mcu, a main memory, a cache memory, a flash memory, a counter array, a register array and a comparator array, the cache memory is connected between the mcu and the main memory, the flash memory is connected with the main memory, the cache memory adopts a multi-path group associative structure, the cache memory is evenly divided into a plurality of data blocks, the data blocks are connected with the counters one by one, the data blocks store data, and the counters are used for counting the unused times of the data blocks; the comparators in the comparator array are used for comparing the unused times of the data blocks; the registers in the register array are used for temporarily storing the comparison results of the comparators; and the mcu is used for sending an instruction for accessing data to the cache memory.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of cache, in particular to a computing device and a cache-based LRU algorithm optimization method. BACKGROUND

[0002] Cache (also known as level 1 cache) is a kind of RAM with high access speed, which is composed of static storage chips and mainly includes storage, address conversion components and replacement components. The storage is used to store instruction and data blocks downloaded from the main memory. The address conversion components are used to establish a directory table to realize the conversion from the main memory address to the cache address. The replacement components refer to data block replacement according to certain strategies.

[0003] The cache is connected between the main memory and the MCU, as shown in Figure 1 The access speed of the cache is close to that of the MCU, so that the use efficiency of the MCU can be improved. When the MCU downloads or stores data from the main memory, it will first check whether the data at the corresponding address is cached in the cache. If yes, the MCU directly downloads the data from the cache. If not, the data is sequentially downloaded from the main memory to the cache and the MCU. When the MCU downloads data from the cache, it usually follows the random method, the first-in-first-out method or the least recently used method (LRU algorithm) and other strategies. Among them, the LRU algorithm refers to replacing the least recently used content out of the cache to improve the use efficiency of the cache. However, in actual application, the commonly used LRU algorithm only replaces the data in the cache that can be compared with the number of times of use, and cannot select the least frequently used data block from several data blocks with equal number of times of use. If a random selection is made to replace any infrequently used data at this time, the least frequently used data may exist in the cache, which reduces the hit rate of the cache. SUMMARY

[0004] In view of the problem in the prior art that the strategy of replacing the content in the cache using the existing LRU algorithm cannot accurately replace the least frequently used data, resulting in reduced use efficiency of the cache, the present application provides a cache-based LRU algorithm optimization method. When the data in the cache is missing and the counters of two or more cache lines are full or the number of times of use recorded is the same, the accurate replacement of the infrequently used data can still be realized, the use efficiency of the cache can be improved, and the hit rate of the MCU accessing the data in the cache can be improved.

[0005] To achieve the above object, the present application adopts the following technical scheme:

[0006] A computing device comprises an MCU, a main memory, a cache memory, a flash memory, the cache memory is connected between the MCU and the main memory, the flash memory is connected with the main memory, characterized in that it further comprises a counter array, a register array, a comparator array, the cache memory adopts a multi-group associative structure, the cache memory is equally divided into a plurality of data blocks, the number of the data blocks is consistent with the number of the counters in the counter array, and the blocks are connected with the counters one by one, the data blocks store data, and the counters are used to count the number of times of non-use of the corresponding data blocks;

[0007] The comparator array is connected with the counter array, the comparator array comprises two levels: a first-level comparator array and a second-level comparator array, and the comparators in the comparator array are used to compare the number of times of non-use of the corresponding data blocks;

[0008] The registers in the register array are used to temporarily store the comparison results of the comparators;

[0009] The MCU is used to send an instruction for accessing data to the cache memory.

[0010] Further features are that,

[0011] The cache memory is an array structure of N*M, N*M represents that the cache memory is divided into N paths, and each path contains M rows, wherein N and M are positive integers; the M rows are distinguished from each other by group indexes, and the instruction sent by the MCU to the cache memory comprises a group index, a tag, and an offset, and the address of a certain byte data in the cache memory is determined by the group index, the tag, and the offset;

[0012] The size of the cache memory is 4K, and the cache memory adopts a structure of 4-group connection, the size of the block is 128 bytes, the address is 16 bits, the first 6 bits of the address are the tag, the middle 3 bits are the group index, and the last 7 bits are the offset;

[0013] Further, N is 4, and M is 8, each row contains a first even block, a first odd block, a second even block, and a second odd block;

[0014] The first-level comparator comprises a first first-level comparator and a second first-level comparator, the first first-level comparator is used to compare the data usage frequency in the first even block and the first odd block, the second first-level comparator is used to compare the data usage frequency in the second even block and the second odd block, and the second-level comparator is used to compare the comparison results of the first first-level comparator and the second first-level comparator;

[0015] The register array comprises at least two levels of registers: a first level of registers and a second level of registers, each level of the registers being connected in one-to-one correspondence with each level of the comparators, the first level of registers being connected with the first level of comparators and used for storing comparison results of the first level of comparators, and the second level of registers being connected with the second level of comparators and used for storing comparison results of the second level of comparators.

[0016] The first level of comparators comprises 16 comparators, including 8 first comparators and 8 second comparators, the first level of registers comprises 16 registers, including 8 first registers and 8 second registers, and the second level of comparators and the second level of registers are both 8, the first registers are connected in one-to-one correspondence with the first comparators, the second comparators are connected in one-to-one correspondence with the second registers, and the second comparators are connected in one-to-one correspondence with the second registers.

[0017] An LRU algorithm optimization method based on Cache, the method applying the computing device of claim 1 or 7, characterized in that the optimization method comprises S1, the MCU issuing an instruction for accessing data in the Cache;

[0018] S2, judging whether the data to be accessed by the MCU is cached in the Cache, if yes, indicating a hit, and if no, indicating that the data is missing;

[0019] When a hit occurs, the counter clears the counter of the hit data block, and meanwhile, the unused times of the remaining data blocks in the same group index are all incremented by 1; then, the MCU performs data interaction on the data at the selected address in the Cache.

[0020] When data missing occurs, step S3 is entered;

[0021] S3, comparing the unused times of the data blocks in the current group index by the first level of comparators, selecting the data block with the largest unused time, and temporarily storing the comparison result in the corresponding register array, and entering step S4;

[0022] S4, according to the comparison result of the first level of comparators, comparing the unused times of the two data blocks selected by the first level of comparators by the second level of comparators, selecting the data block with the largest unused time, and temporarily storing the comparison result in the corresponding register array, and entering step S5;

[0023] S5, clearing the counter of the selected data block that needs to be updated, and meanwhile, incrementing the unused times of the remaining data blocks in the row where the group index is located by 1; then, the MCU performs data interaction on the data at the selected address in the Cache.

[0024] Further features are that,

[0025] In step S1, the instruction issued by the mcu is to download data from a certain address of the Cache or store data into the Cache, and the instruction is the address of a certain byte in the Cache;

[0026] In step S2, the way to determine whether the data to be accessed by the mcu is cached in the Cache is as follows: S21, find the corresponding row in the Cache according to the group index in the instruction; S22, find the corresponding way in the row according to the tag in the instruction. If the tag of a data block in the row selected in step S21 is consistent with the tag in the instruction, it indicates a hit. If the two tags are inconsistent, it indicates that the data to be accessed by the mcu is not cached in the Cache, and the data is missing. S23, determine the address in the block corresponding to the row according to the offset in the instruction;

[0027] In S3, the way to compare the number of times of non-use of the data blocks in the current group index by the first comparator array is as follows: S31, compare the number of times of non-use of the data in the first even block and the first odd block in the row determined in step S21 by the first first-level comparator, and determine whether the number of times of non-use of the two data blocks is equal. If not, select the data block with the most number of times of non-use to obtain the first first-level comparison result, and store the first first-level comparison result in the corresponding first first-level register. If yes, select the data block not selected after the last first first-level comparison by querying the result of the last first first-level comparison stored in the corresponding register array to obtain the first first-level comparison result, and store the first first-level comparison result in the corresponding first first-level register. S32, compare the number of times of non-use of the data in the second even block and the second odd block in the row determined in step S21 by the second first-level comparator, and determine whether the number of times of non-use of the two data blocks is equal. If not, select the data block with the most number of times of non-use to obtain the second first-level comparison result, and store the second first-level comparison result in the corresponding second first-level register. If yes, select the data block not selected after the last second first-level comparison by querying the result of the last second first-level comparison stored in the corresponding register array to obtain the second first-level comparison result, and store the second first-level comparison result in the corresponding second first-level register;

[0028] In step S4, the first primary comparison result and the second primary comparison result are compared by the secondary comparator to determine whether the number of times of non-use of the two data blocks is equal. If not, the data block with the largest number of times of non-use is selected to obtain a secondary comparison result, and the secondary comparison result is stored in a corresponding secondary register. The final data block to be updated is obtained according to the secondary comparison result. If yes, the result of the last comparison of the secondary comparator is queried from the corresponding register array, and the data block not selected after the last comparison of the secondary comparator is selected to obtain the secondary comparison result, which is stored in the corresponding secondary register. The final data block to be replaced is obtained according to the secondary comparison result.

[0029] In step S5, the counter of the final data block to be replaced is cleared by the final comparison result of the secondary comparator, and the number of times of non-use of the remaining data blocks in the row is increased by 1. Then, the data block with a miss in the cache memory is replaced by the data block required by the MCU, and the MCU interacts with the cache memory for data.

[0030] The specific way of replacing the data block with a miss in the cache memory by the data block required by the MCU is that the corresponding new data is downloaded from the main memory and stored in the cache memory, and the new data replaces the data block with the largest number of times of non-use in the first even block, the first odd block, the second even block and the second odd block in the row of the group index in the cache memory.

[0031] The above structure of the application can achieve the following beneficial effects: the counting array, the register array and the comparator array are included in the computing device. The counting array is used to count the number of times of non-use of the data blocks in the cache. The comparator array is used to compare the counting values, that is, when a data miss occurs, the frequency of use of the data in the block is compared. The larger the counting value is, the more times the data in the block is not used. Therefore, the least frequently used data block in the row of the group index in the cache is selected to replace the frequently used data block in time, so that the problem of low hit rate of the MCU when accessing the data in the cache is avoided.

[0032] In addition, the register array is connected to the comparator array, and the register array is used to temporarily store the comparison result of the comparator array. When a data miss occurs and the counters of two or more data blocks are equal, the last comparison result stored in the corresponding register array is queried, and the data block not selected after the last comparison of the secondary comparator is selected, so that the data block that is less frequently used compared to other data blocks is replaced from the cache, thereby improving the hit rate of the MCU when accessing the data in the cache and improving the use efficiency of the cache. BRIEF DESCRIPTION OF DRAWINGS

[0033] Figure 1 is a structural block diagram of an existing computing device;

[0034] Figure 2 is a structural block diagram of a computing device of the present application;

[0035] Figure 3 is a structural block diagram of the distribution of blocks in the Cache of a computing device of the present application;

[0036] Figure 4 is a structural block diagram of the distribution of tags in the Cache of a computing device of the present application;

[0037] Figure 5 is a structural block diagram of a comparator in a computing device of the present application;

[0038] Figure 6 is a structural block diagram of the distribution of registers in a computing device of the present application;

[0039] Figure 7 is a bit partitioning diagram of the pre-download address or storage address (or the cached address in the Cache) sent by the MCU of the present application;

[0040] Figure 8 is a flowchart of the LRU algorithm optimization method of the present application. DETAILED DESCRIPTION

[0041] In order for those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the accompanying drawings of the embodiments of the present application. It should be noted that the terms “include” and “have” and any variations thereof in the specification and claims of the present application and the above-mentioned accompanying drawings are intended to cover non-exclusive inclusion, for example, a process, method, device, product or equipment that includes a series of steps or units does not have to be limited to only those steps or units clearly listed, but can include other steps or units that are not clearly listed or inherent to these processes, methods, products or equipment.

[0042] Figure 1 A currently commonly used computing device structure is provided, which includes an MCU, a Cache, a main memory and a flash memory connected in sequence. When the MCU attempts to download or store data from the main memory, the MCU (i.e., the processor) will first check whether the data corresponding to the address is cached in the Cache. If the data is cached in the Cache, the data is directly returned to the MCU. If the data to be accessed is not cached in the Cache, new data is downloaded from the main memory and returned to the Cache and the MCU, and the new data replaces the least frequently used content (i.e., the least frequently used content) in the Cache.

[0043] In practical applications, if the unused times of the cache lines are recorded by using the counter counting mode, if data missing occurs and the counters of two or more data blocks are full or the unused times of the two or more data blocks are the same, the LRU algorithm cannot select one of the two or more data blocks as the least frequently used data to be replaced, and the problem that the least frequently used data in the cache cannot be replaced occurs.

[0044] In view of the problem of low cache data hit rate and low use efficiency of the cache caused by the strategy of replacing the contents in the cache by using the LRU algorithm in the prior art, specific embodiments of a computing device are provided.

[0045] See Figure 2 A computing device includes an MCU, a main memory 1, a cache memory 2, a flash memory 3, a counter array 4, a register array 5, and a comparator array 6. The cache memory 2 is connected between the MCU and the main memory 1, and the flash memory 3 is connected to the main memory 1. The cache memory 2 is a 4-way set-associative cache structure, and the cache memory 2 is divided into a plurality of data blocks 20. The number of counters in the counter array 4 is consistent with the number of data blocks 20, and the data blocks 20 are connected to the counters one by one. The data blocks 20 store data. The size of the cache memory is 4 KB, the size of the data block is 128 bytes, and the data block is divided into 32 data blocks. When the MCU reads or stores an address from the cache memory, the lower 7 bits of the address are used to address a byte in the 128 bytes in the data block, and the combination of the lower 7 bits is an offset. Since the application adopts a 4-way set-associative cache structure, that is, the cache is evenly divided into 4 ways, and each way has 8 rows. In order to cover each row of data blocks (i.e., cache line), 3 bits are needed to find a row, which is called an index (i.e., index). Since the cache memory is divided into 4 ways, according to the index, 4 cache lines can be corresponded, and therefore the index can also be called a set index. In order to find the target data block, a tag array is introduced, and the tag array and the data array correspond one by one. Each data block corresponds to a unique tag, and the tag saves the remaining part of the entire address bit width excluding the index and the offset (see Figure 7 ). The combination of the tag, the set index, and the offset can uniquely determine an address.

[0046] The counter is used to count the unused times of the corresponding data block.

[0047] The comparator array 6 is connected to the counter array 4. The comparator array 6 is used to compare the number of times a data block is not used, that is, to compare the count value of the counter. In this embodiment, the counter mainly counts the frequency of data not being hit when the MCU accesses data in the cache.

[0048] The registers in the register array 5 are used to temporarily store the comparison results of the comparators in the comparator array 6;

[0049] MCU is used to send instructions to access data in the cache memory. The core of MCU is 8051. The address sent is a 16-bit address bus. The structure of the pre-download address or storage address in the instruction sent by MCU is shown in Figure 7 This 16-bit instruction indicates the byte in the cache that the MCU wants to select. The first 6 bits are the tag field, the middle 3 bits are the set index, and the last 7 bits are the offset. This offset is calculated based on the byte size of the data block (cache line). For example, if the data block size is 128 bytes, 2 to the power of 7 can represent exactly 128 results. These 128 results will correspond one-to-one with 128 bytes, allowing the unique byte of the data block to be found.

[0050] See Figure 3 Block 20 is an N*M array structure, where N*M indicates that the cache memory is divided into N ways (i.e., Way0 to Way3), each way contains M rows, where N and M are both positive integers. In this embodiment, N is 4 and M is 8, and each row contains a first even block, a first odd block, a second even block, and a second odd block. The M rows are distinguished from each other by group indexes. The instruction sent by the MCU to the cache memory includes: group index, tag, and offset. The storage location of the address sent by the MCU in the cache memory is determined by the group index (Set index0 to Set index7), tag, and offset. See the tag array corresponding to the data block. Figure 4 .

[0051] See Figure 5 The comparator array includes a primary comparator 61 and a secondary comparator (ie, Compare2_1) ​​62. The primary comparator 61 includes a first primary comparator (ie, Compare1_1) and a second primary comparator (ie, Compare1_2). The first primary comparator is used to compare the first even block (the first even block is in Figure 2 、 Figure 3 、 Figure 5 0, 0+4n, where n represents the current row where the block is located or the group index value where the block is located), the first odd block (the first odd block is in Figure 2 、Figure 3 The first primary comparator (i.e., Compare1_1) is configured to compare the data usage frequency of the data in the first even block (the first even block is represented by 0, 1+4n, where n represents the current row where the block is located or the group index value where the block is located, 0≤n≤7) and the data in the first odd block (the first odd block is represented by 1, 2+4n, where n represents the current row where the block is located or the group index value where the block is located, 0≤n≤7). Figure 2 Figure 3 Figure 5 The second primary comparator (i.e., Compare1_2) is configured to compare the data usage frequency of the data in the second even block (the second even block is represented by 2, 2+4n, where n represents the current row where the block is located or the group index value where the block is located, 0≤n≤7) and the data in the second odd block (the second odd block is represented by 3, 3+4n, where n represents the current row where the block is located or the group index value where the block is located, 0≤n≤7). Figure 2 Figure 3 Figure 5 The second primary comparator (i.e., Compare1_2) is configured to compare the data usage frequency of the data in the second even block (the second even block is represented by 2, 2+4n, where n represents the current row where the block is located or the group index value where the block is located, 0≤n≤7) and the data in the second odd block (the second odd block is represented by 3, 3+4n, where n represents the current row where the block is located or the group index value where the block is located, 0≤n≤7).

[0052] See Figure 6 The register array includes the first primary register 51 and the second primary register 52. The first primary register 51 is connected with the first primary comparator 61 and is configured to store the comparison result of the first primary comparator 61. The second primary register 52 is connected with the second primary comparator 62 and is configured to store the comparison result of the second primary comparator 62. The first primary register 51 includes the first first primary register and the first second primary register.

[0053] In the embodiment, the first primary comparator includes 8 first primary comparators and 8 second primary comparators. The first primary register includes 8 first first primary registers and 8 first second primary registers. The second primary comparator includes 8 second primary comparators and 8 second primary registers. The first first primary register is connected with the first primary comparator in one-to-one correspondence. The second primary register is connected with the second primary comparator in one-to-one correspondence. The second primary register is connected with the second primary comparator in one-to-one correspondence. In the embodiment, two-level comparators are adopted. The reason is that the cache adopts a structure connected with 4 groups. The counters of 4 cache lines in a row (group index) need to be compared. Therefore, two-level comparators are needed to compare two by two, and finally the cache line with the most unused times is selected. According to actual application requirements, the comparator array can be flexibly set. For example, if the cache adopts a structure connected with 8 groups, three-level comparators can be adopted to replace the least frequently used data in the 8 cache lines of the same group index.

[0054] The settings of the counter array, the comparator array, and the register array in the computing device of the application are beneficial to accumulate and compare the unused times of the data blocks, and store the comparison results. When the comparison results show that the unused times of two or more data blocks are equal, the least frequently used data block can be selected for replacement. ​​​​

[0055] A Cache-based LRU algorithm optimization method, which applies the above computing device, see Figure 8 The optimization method comprises the following steps: S1, the mcu issues an instruction for accessing data in the Cache: downloading data from the Cache or storing data in the Cache.

[0056] S2, judging whether the data to be accessed by the mcu is cached in the Cache, if yes, it indicates a hit, if not, it indicates that the data is missing; the way to judge whether the data to be accessed by the mcu is cached in the Cache is: S21, finding the corresponding row in the Cache according to the group index in the instruction; S22, finding the corresponding way in the row according to the tag in the instruction; if there is a data block whose tag is consistent with the tag in the instruction in the row selected in S21, it indicates a hit, if the two are inconsistent, it indicates that the data to be accessed by the mcu is not cached in the Cache, the data is missing; S23, determining the block address in the row corresponding to the way according to the offset in the address;

[0057] When a hit occurs, the counter clears the counter of the hit data block, and at the same time, the unused times of the remaining data blocks in the same group index are increased by 1; then, the MCU performs data interaction on the data at the selected address in the Cache;

[0058] When data missing occurs, step S3 is entered;

[0059] In S3, the unused times of the data blocks in the current group index are compared by the first-level comparators, the data block with the most unused times is selected, and the comparison result is temporarily stored in the corresponding register array, and step S4 is entered. The comparison of the unused times of the data blocks in the current group index by the first-level comparator array is as follows: S31, the unused times of the data in the first even block and the first odd block in the row determined in step S21 are compared by the first first-level comparator, and it is determined whether the unused times of the two data blocks are equal. If not, the data block with the most unused times is selected, the first first-level comparison result is obtained, and the first first-level comparison result is stored in the corresponding first first-level register; if yes, the data block not selected after the last first first-level comparator comparison is selected by querying the result of the last first first-level comparison stored in the corresponding register array, the first first-level comparison result is obtained, and the first first-level comparison result is stored in the corresponding first first-level register; S32, the unused times of the data blocks in the second even block and the second odd block in the row determined in step S21 are compared by the second first-level comparator at the same time, and it is determined whether the unused times of the two data blocks are equal. If not, the data block with the most unused times is selected, the second first-level comparison result is obtained, and the second first-level comparison result is stored in the corresponding second first-level register. If yes, the data block not selected after the last first first-level comparator comparison is selected by querying the result of the last first first-level comparison stored in the corresponding register array, the first first-level comparison result is obtained, and the first first-level comparison result is stored in the corresponding first first-level register.

[0060] In S4, according to the comparison result of the first-level comparator, the unused times of the two data blocks selected by the first-level comparator are compared by the second-level comparator, the data block with the most unused times is selected, and the comparison result is temporarily stored in the corresponding register array, and step S5 is entered.

[0061] In this step S4, the first first-level comparison result and the second first-level comparison result are compared by the second-level comparator, and it is determined whether the unused times of the two data blocks are equal. If not, the data block with the most unused times is selected, the second-level comparison result is obtained, the second-level comparison result is stored in the corresponding second-level register, and the data block finally needed to be updated is obtained according to the second-level comparison result; if yes, the data block not selected after the last second-level comparator comparison is selected by querying the result of the last second-level comparator comparison stored in the corresponding register array, the second-level comparison result is obtained, the second-level comparison result is stored in the corresponding second-level register, and the data block finally needed to be replaced is obtained according to the second-level comparison result.

[0062] S5, the selected data block counter which needs to be updated is cleared, at the same time, the unused times of the rest data blocks in the row of the group index are increased by 1; then, the MCU carries out data interaction on the data of the selected address in the Cache.

[0063] The above LRU algorithm optimization method of the present application is used as a replacement strategy, which can select and replace the least frequently used cache line in the same group index of the Cache: firstly, steps S21-S23 in steps S1 and S2 are used to determine cache hit or miss. Then, steps S31-S32 in step S3 and step S4 are used to select the least frequently used cache line in the group index through the two-stage comparator, the register array and the counter array. Finally, step S5 is used to replace the least frequently used data. Thus, the phenomenon that the infrequently used data in the Cache is not updated all the time is avoided, and the hit rate and the use efficiency of the Cache are improved.

[0064] The above is only the preferred embodiment of the present application, and the present application is not limited to the above embodiments. It can be understood that other improvements and changes directly derived or conceived by those skilled in the art without departing from the spirit and concept of the present application should be considered to be included in the protection scope of the present application.

Claims

1. A cache-based LRU algorithm optimization method, the method being applied to a computing device, the computing device comprising an MCU, a main memory, a cache memory, and a flash memory, the cache memory being connected between the MCU and the main memory, the flash memory being connected to the main memory, the computing device further comprising a counter array, a register array, and a comparator array, the cache memory being divided into a plurality of data blocks, the number of the data blocks being the same as the number of counters in the counter array, the data blocks being connected to the counters in a one-to-one correspondence, the data blocks storing data, and the counters being used to count the number of times the corresponding data blocks have not been used; The comparator array is connected to the counter array, and the comparator array includes two stages: a primary comparator array and a secondary comparator array, wherein the comparators in the comparator array are used to compare the number of unused times of the data blocks; The registers in the register array are used to temporarily store the comparison results of the comparator; The MCU is used to send an instruction to access data to the cache memory; The optimization method is characterized in that: S1, MCU issues instructions to access data in Cache; S2. Determine whether the cache contains the data that the MCU wants to access. If so, it indicates a hit; if not, it indicates that the data is missing. When a hit occurs, the counter clears the counter of the hit data block and increases the unused count of the remaining data blocks in the same group index by 1. Then, the MCU performs data interaction on the data of the selected address in the cache. When data is missing, go to step S3; S3, using a first-level comparator to compare the number of unused times of the data blocks in the current group index, select the data block with the largest number of unused times, and temporarily store the comparison result in the corresponding register array, and then proceed to step S4; S4. Based on the comparison result of the first comparator, the second comparator compares the unused times of the two data blocks selected by the first comparator, selects the data block with the largest unused times, and temporarily stores the comparison result in the corresponding register array, and then proceeds to step S5. S5. Clear the counter of the selected data block to be updated, and at the same time, increment the unused counts of the remaining data blocks in the row where the group index is located by 1; then, the MCU performs data interaction on the data at the selected address in the cache; In S3, the method of comparing the number of unused times of the data blocks in the current group index through the first-level comparator array is as follows: S31, using the first-level comparator, compare the number of unused times of the data in the first even block and the first odd block in the row where the current group index is located, and determine whether the number of unused times of the two data blocks is equal. If not, select the data block with the largest number of unused times to obtain the first-level comparison result, and store the first-level comparison result in the corresponding first-level register; if so, query the result of the last first-level comparison stored in the corresponding register array, select the data block that was not selected after the last first-level comparator comparison, and obtain the first-level comparison result this time, and store the first-level comparison result in the corresponding register array. The comparison result is stored in the corresponding first-level register; S32, at the same time, the unused times of the data in the second even block and the second odd block in the row where the current group index is located are compared by the second-level comparator to determine whether the unused times of the two data blocks are equal; if not, the data block with the largest number of unused times is selected to obtain the second-level comparison result, and the second-level comparison result is stored in the corresponding second-level register; if so, by querying the result of the last second-level comparison stored in the corresponding register array, the data block that was not selected after the last comparison by the second-level comparator is selected to obtain the second-level comparison result this time, and the second-level comparison result is stored in the corresponding second-level register.

2. The cache-based LRU algorithm optimization method according to claim 1, characterized in that: The cache memory is The array structure of It indicates that the cache memory is divided into N ways, each way contains M rows, where N and M are both positive integers; the M rows are distinguished from each other by group indexes, and the instruction sent by the MCU to the cache memory includes: a group index, a tag, and an offset, and the address of a byte of data in the cache memory is determined by the group index, tag, and offset.

3. The cache-based LRU algorithm optimization method according to claim 2, characterized in that: The cache memory has a size of 4K and adopts a 4-way group-connected structure. The data block has a size of 128 bytes. The instruction is 16 bits, the first 6 bits of the instruction are the tag, the middle 3 bits are the group index, and the last 7 bits are the offset.

4. The cache-based LRU algorithm optimization method according to claim 3, characterized in that: N is 4, M is 8, and each row includes a first even block, a first odd block, a second even block, and a second odd block.

5. The cache-based LRU algorithm optimization method according to claim 4, characterized in that: The comparator array includes a first-level comparator, and the first-level comparator includes a first first-level comparator and a second first-level comparator. The first first-level comparator is used to compare the number of times data in the first even block and the first odd block is not used, and the second first-level comparator is used to compare the number of times data in the second even block and the second odd block is not used. The second-level comparator is used to compare the comparison results of the first first-level comparator and the comparison results of the second first-level comparator.

6. The cache-based LRU algorithm optimization method according to claim 5, characterized in that: The register array includes a first-level register and a second-level register. The first-level register is connected to the first-level comparator and is used to store the comparison results of the first-level comparator array. The second-level register is connected to the second-level comparator array and is used to store the comparison results of the second-level comparator array.

7. The cache-based LRU algorithm optimization method according to claim 6, characterized in that: There are 16 first-level comparators, including 8 first-level comparators and 8 second-level comparators. There are 16 first-level registers, including 8 first-level registers and 8 second-level registers. There are 8 second-level comparators and 8 second-level registers. The first-level register is connected to the first-level comparator in a one-to-one correspondence, the second-level comparator is connected to the second-level register in a one-to-one correspondence, and the second-level comparator is connected to the second-level register in a one-to-one correspondence.

8. The cache-based LRU algorithm optimization method according to claim 7, characterized in that: In step S4, the first-level comparison result and the second-level comparison result are compared by a secondary comparator to determine whether the number of unused times of the two data blocks is equal; if not, the data block with the largest number of unused times is selected to obtain the secondary comparison result, and the secondary comparison result is stored in the corresponding secondary register, and the data block that needs to be updated is finally obtained according to the secondary comparison result; if so, the data block that was not selected after the last second comparator comparison is selected by querying the result of the last second-level comparator comparison stored in the corresponding register array to obtain the second-level comparison result this time, and the second-level comparison result is stored in the corresponding second-level register, and the data block that needs to be updated is finally obtained according to the secondary comparison result.

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