Signal control method, system, medium and device based on chip verification system

Abstract

This invention provides a signal control method, system, medium, and device based on a chip verification system. The method, implemented using C language, includes the following steps: connecting the device under test (DUT) and multiple verification components in the chip verification system to an interconnect bus, and allocating corresponding address spaces for the verification components; responding to test cases accessing the interconnect bus according to the allocated addresses, the interconnect bus identifies the corresponding verification component based on the address space and sends a command to the port connected to the interconnect bus for the corresponding verification component; the corresponding verification component retrieves the command from the port, parses the command to identify the corresponding opcode, generates a corresponding signal based on the opcode, and executes the relevant operation so that the signal can be used by the DUT. This invention significantly shortens the chip verification cycle and improves chip verification efficiency and quality.

Description

Technical Field

[0001] This invention relates to the field of chip technology, and in particular to a signal control method, system, medium, and device based on a chip verification system. Background Technology

[0002] In recent years, with the continuous increase in chip scale, the complexity of chip verification has also increased exponentially. To ensure chip quality and accelerate simulation verification time, chip verification is often performed at the module level, system level, and chip level. Currently, the mainstream verification method in the industry is to use UVM (Universal Verification Methodology) to build a simulation verification environment and develop UVM-based test cases. However, controlling clock, reset, and sideband signals in the test cases is very inconvenient.

[0003] The commonly used method is to control these signals through interfaces in SV (System Verilog, a system hardware description language). However, this approach is slow to iterate and inconvenient to debug. Therefore, this traditional verification method is no longer sufficient to meet the verification requirements of all test levels.

[0004] Compared to UVM, C is also frequently used in chip verification processes. It features fast compilation and easy debugging, and is often used in SoC (System on Chip) level verification. Therefore, applying C to module-level verification, developing C-based test cases, implementing bus control functions through DPI (Direct Programming Interface), and replacing UVM with C for basic bus access is gradually becoming a popular approach.

[0005] However, there is still a lack of effective methods for controlling clock signals, reset signals, and sideband signals in C. Most methods still use a hybrid approach, that is, accessing the bus in C and using UVM to control clock, reset, and other signals. This approach, relying on traditional UVM, suffers from drawbacks such as slow compilation iterations and inconvenient debugging. Summary of the Invention

[0006] In view of this, the purpose of this invention is to propose a signal control method, system, medium and device based on a chip verification system, so as to solve the problem that the existing technology uses a hybrid approach of C language and UVM to control clock, reset, sideband and other signals, which leads to slow compilation iteration and inconvenient debugging.

[0007] To achieve the above objectives, this invention provides a signal control method based on a chip verification system, which implements the following steps using the C language:

[0008] The device under test (DUT) and multiple verification components in the chip verification system are connected to the interconnect bus, and corresponding address spaces are allocated to the multiple verification components.

[0009] In response to the test case accessing the interconnect bus according to the assigned address, the interconnect bus identifies the corresponding verification component based on the address space and sends the command to the port where the corresponding verification component is connected to the interconnect bus.

[0010] The corresponding verification component obtains the command from the port, parses the command to identify the corresponding opcode, generates the corresponding signal based on the opcode, and performs the relevant operation so that the signal can be used by the device under test.

[0011] In some embodiments, the plurality of verification components include at least a clock generator, a GPIO control generator, a sideband signal controller, and a memory.

[0012] In some embodiments, generating a corresponding signal based on an opcode and performing related operations to enable the signal to be used by the device under test includes:

[0013] In response to the corresponding verification component being a clock generator, the clock generator generates multiple clock signals based on the opcode, performs frequency conversion control and enable control on the multiple clock signals, and connects the multiple clock signals to the corresponding port signals of the device under test (DUT) for use by the DUT.

[0014] In some embodiments, generating a corresponding signal based on an opcode and performing related operations to enable the signal to be used by the device under test includes:

[0015] In response to the corresponding verification component being a GPIO control generator, the GPIO control generator generates a reset signal and a level signal based on the opcode, and connects the reset signal and / or the level signal to the corresponding port signal of the device under test (DUT) for use by the DUT.

[0016] In some embodiments, generating a corresponding signal based on an opcode and performing related operations to enable the signal to be used by the device under test includes:

[0017] In response to the corresponding verification component being a sideband signal controller, the sideband signal controller generates a multi-bit data signal based on the opcode and sends the multi-bit data signal to the transceiver. The transceiver then recovers each bit of the received data signal and outputs it to the port so that the port obtains a multi-bit wide signal. The multi-bit wide signal is then connected to the corresponding port signal of the device under test (DUT) for use by the DUT.

[0018] In some embodiments, the method further includes:

[0019] In response to the corresponding verification component being a memory, the device under test (DUT) performs read and write operations on the connected memory.

[0020] In some embodiments, the method further includes:

[0021] The interconnect bus is selected based on the interface type of the device under test (DUT). The interconnect bus includes at least the AHB bus and the AXI bus.

[0022] Another aspect of the present invention provides a signal control system based on a chip verification system, which is generated using the C language and includes:

[0023] The address space allocation module is configured to connect the device under test and multiple verification components in the chip verification system to the interconnect bus, and allocate corresponding address spaces to the multiple verification components.

[0024] The command delivery module is configured to respond to test cases by accessing the interconnect bus according to the assigned address. The interconnect bus identifies the corresponding verification component based on the address's address space and then delivers the command to the port where the corresponding verification component is connected to the interconnect bus.

[0025] The signal control module is configured to receive commands from the port by the corresponding verification component, parse the commands to identify the corresponding opcode, generate the corresponding signal based on the opcode, and perform related operations so that the signal can be used by the device under test.

[0026] In another aspect, the present invention provides a computer-readable storage medium storing computer program instructions that, when executed by a processor, implement the above-described method.

[0027] In another aspect, the present invention provides a computer device including a memory and a processor, wherein the memory stores a computer program that, when executed by the processor, performs the above-described method.

[0028] The present invention has at least the following beneficial technical effects:

[0029] 1. The signal control method based on a chip verification system of the present invention connects the device under test (DUT) and multiple verification components in the chip verification system to an interconnect bus using C language, and allocates corresponding address spaces to each verification component. Access to each address in the C language is routed to the corresponding verification component through the real interconnect bus. Each verification component parses and identifies the received commands, thereby effectively controlling signals with non-standard bus behavior. All operations of the present invention can be implemented in C language, thus avoiding the disadvantages of slow compilation iteration and inconvenient debugging caused by traditional UVM in the chip verification process, which can greatly shorten the verification cycle and improve verification efficiency and quality.

[0030] 2. In addition, the method of mounting the verification component onto the interconnect bus has extremely high scalability, making it easy to connect new custom verification components. The required functions can be achieved simply by developing the new verification component, which has high reusability. Attached Figure Description

[0031] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other embodiments can be obtained based on these drawings without creative effort.

[0032] Figure 1 This is a schematic diagram of a signal control method based on a chip verification system according to an embodiment of the present invention;

[0033] Figure 2 This is a schematic diagram of the structure of a signal control method for a chip verification system according to an embodiment of the present invention;

[0034] Figure 3 This is a schematic diagram of the structure of a clock generator provided according to an embodiment of the present invention;

[0035] Figure 4 This is a schematic diagram of the structure of a GPIO control generator provided according to an embodiment of the present invention;

[0036] Figure 5 This is a schematic diagram of the structure of a sideband signal controller provided according to an embodiment of the present invention;

[0037] Figure 6 This is a schematic diagram of a signal control system based on a chip verification system according to an embodiment of the present invention;

[0038] Figure 7 This is a schematic diagram of a computer-readable storage medium for implementing a signal control method based on a chip verification system according to an embodiment of the present invention;

[0039] Figure 8 This is a schematic diagram of the hardware structure of a computer device for executing a signal control method based on a chip verification system according to an embodiment of the present invention. Detailed Implementation

[0040] To make the objectives, technical solutions, and advantages of the present invention clearer, the embodiments of the present invention will be further described in detail below with reference to specific examples and the accompanying drawings.

[0041] It should be noted that all uses of "first" and "second" in the embodiments of the present invention are for the purpose of distinguishing two different entities or different parameters with the same name. Therefore, "first" and "second" are merely for convenience of expression and should not be construed as limiting the embodiments of the present invention. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion, such as other steps or units inherent in a process, method, system, product, or device that includes a series of steps or units.

[0042] To achieve the above objectives, the first aspect of the present invention provides an embodiment of a signal control method based on a chip verification system. Figure 1 The diagram shown is a schematic representation of an embodiment of the signal control method based on a chip verification system provided by the present invention. Figure 1 As shown, the embodiments of the present invention implement the following steps using the C language:

[0043] Step S10: Connect the device under test and multiple verification components in the chip verification system to the interconnect bus respectively, and allocate corresponding address space to the multiple verification components.

[0044] Step S20: In response to the test case accessing the interconnect bus according to the assigned address, the interconnect bus confirms the corresponding verification component based on the address space and sends the command to the port where the corresponding verification component is connected to the interconnect bus.

[0045] Step S30: The corresponding verification component obtains the command from the port, parses the command to identify the corresponding operation code, generates the corresponding signal based on the operation code, and performs the relevant operation so that the signal can be used by the device under test.

[0046] The signal control method based on a chip verification system in this invention uses C language to connect the device under test (DUT) and multiple verification components in the chip verification system to an interconnect bus, and allocates corresponding address spaces to each verification component. The access to each address in the C language is routed to the corresponding verification component through the real interconnect bus. Each verification component parses and identifies the received commands, thereby effectively controlling signals with non-standard bus behavior. All operations in this invention can be implemented in C language, thus avoiding the disadvantages of slow compilation iteration and inconvenient debugging associated with traditional UVM during chip verification. This significantly shortens the verification cycle and improves verification efficiency and quality. Furthermore, the method of mounting verification components to the interconnect bus has high scalability, allowing for easy connection of new customized verification components. The required functions can be achieved simply by developing new verification components, demonstrating high reusability.

[0047] In some embodiments, the plurality of verification components include at least a clock generator, a GPIO control generator, a sideband signal controller, and a memory.

[0048] In this embodiment, the verification components are not limited to clock generators, GPIO control generators, sideband signal controllers, and memory, and can be easily expanded.

[0049] In some embodiments, generating a corresponding signal based on an opcode and performing related operations to enable the signal to be used by the device under test includes: in response to the corresponding verification component being a clock generator, the clock generator generating multiple clock signals based on the opcode, performing frequency conversion control and enable control on the multiple clock signals, and connecting the multiple clock signals to the corresponding port signals of the device under test for use by the device under test.

[0050] In some embodiments, generating a corresponding signal based on an opcode and performing related operations to enable the signal to be used by the device under test (DUT) includes: in response to the corresponding verification component being a GPIO control generator, the GPIO control generator generates a reset signal and a level signal based on the opcode, and connects the reset signal and / or the level signal to the corresponding port signal of the DUT for use by the DUT.

[0051] In some embodiments, generating a corresponding signal based on an opcode and performing related operations to enable the signal to be used by the device under test (DUT) includes: in response to the corresponding verification component being a sideband signal controller, the sideband signal controller generates a multi-bit data signal based on the opcode and sends the multi-bit data signal to a transceiver; the transceiver recovers each bit of the received data signal and outputs it to a port so that the port obtains a multi-bit wide signal; and the multi-bit wide signal is connected to the corresponding port signal of the DUT for use by the DUT.

[0052] In the above embodiments, by unifying the control of the interconnect bus, multiple clock signals, reset signals, level signals, sideband unit-width signals, and multi-bit-width signals, and importing the control method into the C language, different test cases can be written in C language according to the test scenario. Within these test cases, the clock changes, reset occurrences, and sideband signal levels can be flexibly controlled at any given time, thereby simulating real-world usage scenarios and improving the quality of chip verification. Implementing control of all port signals in C language allows for convenient integration of the device under test (DUT) into this verification framework, thus enabling DUT verification.

[0053] In some embodiments, the method further includes: in response to the corresponding verification component being a memory, the device under test performing read and write operations on the connected memory.

[0054] In some embodiments, the method further includes: selecting an interconnect bus based on the interface type of the device under test, wherein the interconnect bus includes at least an AHB bus and an AXI bus.

[0055] In this embodiment, the interconnect bus is not limited to a certain type of bus and can be flexibly selected according to the interface type of the device under test. For example, if the external configuration interface of the device under test is AHB (Advanced High Performance Bus), then the interconnect bus can be selected as the AHB bus. If the configuration interface is AXI (Advanced eXtensible Interface), then the AXI bus can be selected as the interconnect bus.

[0056] The following are specific embodiments of the signal control method based on the chip verification system of the present invention:

[0057] Figure 2 A schematic diagram of the structure of the signal control method for implementing a chip verification system provided in this embodiment is shown. Figure 2 As shown, this embodiment employs a unified bus approach, connecting the device under test (DUT) and all verification components via an interconnect bus. The verification components include a clock generator, a GPIO (General Purpose Input / Output Port) control generator, a sideband signal controller, and memory. By pre-assigning different addresses to each verification component and utilizing the address decoding function of the interconnect bus, commands can be sent to the corresponding verification components. Each verification component parses the received commands, identifies the corresponding opcode, and thus implements the specific function. Furthermore, each component can customize the command format and parameter content, maximizing its scalability.

[0058] The specific steps are as follows:

[0059] 1) Develop corresponding bus driver tasks based on the selected bus type, such as basic read / write access, and import these read / write accesses into the C language via DPI (Direct Programming Interface) for easy calling. A specific example is as follows:

[0060]

[0061] 2) Select the required verification components and allocate address space for each verification component and the DUT. In this embodiment, the address space allocated to the DUT is 0x0000_0000~0x0FFF_FFFF, the address space allocated to the clock generator is 0x1000_0000~0x1000_00FF, the address space allocated to the GPIO control generator is 0x1000_0100~0x1000_01FF, the address space allocated to the sideband signal controller is 0x1000_2000~0x1000_6000, and the address space allocated to the memory is 0x2000_0000~0x4000_0000. Therefore, the C language implementation of the test program can send commands to the respective verification components according to the different addresses accessed.

[0062] 3) Implement the functions of each component:

[0063] When the clock generator receives an access request for itself via the interconnect bus, it can parse the content based on the accessed address and data. Figure 3 A schematic diagram of the clock generator provided in this embodiment is shown. Figure 3 As shown, when the test case accesses the bus according to the pre-allocated address 0x1000_0000, the interconnect bus will send a command to the Slave1 port. The clock generator will then call the corresponding parsing task command_parse according to the received command. Based on the defined command format, it will control the frequency and enable of multiple clock signals. At the same time, it will pass these parameters to the clock generator clock_generator to generate a clock of the corresponding frequency. Finally, the output clock will be connected to the corresponding port signal of the DUT.

[0064] The specific implementation process is as follows, where both the command_parse task and the clock_generator task are implemented on the SV (System Verilog) side.

[0065]

[0066]

[0067] When the GPIO control generator receives an access request for itself via the interconnect bus, it can parse the content based on the accessed address and data. Figure 4 A schematic diagram of the GPIO control generator provided in this embodiment is shown. Figure 4 As shown, when the test case accesses the bus according to the pre-allocated address 0x1000_0100, the interconnect bus sends a command to the Slave2 port. The GPIO control generator then calls the corresponding parsing task `command_parse` based on the received command, controls the multiple signals according to the defined command format, and finally connects the output reset signal or level signal to the corresponding port signal of the DUT. The specific implementation process is as follows:

[0068]

[0069]

[0070] When the sideband signal controller receives an access request for itself via the interconnect bus, it can parse the content based on the access address and data. Figure 5 A schematic diagram of the sideband signal controller provided in this embodiment is shown. Figure 5 As shown, when the test case accesses the bus according to the pre-allocated address 0x1000_2000, the interconnect bus sends a command to Slave3 port. The sideband signal controller then calls the corresponding parsing task `command_parse` based on the received command. According to the defined command format, it controls the multi-bit data signal and sends this signal to the transceiver (deserializer) via serial protocol. This module recovers the received single-bit signal (i.e., each data bit) and outputs it to the port. Finally, the output multi-bit wide signal is connected to the corresponding port signal on the DUT. The specific implementation process is as follows:

[0071]

[0072]

[0073] As a slave device in the verification environment, the memory is mainly used to store data. When test cases need to pre-set some content into the memory, access control can be performed through the assigned address, or convenient operations on the stored content can be achieved through the DPI function. At the same time, the memory is connected to the DUT. When the DUT performs a write operation on the memory, the test program can access the memory through the bus to obtain the latest value at the corresponding address in order to determine whether the DUT's write operation is correct.

[0074] This embodiment uses C language to control the port signals of all modules. The verification components required in the verification environment are mounted on the interconnect bus. When the behavior of the port signals needs to be controlled in the test case, it is only necessary to access the corresponding address and the predefined command. According to the assigned address, the corresponding verification component can be automatically routed through the interconnect bus. The verification component generates control over various verification components such as clock, reset, sideband signals, and peripheral memory according to the received command, thereby realizing the control of the behavior of all port signals in C language.

[0075] A second aspect of the present invention also provides a signal control system based on a chip verification system. Figure 6 The diagram shown is a schematic representation of an embodiment of the signal control system based on a chip verification system provided by the present invention. Figure 6 As shown, a signal control system based on a chip verification system is generated using C language. The system includes: an address space allocation module 10, configured to connect the device under test (DUT) and multiple verification components in the chip verification system to an interconnect bus, and allocate corresponding address spaces for the multiple verification components; a command issuing module 20, configured to respond to test cases by accessing the interconnect bus according to the allocated address, with the interconnect bus identifying the corresponding verification component based on the address space, and issuing commands to the port where the corresponding verification component is connected to the interconnect bus; and a signal control module 30, configured to have the corresponding verification component obtain commands from the port, parse the commands to identify the corresponding opcode, generate corresponding signals based on the opcode, and perform related operations so that the signals can be used by the DUT.

[0076] A third aspect of the present invention also provides a computer-readable storage medium. Figure 7 A schematic diagram of a computer-readable storage medium for implementing a signal control method for a chip verification system according to an embodiment of the present invention is shown. Figure 7 As shown, the computer-readable storage medium 3 stores computer program instructions 31. When executed by a processor, the computer program instructions 31 implement the method of any of the above embodiments.

[0077] It should be understood that, where there is no conflict, all the embodiments, features and advantages described above for the signal control method based on the chip verification system according to the present invention are equally applicable to the signal control system and storage medium based on the chip verification system according to the present invention.

[0078] A fourth aspect of the present invention also provides a computer device, including as follows: Figure 8 The memory 402 and processor 401 shown are provided. The memory 402 stores a computer program that, when executed by the processor 401, implements the method of any of the above embodiments.

[0079] like Figure 8 The diagram shown is a hardware structure schematic of an embodiment of a computer device for executing a signal control method based on a chip verification system provided by the present invention. Figure 8 Taking the computer device shown as an example, this computer device includes a processor 401 and a memory 402, and may also include an input device 403 and an output device 404. The processor 401, memory 402, input device 403, and output device 404 can be connected via a bus or other means. Figure 8 Taking a bus connection as an example, input device 403 can receive input digital or character information, and generate key signal inputs related to user settings and function control of the signal control system based on the chip verification system. Output device 404 may include display devices such as a display screen.

[0080] Memory 402, as a non-volatile computer-readable storage medium, can be used to store non-volatile software programs, non-volatile computer-executable programs, and modules, such as the program instructions / modules corresponding to the signal control method based on the chip verification system in this embodiment. Memory 402 may include a program storage area and a data storage area, wherein the program storage area may store the operating system and application programs required for at least one function; the data storage area may store data created by the use of the signal control method based on the chip verification system, etc. In addition, memory 402 may include high-speed random access memory and may also include non-volatile memory, such as at least one disk storage device, flash memory device, or other non-volatile solid-state storage device. In some embodiments, memory 402 may optionally include memory remotely located relative to processor 401, and these remote memories can be connected to the local module via a network. Examples of such networks include, but are not limited to, the Internet, corporate intranets, local area networks, mobile communication networks, and combinations thereof.

[0081] The processor 401 executes various functional applications and data processing of the server by running non-volatile software programs, instructions and modules stored in the memory 402, thereby implementing the signal control method based on the chip verification system in the above method embodiment.

[0082] Finally, it should be noted that the computer-readable storage medium (e.g., memory) described herein can be volatile memory or non-volatile memory, or may include both volatile and non-volatile memory. By way of example, and not limitation, non-volatile memory may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memory may include random access memory (RAM), which can act as external cache memory. By way of example, and not limitation, RAM can be obtained in various forms, such as synchronous RAM (DRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), dual data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), and direct Rambus RAM (DRRAM). The storage devices disclosed herein are intended to include, but are not limited to, these and other suitable types of memory.

[0083] Those skilled in the art will also understand that the various exemplary logic blocks, modules, circuits, and algorithm steps described in conjunction with the disclosure herein can be implemented as electronic hardware, computer software, or a combination of both. To clearly illustrate this interchangeability between hardware and software, the functionality of various illustrative components, blocks, modules, circuits, and steps has been generally described. Whether this functionality is implemented as software or as hardware depends on the specific application and the design constraints imposed on the system as a whole. Those skilled in the art can implement the functionality in various ways for each specific application, but such implementation decisions should not be construed as departing from the scope of the embodiments disclosed herein.

[0084] The above are exemplary embodiments disclosed in this invention. However, it should be noted that various changes and modifications can be made without departing from the scope of the embodiments of this invention as defined by the claims. The functions, steps, and / or actions of the methods according to the disclosed embodiments described herein do not need to be performed in any particular order. Furthermore, although the elements disclosed in the embodiments of this invention may be described or claimed individually, they may be understood as multiple unless explicitly limited to a singular number.

[0085] It should be understood that, as used herein, the singular form "a" is intended to include the plural form as well, unless the context clearly supports an exception. It should also be understood that, as used herein, "and / or" refers to any and all possible combinations of one or more of the associatedly listed items. The embodiment numbers disclosed above are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0086] Those skilled in the art should understand that the discussion of any of the above embodiments is merely exemplary and is not intended to imply that the scope of the invention (including the claims) is limited to these examples. Within the framework of the invention, technical features of the above embodiments or different embodiments can be combined, and many other variations of different aspects of the invention exist, which are not provided in the details for the sake of brevity. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the invention should be included within the protection scope of the invention.

Claims

1. A signal control method based on a chip verification system, characterized in that, Implement the following steps using the C language: The device under test (DUT) and multiple verification components in the chip verification system are connected to an interconnect bus, and corresponding address spaces are allocated to the multiple verification components. The multiple verification components include a clock generator, a GPIO control generator, and a sideband signal controller. In response to a test case accessing the interconnect bus according to the assigned address, the interconnect bus identifies the corresponding verification component based on the address space and sends a command to the port where the corresponding verification component is connected to the interconnect bus. The corresponding verification component obtains the command from the port and parses the command to identify the corresponding opcode; In response to the corresponding verification component being the clock generator, the clock generator generates multiple clock signals based on the opcode, performs frequency conversion control and enable control on the multiple clock signals, and connects the multiple clock signals to the corresponding port signals of the device under test for use by the device under test; In response to the corresponding verification component being the GPIO control generator, the GPIO control generator generates a reset signal and a level signal based on the opcode, and connects the reset signal and / or the level signal to the corresponding port signal of the device under test so that it can be used by the device under test; In response to the corresponding verification component being the sideband signal controller, the sideband signal controller generates a multi-bit data signal based on the opcode and sends the multi-bit data signal to the transceiver. The transceiver then recovers each received data signal and outputs it to the port so that the port obtains a multi-bit wide signal. The multi-bit wide signal is then connected to the corresponding port signal of the device under test (DUT) for use by the DUT.

2. The method according to claim 1, characterized in that, The plurality of verification components also include a memory.

3. The method according to claim 2, characterized in that, Also includes: In response to the corresponding verification component being the memory, the device under test (DUT) performs read and write operations on the connected memory.

4. The method according to claim 1, characterized in that, Also includes: The interconnect bus is selected based on the interface type of the device under test, and the interconnect bus includes at least the AHB bus and the AXI bus.

5. A signal control system based on a chip verification system, characterized in that, The system is generated using the C programming language and includes: The address space allocation module is configured to connect the device under test (DUT) and multiple verification components in the chip verification system to the interconnect bus, and allocate corresponding address spaces to the multiple verification components. The multiple verification components include at least a clock generator, a GPIO control generator, and a sideband signal controller. The command issuance module is configured to respond to test cases accessing the interconnect bus according to an assigned address. The interconnect bus identifies the corresponding verification component based on the address space and issues commands to the port connected to the corresponding verification component and the interconnect bus. A signal control module is configured to have the corresponding verification component obtain the command from the port and parse the command to identify the corresponding opcode; in response to the corresponding verification component being the clock generator, the clock generator generates multiple clock signals based on the opcode, performs frequency conversion control and enable control on the multiple clock signals, and connects the multiple clock signals to the corresponding port signals of the device under test (DUT) for use by the DUT; in response to the corresponding verification component being the GPIO control generator, the GPIO control generator generates multiple clock signals based on the opcode. The code generates a reset signal and a level signal, and connects the reset signal and / or the level signal to the corresponding port signal of the device under test (DUT) for use by the DUT; in response to the corresponding verification component being the sideband signal controller, the sideband signal controller generates a multi-bit data signal based on the opcode, sends the multi-bit data signal to the transceiver, and the transceiver recovers each received bit of data signal and outputs it to the port so that the port obtains a multi-bit wide signal, and connects the multi-bit wide signal to the corresponding port signal of the DUT for use by the DUT.

6. A computer-readable storage medium, characterized in that, The system stores computer program instructions that, when executed by a processor, implement the method as described in any one of claims 1-4.

7. A computer device, comprising a memory and a processor, characterized in that, The memory stores a computer program, which, when executed by the processor, performs the method as described in any one of claims 1-4.

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