Memory device and operating method thereof, memory system

Abstract

Embodiments of the present application provide a memory device and an operating method thereof, and a memory system. The memory device includes a memory array and a peripheral circuit coupled with the memory array. The memory array includes a first memory block and a second memory block sharing a same well. The peripheral circuit is configured to apply a first recovery voltage to all word lines of the first memory block during a first program verify recovery operation, and to apply a second recovery voltage to all word lines of the first memory block after applying the first recovery voltage to suppress leakage caused by a parasitic field effect transistor between the first memory block and the second memory block. The first memory block is a selected memory block, and the second memory block is an unselected memory block. The first recovery voltage is the same as or different from the second recovery voltage.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the technical field of semiconductor technology, and particularly relate to a memory device and an operating method thereof, and a memory system. BACKGROUND

[0002] Memory is a memory device used for saving information in modern information technology. As a typical non-volatile semiconductor memory, NAND (Not-And) flash memory has become a mainstream product in the storage market due to its high storage density, controllable production cost, suitable programming and erasing speed, and retention characteristics.

[0003] With the increasing requirements for memory, how to reduce the programming interference in the memory has become one of the technical problems to be solved in the field at present. SUMMARY

[0004] Embodiments of the present application provide a memory device and an operating method thereof, and a memory system.

[0005] In a first aspect, embodiments of the present application provide a memory device, comprising a memory array and a peripheral circuit coupled with the memory array; wherein,

[0006] The memory array comprises a first memory block and a second memory block sharing a same well.

[0007] The peripheral circuit is configured to:

[0008] In the process of performing the first programming verification recovery operation, a first recovery voltage is applied to all word lines of the first memory block; after the first recovery voltage is applied, a second recovery voltage is applied to all word lines of the first memory block to suppress the leakage caused by a parasitic field effect transistor between the first memory block and the second memory block; the first memory block is a selected memory block, and the second memory block is an unselected memory block; the first recovery voltage and the second recovery voltage are the same or different.

[0009] In the above scheme, the peripheral circuit is configured to:

[0010] The first recovery voltage is floated to all word lines of the first memory block.

[0011] The second recovery voltage is floated to all word lines of the first memory block; or the second recovery voltage is continuously applied in the process of the programming verification recovery operation.

[0012] In the above scheme, the peripheral circuit is configured to:

[0013] performing a first programming operation and a first programming verification operation on the memory cells coupled to the selected word line in the first memory block;

[0014] performing the first programming verification recovery operation after the first programming verification operation is completed.

[0015] In the above solution, the peripheral circuit is configured to:

[0016] applying a programming verification voltage to the selected word line in the first memory block and applying a read voltage to the unselected word line in the first memory block to perform a first programming verification operation on the selected word line in the first memory block;

[0017] applying a first recovery voltage to the selected word line after the pulse drop of the programming verification voltage is completed and applying a first recovery voltage to the unselected word line after the pulse drop of the read voltage is completed; or applying a first recovery voltage to the selected word line during the pulse drop of the programming verification voltage and applying a first recovery voltage to the unselected word line during the pulse drop of the read voltage.

[0018] In the above solution, the peripheral circuit is configured to:

[0019] performing a second programming operation on the selected word line in the first memory block after the second recovery voltage is applied to all the word lines in the first memory block;

[0020] the voltage applied to the selected word line when the first programming operation is performed is a first programming voltage, and the voltage applied to the selected word line when the second programming operation is performed is a second programming voltage; the second programming voltage is greater than the first programming voltage.

[0021] In the above solution, the first recovery voltage and the second recovery voltage both range from 1.5V to 4V.

[0022] In the above solution, the memory array further includes a third memory block and a fourth memory block whose word line drivers do not share the same well;

[0023] the peripheral circuit is configured to:

[0024] performing a third programming operation and a second programming verification operation on the memory cells coupled to the selected word line in the third memory block; wherein the third memory block is the selected memory block, and the fourth memory block is the unselected memory block;

[0025] performing a second programming verification recovery operation after the second programming verification operation is completed.

[0026] During execution of the second program verify recovery operation, a first recovery voltage is applied to all word lines of the third memory block.

[0027] In the above aspect, the memory device includes a three-dimensional NAND type memory.

[0028] In a second aspect, an embodiment of the present application provides a memory system, comprising:

[0029] one or more memory devices according to any of the above aspects; and

[0030] a memory controller coupled to the memory device and configured to control the memory device.

[0031] In the above aspect, the memory system includes a memory card or a solid state drive (SSD).

[0032] In a third aspect, an embodiment of the present application provides a method for operating a memory device, comprising:

[0033] During execution of the first program verify recovery operation, a first recovery voltage is applied to all word lines of the first memory block;

[0034] After the first recovery voltage is applied, a second recovery voltage is applied to all word lines of the first memory block to suppress current leakage caused by a parasitic field effect transistor between the first memory block and the second memory block; wherein

[0035] The word line driver of the first memory block and the word line driver of the second memory block share a same well, the first memory block is a selected memory block, and the second memory block is an unselected memory block; the first recovery voltage is the same as or different from the second recovery voltage.

[0036] In the above aspect, the first recovery voltage is applied to all word lines of the first memory block, comprising:

[0037] floating the first recovery voltage to all word lines of the first memory block;

[0038] The second recovery voltage is applied to all word lines of the first memory block, comprising:

[0039] floating the second recovery voltage to all word lines of the first memory block; or continuously applying the second recovery voltage during the program verify recovery operation.

[0040] In the above aspect, the method further comprises:

[0041] performing a first program operation and a first program verify operation on a storage unit coupled to a selected word line in the first memory block;

[0042] After the first program verify operation is completed, the first program verify recovery operation is performed.

[0043] In the above scheme, the program verify operation on the storage unit coupled to the selected word line in the first storage block comprises:

[0044] A program verify voltage is applied to the selected word line in the first storage block, and a read voltage is applied to the unselected word line in the first storage block, so as to perform a first program verify operation on the selected word line in the first storage block.

[0045] The first recovery voltage is applied to all word lines of the first storage block, comprising:

[0046] The first recovery voltage is applied to the selected word line after the pulse drop of the program verify voltage is completed, and the first recovery voltage is applied to the unselected word line after the pulse drop of the read voltage is completed; or the first recovery voltage is applied to the selected word line during the pulse drop of the program verify voltage, and the first recovery voltage is applied to the unselected word line during the pulse drop of the read voltage.

[0047] In the above scheme, the method further comprises:

[0048] After the second recovery voltage is applied to all word lines of the first storage block, a second program operation is performed on the selected word line in the first storage block.

[0049] The voltage applied to the selected word line during the first program operation is a first program voltage, and the voltage applied to the selected word line during the second program operation is a second program voltage; the second program voltage is greater than the first program voltage.

[0050] In the above scheme, the range of the first recovery voltage and the second recovery voltage is 1.5V-4V.

[0051] In the above scheme, the method further comprises:

[0052] A third program operation and a second program verify operation are performed on the selected word line in the third storage block; wherein the word line driver of the third storage block and the word line driver of the fourth storage block do not share the same well, the third storage block is a selected storage block, and the fourth storage block is an unselected storage block.

[0053] After the second program verify operation is completed, a second program verify recovery operation is performed; during the execution of the second program verify recovery operation, the first recovery voltage is applied to all word lines of the third storage block.

[0054] Embodiments of the present application provide a memory device and an operating method thereof, and a memory system. The memory device includes a memory array and a peripheral circuit coupled with the memory array. The memory array includes a first memory block and a second memory block sharing a same well. The peripheral circuit is configured to apply a first recovery voltage to all word lines of the first memory block during a first program verify recovery operation, and to apply a second recovery voltage to all word lines of the first memory block after the first recovery voltage is applied to suppress leakage caused by a parasitic field effect transistor between the first memory block and the second memory block. The first memory block is a selected memory block, and the second memory block is an unselected memory block. The first recovery voltage is the same as or different from the second recovery voltage. In embodiments of the present application, by applying the second recovery voltage to all word lines of the selected first memory block after the program verify operation is completed, the second recovery voltage can improve the leakage problem caused by the parasitic field effect transistor between the first memory block and the second memory block to the selected first memory block, and avoid a high failed bit rate count caused by a threshold voltage distribution shift due to an initial threshold voltage shift (IVS) of the selected first memory block, thereby reducing the probability of program disturbance of the memory device. BRIEF DESCRIPTION OF DRAWINGS

[0055] Figure 1 Schematic diagram of an exemplary system having a memory system according to an embodiment of the present application;

[0056] Figure 2a Schematic diagram of an exemplary memory card having a memory system according to an embodiment of the present application;

[0057] Figure 2b Schematic diagram of an exemplary solid state drive having a memory system according to an embodiment of the present application;

[0058] Figure 3a Schematic diagram of a distribution of memory cells of a three-dimensional NAND type memory according to an embodiment of the present application;

[0059] Figure 3b Schematic diagram of an exemplary memory device including a peripheral circuit according to an embodiment of the present application;

[0060] Figure 4 Schematic diagram of a cross-section of a memory array including NAND memory strings according to an embodiment of the present application;

[0061] Figure 5 Schematic diagram of an exemplary memory device including a memory cell array and a peripheral circuit according to an embodiment of the present application;

[0062] Figure 6 A schematic diagram of the voltage applied on the driver of the first memory block and the second memory block provided by an embodiment of the present application;

[0063] Figure 7a A schematic diagram of the timing of the word line voltage applied on the memory cell during a program operation of an embodiment of the present application Figure 1 ;

[0064] Figure 7b A schematic diagram of the timing of the word line voltage applied on the memory cell during a program operation of an embodiment of the present application

[0065] Figure 8 A schematic diagram of the timing of the word line voltage applied on the memory cell during a program operation of an embodiment of the present application using step-pulse programming

[0066] Figure 9 A schematic diagram of the failed bit rate count of the first memory block and the second memory block provided by an embodiment of the present application;

[0067] Figure 10 A schematic diagram of the implementation flow of the operation method of the memory device of an embodiment of the present application. DETAILED DESCRIPTION

[0068] The exemplary embodiments of this disclosure will be described more fully hereinafter with reference to the accompanying drawings, in which exemplary embodiments of the disclosure are shown. This disclosure may, however, be embodied in many different forms and should not be construed as limited to the exemplary embodiments set forth herein. Rather, these exemplary embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0069] In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present application. However, it will be apparent to one skilled in the art that the present application can be practiced without one or more of these specific details. In other instances, well-known features have not been described in detail to avoid obscuring aspects of the present application.

[0070] In the drawings, the size of layers, regions, elements, and the relative sizes of the same can be exaggerated for clarity. Like reference numbers in different drawings can represent similar elements.

[0071] It will be understood that when an element or layer is referred to as being "on" or "connected to" another element or layer, it can be directly on or connected to the other element or layer or intervening elements or layers can be present. In contrast, when an element is referred to as being "directly on" or "directly connected to" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present application.

[0072] Spatially relative terms, such as "beneath", "below", "lower", "under", "above", "upper" and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if a device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" or "over" the other elements or features. Thus, the exemplary term "below" can encompass both an orientation of above and below. The device can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0073] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the present application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising", when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. As used herein the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0074] In order to enable a more detailed understanding of the features and technical contents of the embodiments of the present application, the implementation of the embodiments of the present application is described in detail below with reference to the accompanying drawings, which are only used for reference and do not limit the embodiments of the present application.

[0075] The memory device in the embodiments of the present application includes but is not limited to a three-dimensional NAND type memory, and is described taking the three-dimensional NAND type memory as an example for ease of understanding.

[0076] With the increasing requirements of the three-dimensional NAND type memory, the size of the peripheral circuit in the three-dimensional NAND type memory is further reduced, in order to enable the reduced peripheral circuit to meet the requirements of the memory array in the three-dimensional NAND type memory, it has become a trend that the word line drivers of different memory blocks share the same well during the programming operation of the memory cells in the three-dimensional NAND type memory. The memory blocks sharing the same well with the word line drivers are selected memory blocks or unselected memory blocks. Due to the fact that these memory blocks share the same well, when a voltage is applied, a coupling effect is easily generated, and the selected memory blocks and the unselected memory blocks interfere with each other, thereby affecting the performance of the three-dimensional NAND type memory.

[0077] In order to solve one or more of the above problems, the embodiments of the present application introduce a solution that can improve the coupling effect between the memory blocks sharing the same well with the word line drivers, improve the leakage problem of the parasitic field effect transistor between the memory blocks sharing the same well with the word line drivers, and thereby improve the performance of the three-dimensional NAND type memory.

[0078] Figure 1 A block diagram of an exemplary system 100 having a memory device in accordance with some aspects of the present application is shown. The system 100 can be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a gaming console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a storage. As shown in Figure 1 The system 100 can include a host 108 and a memory system 102 having one or more memory devices 104 and a memory controller 106, as shown in the middle. The host 108 can be a processor (e.g., a central processing unit (CPU)) or a system on a chip (SoC) (e.g., an application processor (AP)) of an electronic device. The host 108 can be configured to send or receive data to or from the memory device 104.

[0079] According to some embodiments, memory controller 106 is coupled to memory device 104 and host 108 and is configured to control memory device 104. Memory controller 106 can manage data stored in memory device 104 and communicate with host 108. In some embodiments, memory controller 106 is designed to operate in low duty cycle environments, such as Secure Digital (SD) cards, Compact Flash (CF) cards, Universal Serial Bus (USB) flash drives, or other media used in electronic devices such as personal calculators, digital cameras, mobile phones, etc. In some embodiments, memory controller 106 is designed to operate in high duty cycle environments, such as SSDs or embedded multimedia cards (eMMCs), which are used as data storage in mobile devices such as smartphones, tablets, laptops, etc., and in enterprise storage arrays.

[0080] The memory controller 106 can be configured to control the operation of the memory device 104, such as read, erase, and program operations. The memory controller 106 can also be configured to manage various functions relating to data stored or to be stored in the memory device 104, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In some embodiments, the memory controller 106 is also configured to process error correction codes (ECC) relating to data read from or written to the memory device 104. The memory controller 106 can also perform any other suitable functions, such as formatting the memory device 104. The memory controller 106 can communicate with external devices (e.g., host 108) according to specific communication protocols. For example, the memory controller 106 can communicate with external devices through at least one of various interface protocols, such as USB protocol, MMC protocol, Peripheral Component Interconnect (PCI) protocol, PCI High Speed ​​(PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer Small Interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, Integrated Drive Electronic Devices (IDE) protocol, Firewire protocol, etc.

[0081] The memory controller 106 and one or more memory devices 104 can be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Memory (UFS) package or an eMMC package). That is, the memory system 102 can be implemented and packaged into different types of end electronic products. Figure 2aIn one example shown, the memory controller 106 and a single memory device 104 may be integrated into a memory card 202. The memory card 202 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 202 may also include a connection between the memory card 202 and a host computer (e.g., Figure 1 The host 108) is coupled to the memory card connector 204. In such a... Figure 2b In another example shown, the memory controller 106 and multiple memory devices 104 may be integrated into the SSD 206. The SSD 206 may also include components for connecting the SSD 206 to a host computer (e.g., Figure 1 The SSD connector 208 is coupled to the host 108. In some embodiments, the storage capacity and / or operating speed of the SSD 206 is greater than the storage capacity and / or operating speed of the memory card 202.

[0082] Figure 3a An exemplary schematic diagram of a three-dimensional NAND flash memory array is provided, such as... Figure 3a As shown, the memory array of a three-dimensional NAND flash memory consists of several rows of parallel, staggered rows of memory cells parallel to the gate isolation structure. Each two rows of memory cells are separated by a gate isolation structure and an up-select gate isolation structure. Each row of memory cells includes multiple memory cells. The gate isolation structure may include a first gate isolation structure and a second gate isolation structure. The first gate isolation structure divides the memory array into multiple blocks. Multiple second gate isolation structures can divide the blocks into multiple finger regions. An up-select gate isolation structure located in the middle of each finger region can divide the finger region into two parts, thus dividing the finger region into two strings.

[0083] It should be noted that, Figure 3a The number of rows of memory cells between the gate isolation structure and the top-select gate isolation structure given is merely an exemplary example and is not intended to limit the number of rows of memory cells contained in a single memory region of the three-dimensional NAND memory in this invention. In practical applications, the number of rows of memory cells contained in a single memory region can be adjusted according to actual conditions, such as 2, 4, 8, 16, etc.

[0084] Figure 3b A schematic circuit diagram of an exemplary memory device 300 including peripheral circuitry according to some aspects of the present invention is shown. The memory device 300 may be...Figure 1 The memory device 300 can include a memory array 301 and a peripheral circuit 302 coupled to the memory array 301. By way of example, the memory array 301 is illustrated as a three-dimensional NAND type memory array in which memory cells 306 are provided in an array of NAND memory strings 308 that each extend vertically above a substrate (not shown). In some embodiments, each NAND memory string 308 includes a plurality of memory cells 306 that are coupled in series and stacked vertically. Each memory cell 306 can hold a continuous analog value, e.g., a voltage or charge, that depends on the number of electrons captured within a region of the memory cell 306. Each memory cell 306 can be a floating gate type of memory cell that includes a floating gate transistor, or a charge trap type of memory cell that includes a charge-trapping transistor.

[0085] In some embodiments, each memory cell 306 is a single-level cell (SLC) that has two possible memory states and thus can store one bit of data. For example, a first memory state “0” can correspond to a first voltage range, and a second memory state “1” can correspond to a second voltage range. In some embodiments, each memory cell 306 is a multi-level cell (MLC) that can store more than a single bit of data in more than four memory states. For example, an MLC can store two bits per cell, three bits per cell (also referred to as triple-level cells (TLC)), or four bits per cell (also referred to as quad-level cells (QLC)). Each MLC can be programmed to take on a range of possible nominal storage values. In one example, if each MLC stores two bits of data, the MLC can be programmed to take on one of three possible programmed levels from an erased state by writing one of three possible nominal storage values to the cell. A fourth nominal storage value can be used for the erased state.

[0086] As Figure 3bAs shown in FIG. 3, each NAND memory string 308 can include a lower select gate (BSG) 310 at its source end and an upper select gate (TSG) 312 at its drain end. The BSG 310 and TSG 312 can be configured to activate a selected NAND memory string 308 during read and program operations. In some embodiments, the sources of the NAND memory strings 308 in the same memory block 304 are coupled through the same source line (SL) 314 (e.g., a common SL). In other words, according to some embodiments, all NAND memory strings 308 in the same memory block 304 have an array common source (ACS). According to some embodiments, the TSG 312 of each NAND memory string 308 is coupled to a respective bit line (BL) 316 from which data can be read or written via an output bus (not shown). In some embodiments, each NAND memory string 308 is configured to be selected or deselected by applying a select voltage (e.g., above the threshold voltage of the transistor with the TSG 312) or a deselect voltage (e.g., 0 V) to the respective TSG 312 via one or more TSG lines 313 and / or by applying a select voltage (e.g., above the threshold voltage of the transistor with the BSG 310) or a deselect voltage (e.g., 0 V) to the respective BSG 310 via one or more BSG lines 315.

[0087] As Figure 3bAs shown, NAND memory strings 308 can be organized into multiple memory blocks 304, each of which may have a common source line 314 (e.g., coupled to ground). In some embodiments, each memory block 304 is the basic data unit for an erase operation, i.e., all memory cells 306 on the same memory block 304 are erased simultaneously. To erase memory cells 306 in a selected memory block 304a, an erase voltage (Vers) (e.g., a high positive voltage (e.g., 20V or higher)) can be used to bias and couple the source line 314 of the selected memory block 304a and the unselected memory block 304b on the same face as the selected memory block 304a. It should be understood that in some examples, erase operations can be performed at the half-block level, at the quarter-block level, or at a level with any suitable number of memory blocks or any suitable fraction of memory blocks. Memory cells 306 of adjacent NAND memory strings 308 can be coupled via word lines 318, which select which row of memory cells 306 is affected by read and program operations. In some implementations, each word line 318 is coupled to a page 320 of memory cell 306, where page 320 is the basic data unit used for programming operations. The size of a page 320, in bits, can be related to the number of NAND memory strings 308 coupled by word lines 318 in a memory block 304. Each word line 318 may include multiple control gates (gate electrodes) at each memory cell 306 in the corresponding page 320, as well as gate lines coupling the control gates. (This is in conjunction with the preceding...) Figure 3a A page 320 contains multiple memory cells 306, which are separated by an up-select gate isolation structure and a gate isolation structure. The memory cells between the up-select gate isolation structure and the gate isolation structure are arranged into multiple memory cell rows, each of which is parallel to the gate isolation structure and the up-select gate isolation structure. The memory cells in the memory chip that share the same word line form a programmable (read / write) page.

[0088] Figure 4 A schematic cross-sectional view of an exemplary memory array 301 including NAND memory strings 308 is shown according to some aspects of the present invention. Figure 4 As shown, the NAND memory string 308 may include a stacked structure 410, which includes multiple gate layers 411 and multiple insulating layers 412 stacked alternately in sequence, and a memory string 308 perpendicularly penetrating the gate layers 411 and insulating layers 412. The gate layers 411 and insulating layers 412 may be stacked alternately, with adjacent gate layers 411 separated by an insulating layer 412. The number of pairs of gate layers 411 and insulating layers 412 in the stacked structure 410 can determine the number of memory cells included in the memory array 401.

[0089] The constituent material of the gate layers 411 can include an electrically conductive material. The electrically conductive material includes, but is not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some implementations, each gate layer 411 includes a metal layer, e.g., a tungsten layer. In some implementations, each gate layer 411 includes a doped polysilicon layer. Each gate layer 411 can include a control gate that surrounds a memory cell. The gate layers 411 at the top of the layer stack 410 can laterally extend as upper select gate lines, the gate layers 411 at the bottom of the layer stack 410 can laterally extend as lower select gate lines, and the gate layers 411 that laterally extend between the upper select gate lines and the lower select gate lines can as word line layers.

[0090] In some embodiments, the layer stack 410 can be disposed on a substrate 401. The substrate 401 can include silicon (e.g., single crystalline silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or any other suitable material.

[0091] In some embodiments, the NAND memory string 308 includes a channel structure that extends vertically through the layer stack 410. In some implementations, the channel structure includes a channel hole that is filled with a semiconductor material(s) (e.g., as a semiconductor channel) and a dielectric material(s) (e.g., as a memory film). In some implementations, the semiconductor channel includes silicon, e.g., polysilicon. In some implementations, the memory film is a composite dielectric layer that includes a tunneling layer, a storage layer (also referred to as a “charge-trapping / storage layer”), and a blocking layer. The channel structure can have a cylindrical shape (e.g., a column shape). According to some implementations, the semiconductor channel, the tunneling layer, the storage layer, and the blocking layer are arranged radially from the center of the column toward the outer surface of the column in this order. The tunneling layer can include silicon oxide, silicon oxynitride, or any combination thereof. The storage layer can include silicon nitride, silicon oxynitride, or any combination thereof. The blocking layer can include silicon oxide, silicon oxynitride, a high-k dielectric, or any combination thereof. In one example, the memory film can include a composite layer of silicon oxide / silicon oxynitride / silicon oxide (ONO).

[0092] Referring back to Figure 3bThe peripheral circuitry 302 can be coupled to the memory array 301 through the bit lines 316, word lines 318, source lines 314, BSG lines 315, and TSG lines 313. The peripheral circuitry 302 can include any suitable analog, digital, and / or mixed-signal circuitry to facilitate the operation of the memory array 301 by applying voltage and / or current signals to and sensing voltage and / or current signals from each target memory cell 306 through the bit lines 316, word lines 318, source lines 314, BSG lines 315, and TSG lines 313. The peripheral circuitry 302 can include various types of peripheral circuitry formed using metal-oxide-semiconductor (MOS) technology. For example, Figure 5 Some example peripheral circuitry is shown, the peripheral circuitry 302 includes a page buffer / sense amplifier 504, a column decoder / bit line driver 506, a row decoder / word line driver 508, a voltage generator 510, a control logic unit 512, registers 514, an interface 516, and a data bus 518. It should be understood that additional peripheral circuitry not shown in FIG. 5 can also be included in some examples. Figure 5

[0093] The page buffer / sense amplifier 504 can be configured to read data from and program (write) data to the memory array 301 according to control signals from the control logic unit 512. In one example, the page buffer / sense amplifier 504 can store a page of program data (write data) to be programmed into one page 320 of the memory array 301. In another example, the page buffer / sense amplifier 504 can perform a program verify operation to ensure that data has been correctly programmed into the memory cells 306 coupled to a selected word line 318. In yet another example, the page buffer / sense amplifier 504 can also sense a low-power signal from the bit line 316 representing a data bit stored in the memory cell 306 and amplify the small voltage swing to an identifiable logic level in a read operation. The column decoder / bit line driver 506 can be configured to be controlled by the control logic unit 512 and select one or more NAND memory strings 308 by applying a bit line voltage generated from the voltage generator 510.

[0094] ​The row decoder / word line driver 508 can be configured to be controlled by the control logic unit 512 and to select / deselect memory blocks 304 of the memory array 301 and to select / deselect word lines 318 of the memory blocks 304. The row decoder / word line driver 508 can also be configured to drive the word lines 318 using word line voltages generated from the voltage generator 510. In some embodiments, the row decoder / word line driver 508 can also select / deselect and drive the BSG line 315 and the TSG line 313. As described in detail below, the row decoder / word line driver 508 is configured to perform a program operation on memory cells 306 coupled to the selected word line(s) 318. The voltage generator 510 can be configured to be controlled by the control logic unit 512 and to generate word line voltages (e.g., read voltages, program voltages, pass voltages, local voltages, verify voltages, etc.), bit line voltages, and source line voltages to be supplied to the memory array 301.

[0095] In some embodiments, the program operation can include a plurality of steps. For example, the program operation can include a bit line set step, a program perform step, and a program recovery step. After the program operation is performed, a program verify operation is performed. After the program verify operation is performed, a program verify recovery operation is performed. During the bit line set step of the program operation, the voltage can be maintained at ground voltage GND for unselected word lines. During the program perform step of the program operation, a pass voltage Vpass can be applied to unselected word lines and a program voltage Vpgm can be applied to selected word lines. Thus, the memory cells connected to the selected word lines can be programmed. During the program recovery step of the program operation, the voltage applied to all word lines can be lowered to ground voltage GND.

[0096] During the program verify operation, a verify voltage Vvrf can be applied to selected word lines and a read voltage Vread can be applied to unselected word lines.

[0097] During the program verify recovery operation, a recovery operation of lowering the voltage to ground voltage GND can be performed on both unselected word lines and selected word lines.

[0098] The control logic 512 can be coupled to each of the peripheral circuits described above and configured to control the operation of each of the peripheral circuits. The registers 514 can be coupled to the control logic 512 and include status registers, command registers, and address registers for storing status information, command operation codes (OP codes), and command addresses used to control the operation of each of the peripheral circuits. The interface 516 can be coupled to the control logic 512 and act as a control buffer to buffer control commands received from a host (not shown) and relay them to the control logic 512, and to buffer status information received from the control logic 512 and relay them to the host. The interface 516 can also be coupled to the column decoder / bit line driver 506 via the data bus 518 and act as a data I / O interface and data buffer to buffer data and relay them to or from the memory array 301.

[0099] The embodiments of the present application provide a memory device, the memory device comprising a memory array and a peripheral circuit coupled with the memory array;

[0100] In order to minimize the size of a complementary metal oxide semiconductor (CMOS) to fit more CMOS circuits for the array, word line drivers of different memory blocks share a same well, the memory array in the embodiments of the present application comprises a first memory block and a second memory block sharing a same well, the first memory block is a selected memory block, and the second memory block is an unselected memory block.

[0101] It is found that, on one hand, due to the first memory block and the second memory block sharing a same well, when performing a first programming operation and a verification operation on a selected word line in the first memory block, a parasitic field effect transistor is easily formed between the word line drivers in the peripheral circuits of the two memory blocks, and the weak opening of the parasitic field effect transistor will cause the selected first memory block to leak to the unselected second memory block, so that the word line voltage of the selected first memory block drops, the threshold voltage shifts, and thus the failed bit rate count (FBC) increases during the programming operation; on the other hand, since the bit line is coupled to the TSG, the TSG is connected with the TSG driver, the TSG driver is close to the word line driver, and the word line driver is connected with the word line, therefore, in the discharging process of the bit line of the selected memory block, the drop of the bit line voltage will also cause the drop of the word line voltage, so that the word line voltage of the selected first memory block drops, the threshold voltage shifts, and thus the failed bit rate count increases.

[0102] For a more complete understanding of the present application, reference is made to Figure 6 For a more complete understanding of the present application, reference is made to Figure 6The voltage applied to the driver of the selected first memory block is shown by the left side of the dashed line (for example, the voltage applied to the word line driver is 25V), and the voltage applied to the driver of the unselected second memory block is shown by the right side of the dashed line (for example, the voltage applied to the word line driver is 0V). On the one hand, the parasitic field effect transistor is easily generated at the position framed by the dashed box in Figure 6 When the parasitic field effect transistor is turned on during the programming operation, the voltage of the word line driver of the second memory block and the voltage of the word line driver of the first memory block will affect each other, specifically, the voltage of the word line driver of the second memory block rises, and the voltage of the word line driver of the first memory block drops. The generated parasitic field effect transistor will generate a leakage current along Figure 6 On the other hand, since the bit line is coupled to the upper selection transistor (TSG), and the TSG is connected to the TSG driver, and the TSG driver is close to the word line driver, under the influence of the coupling effect, when the bit line is discharged, it will also cause the voltage of the word line driver to drop.

[0103] After the programming verification operation, applying the first recovery voltage to all the word lines of the first memory block is not enough to recover the voltage of the word line driver.

[0104] Based on one or more of the above problems, embodiments of the present application provide another memory device, which includes a memory array and a peripheral circuit coupled to the memory array;

[0105] The memory array includes a first memory block and a second memory block sharing the same well of the word line driver;

[0106] The peripheral circuit is configured to:

[0107] During the execution of the first programming verification recovery operation, a first recovery voltage is applied to all the word lines of the first memory block; after the first recovery voltage is applied, a second recovery voltage is applied to all the word lines of the first memory block to suppress the leakage current caused by the parasitic field effect transistor between the first memory block and the second memory block; the first memory block is a selected memory block, and the second memory block is an unselected memory block; the first recovery voltage and the second recovery voltage are the same or different.

[0108] In some specific examples, the well can be an n-well or a p-well. The formation of the n-well can include any suitable n-type dopant, such as phosphorus, arsenic, antimony, etc., and / or any combination thereof. The formation of the p-well can include any suitable p-type dopant, such as boron. The dopant can be achieved by ion implantation followed by activation annealing, or by in-situ doping during epitaxy of the active device region.

[0109] In some specific examples, the trap can be formed in a substrate. Here, the substrate can include a single-element semiconductor material substrate (e.g., a silicon (Si) substrate, a germanium (Ge) substrate, etc.), a compound semiconductor material substrate (e.g., a silicon-germanium (SiGe) substrate, etc.), a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GeOI) substrate, etc. Preferably, the substrate is a silicon substrate.

[0110] Here, the selected first memory block is a memory block that needs to be programmed, and the unselected second memory block is a memory block that does not need to be programmed.

[0111] It should be noted that the first memory block and the second memory block are both any memory block in the memory device, and the first memory block and the second memory block are not fixed memory blocks. The first memory block is not always a selected memory block, and the second memory block is not always an unselected memory block. Whether the first memory block and the second memory block are selected memory blocks or unselected memory blocks can be defined according to specific programming operations. For example, there are two memory blocks (a first memory block and a second memory block) in a memory device that share the same trap. In a programming operation, the first memory block is a selected memory block, and the second memory block is an unselected memory block. Then, the first memory block is the first memory block, and the second memory block is the second memory block. In another programming operation, the first memory block is an unselected memory block, and the second memory block is a selected memory block. Then, the first memory block is the second memory block, and the second memory block is the first memory block.

[0112] In some embodiments, the peripheral circuit is configured to:

[0113] perform a first programming operation and a first program verify operation on the memory cells coupled to the selected word line in the first memory block;

[0114] perform the first program verify recovery operation after the first program verify operation is completed.

[0115] Here, as described above, a complete programming cycle includes a programming operation, a program verify operation, and a program verify recovery operation. The programming operation can include a bit line setting step, a programming execution step, and a programming recovery step.

[0116] Here, the first recovery voltage and the second recovery voltage are both applied during the program verify recovery operation.

[0117] It can be understood that, after the first programming operation and the first programming verification operation are performed, the initial threshold voltage of the storage unit is decreased, resulting in that the threshold voltage distribution of the storage unit in different programming states is offset (i.e., the maximum width of the threshold voltage distribution is widened), and at this time, the first recovery voltage needs to be applied to all word lines of the first storage block in the subsequent first programming verification recovery operation, so that the threshold voltage distribution of the storage unit in different programming states returns to normal (i.e., the maximum width of the threshold voltage distribution is narrowed). When the word line driver does not share the same well, the first recovery voltage can basically make the threshold voltage distribution of the storage unit in different programming states return to normal.

[0118] However, due to the existence of the parasitic field effect transistor between the first storage block and the second storage block, the opening of the parasitic field effect transistor causes the word line driver of the first storage block to generate a leakage current into the word line driver of the second storage block, so that the word line voltage of the first storage block is decreased, and the first recovery voltage applied is insufficient to make the threshold voltage distribution of the storage unit in different programming states return to normal, which is manifested as an increase in the failed bit rate. At this time, by applying the second recovery voltage, the leakage current between the first storage block and the second storage block can be suppressed or compensated, so that the threshold voltage distribution of the storage unit in different programming states returns to normal, thereby improving the problem of the increase in the failed bit rate count, and further reducing the probability of programming interference of the memory device.

[0119] In some embodiments, the peripheral circuit includes: a voltage generator and a word line driver; wherein the voltage generator is configured to generate the first recovery voltage and the second recovery voltage to be generated; and the word line driver is configured to apply the generated first recovery voltage and the second recovery voltage to all word lines of the first storage block.

[0120] In some specific examples, the application mode of the second recovery voltage includes multiple cases, and the application mode of the second recovery voltage is specifically introduced as follows.

[0121] In some embodiments, the peripheral circuit is configured to:

[0122] the first recovery voltage is floated to all word lines of the first storage block;

[0123] the second recovery voltage is floated to all word lines of the first storage block; or the second recovery voltage is continuously applied in the programming verification recovery operation.

[0124] Here, the first recovery voltage is floated to all word lines of the first storage block, which can be understood as that, after the first recovery voltage is applied to all word lines of the first storage block, the first recovery voltage is removed.

[0125] Here, the floating the second recovery voltage to all word lines of the first memory block can be understood as removing the second recovery voltage after the second recovery voltage is applied to all word lines of the first memory block.

[0126] Here, the continuously applying the second recovery voltage in the verifying and recovering step can be understood as continuously applying the second recovery voltage in the verifying and recovering step after the first programming operation and before the second programming operation.

[0127] Here, the first recovery voltage and the second recovery voltage can be the same or different. Whether the first recovery voltage and the second recovery voltage are the same or different needs to be adjusted according to specific conditions, as long as the first recovery voltage and the second recovery voltage are within the given voltage range and can meet the actual demand. For example, when the leakage caused by the parasitic field effect transistor between the first memory block and the second memory block is large, the applied second recovery voltage can be greater than the applied first recovery voltage; when the leakage caused by the parasitic field effect transistor between the first memory block and the second memory block is small, the applied second recovery voltage and the first recovery voltage can be the same.

[0128] It can be understood that when the leakage caused by the parasitic field effect transistor between the first memory block and the second memory block is large, the influence of the leakage on the programming operation in the next programming cycle process is still large after the first recovery voltage is applied, and therefore a larger recovery voltage needs to be applied to the first memory block to better improve the leakage problem caused by the parasitic field effect transistor between the first memory block and the second memory block. When the leakage caused by the field effect transistor between the first memory block and the second memory block is small, the influence of the leakage on the programming operation in the next programming cycle process is small after the first recovery voltage is applied, and therefore the applied second recovery voltage does not need to be larger to better improve the leakage problem caused by the parasitic field effect transistor between the first memory block and the second memory block.

[0129] In some embodiments, the peripheral circuit is configured to:

[0130] apply a programming verify voltage to selected word lines in the first memory block and apply a read voltage to unselected word lines in the first memory block to perform a first programming verify operation on the selected word lines in the first memory block;

[0131] apply a first recovery voltage to the selected word lines after the pulse drop of the programming verify voltage is completed and apply the first recovery voltage to the unselected word lines after the pulse drop of the read voltage is completed; or apply the first recovery voltage to the selected word lines during the pulse drop of the programming verify voltage and apply the first recovery voltage to the unselected word lines during the pulse drop of the read voltage.

[0132] Figure 7a and Figure 7b A timing diagram of word line voltage applied to memory cells during a programming operation for an embodiment of the present application. As Figure 7a shown, after the verify perform step is completed during the Nth program cycle, in the verify recovery step, a first recovery voltage Vrcvl is applied to the unselected word lines after the read voltage Vread is completed, a first recovery voltage Vrcvl is applied to the selected word lines after the verify voltage Vvrf is completed, and a second recovery voltage Vrcv2 is applied to all the word lines after the first recovery voltage is applied. Figure 7b shown, after the verify perform step is completed during the Nth program cycle, in the verify recovery step, a first recovery voltage Vrcvl is applied to the unselected word lines during the read voltage Vread is completed, a first recovery voltage Vrcvl is applied to the selected word lines during the verify voltage Vvrf is completed, and a second recovery voltage Vrcv2 is applied to all the word lines after the first recovery voltage is applied.

[0133] It should be noted that, Figure 7a and Figure 7b are only used to illustrate the timing, duration and magnitude relationship of the first recovery voltage and the second recovery voltage, and are not used to limit the timing, duration and magnitude relationship of the first recovery voltage and the second recovery voltage in the embodiments of the present application. In addition to Figure 7a and Figure 7b , in some other embodiments, the second recovery voltage can be applied before the first recovery voltage starts to decrease, the second recovery voltage can be slightly larger than the first recovery voltage, the second recovery voltage can be decreased to ground voltage before the next bit line setting step, or can be decreased to ground voltage during the programming verify recovery operation.

[0134] It should be noted that the voltage in the embodiments of the present application refers to the value of the specific voltage, and the pulse of the voltage refers to the entire voltage application stage from the rising of the voltage, the stable period of the voltage, to the completion of the decrease of the voltage.

[0135] It can be understood that the first recovery voltage and the second recovery voltage can be applied after the pulse of the programming verify voltage is completed or during the decrease of the programming verify voltage.

[0136] In some embodiments, the first recovery voltage and the second recovery voltage are both in the range of 1.5V-4V.

[0137] In some specific examples, the first recovery voltage and the second recovery voltage can have a value of VDD or VCC. For example, the first recovery voltage and the second recovery voltage can have a value of 2.2V; for example, the first recovery voltage and the second recovery voltage can have a value of 2.3V. The ranges of the first recovery voltage and the second recovery voltage and the values of VDD and VCC given above are merely exemplary and are not intended to limit the ranges of the first recovery voltage and the second recovery voltage and the values of VDD and VCC in embodiments of the present application.

[0138] In some embodiments, the memory array further comprises a third memory block and a fourth memory block whose word line drivers do not share a same well;

[0139] The peripheral circuit is configured to:

[0140] performing a third programming operation and a second programming verification operation on the storage cells coupled to the selected word line in the third memory block; wherein the third memory block is the selected memory block and the fourth memory block is the unselected memory block;

[0141] performing a second programming verification recovery operation after the second programming verification operation is completed;

[0142] applying a first recovery voltage to all word lines of the third memory block during the second programming verification recovery operation.

[0143] It should be noted that the word line drivers of the third memory block and the fourth memory block are connected to independent wells, that is, the third memory block and the fourth memory block do not share a same well.

[0144] It can be understood that the second recovery voltage in embodiments of the present application is mainly applied to the word lines of the selected memory block whose word line drivers share a same well. For the selected memory block whose word line drivers do not share a well, there is no leakage problem caused by the word line drivers sharing a same well in the programming verification operation, so it is not necessary to apply the second recovery voltage after the first recovery voltage is applied.

[0145] In some embodiments, the peripheral circuit is configured to:

[0146] performing a second programming operation on the selected word line in the first memory block after the second recovery voltage is applied to all word lines of the first memory block.

[0147] The voltage applied to the selected word line when the first programming operation is performed is a first programming voltage, and the voltage applied to the selected word line when the second programming operation is performed is a second programming voltage; the second programming voltage is greater than the first programming voltage.

[0148] The memory device in the embodiments of the present application includes, but is not limited to, a three-dimensional NAND type memory. For the convenience of understanding, the three-dimensional NAND type memory is taken as an example for description. Programming of the three-dimensional NAND type memory is mostly in the form of incremental step pulse program (ISPP). Figure 8 A schematic diagram of a word line voltage applied to a word line during programming operation in an embodiment of the present application using ISPP.

[0149] For the NAND type memory, when writing operation is performed in the form of incremental step pulse program, the writing operation is performed in units of pages. Taking a certain memory cell in a page as an example, after starting programming, a starting programming voltage Vpgm is first loaded on the memory cell, then a programming verification voltage Vvf_0 is loaded on the memory cell to verify whether the target threshold voltage is written; if the target threshold voltage is not reached, a voltage higher than the starting programming voltage by a preset voltage Vispp is written, and then a programming verification voltage Vvf_1 is loaded to verify whether the target threshold voltage is written; the above process is repeated until it is found in the verification step that the threshold voltage of the memory cell has been written to the target threshold voltage, at which time the programming of the memory cell is completed. In subsequent time, a programming inhibition voltage is applied to the memory cell so that it is no longer programmed; when the threshold voltages of all memory cells in the page are written to the target threshold voltage, the writing process of the entire page is completed. Programming in the above-mentioned form of incremental step pulse program can obtain a narrower final threshold voltage distribution.

[0150] Each programming cycle process includes a programming operation and a programming verification operation. For example, in the programming operation process, a first programming voltage Vpgm is applied to the selected word line, and a pass voltage Vpass is applied to the unselected word line. In the programming verification operation process, a verification voltage Vvfy is applied to the selected word line, and a read voltage Vread is applied to the unselected word line. Next, in the programming operation process of the next programming cycle, a second programming voltage Vpgm+Vispp is applied to the selected word line, and the pass voltage Vpass is applied to the unselected word line. Here, for each programming cycle, the programming voltage is greater than the programming voltage in the previous programming cycle by Vispp.

[0151] In some embodiments, the memory device includes a three-dimensional NAND type memory.

[0152] However, the memory device in the embodiments of the present application is not limited to the three-dimensional NAND type memory. In the embodiments of the present application, the memory device can be a semiconductor memory, including but not limited to a three-dimensional NAND flash memory, a vertical NAND flash memory, a NOR flash memory, a dynamic random access memory (DRAM), a ferroelectric random access memory (FRAM), a magnetoresistive random access memory (MRAM), a phase change random access memory (PCRAM), a resistive random access memory (RRAM), or a nano random access memory (NRAM), etc.

[0153] In the embodiments of the present application, the threshold voltage shift problem caused by the initial threshold voltage shift is solved by applying the second recovery voltage to the word line of the selected first memory block after the end of the programming operation, so that the memory device will not generate a high failure bit rate count due to the threshold voltage distribution shift caused by the initial threshold voltage shift, and the influence on the programming performance is small.

[0154] Figure 9 The failure bit rate count of the first memory block and the second memory block provided by the embodiments of the present application is shown. From Figure 9 It can be seen from the figure that the failure bit rate count of the first memory block is high without applying the second recovery voltage, and the failure bit rate count of the first memory block is significantly reduced after applying the second recovery voltage.

[0155] The embodiment of the present application provides a memory device, including a memory array and a peripheral circuit coupled with the memory array; the memory array includes a first memory block and a second memory block sharing a same well; the peripheral circuit is configured to: apply a first recovery voltage to all word lines of the first memory block in a process of performing a first program verify recovery operation; after applying the first recovery voltage, apply a second recovery voltage to all word lines of the first memory block to suppress current leakage caused by a parasitic field effect transistor between the first memory block and the second memory block; the first memory block is a selected memory block, and the second memory block is an unselected memory block; the first recovery voltage is the same as or different from the second recovery voltage. In the embodiment of the present application, by applying the second recovery voltage to all word lines of the selected first memory block after completing the program verify operation, the second recovery voltage can improve the current leakage problem of the selected first memory block caused by the parasitic field effect transistor between the first memory block and the second memory block, avoid a high failed bit rate count caused by threshold voltage distribution deviation of the selected first memory block due to initial threshold voltage drop, and thus reduce the probability of program interference of the memory device.

[0156] The embodiment of the present application further provides a memory system, and the memory system includes:

[0157] one or more memory devices as described in any of the above embodiments; and

[0158] a memory controller coupled with the memory device and controlling the memory device.

[0159] Here, the specific structure and components of the memory system can refer to the related structure and components of the memory system 102 in the foregoing Figure 1 、 Figure 2a 、 Figure 2b . For the sake of brevity, the details are not repeated here.

[0160] In some embodiments, the memory system includes a memory card or a solid state disk.

[0161] Based on the above memory device, the embodiment of the present application further provides an operation method of a memory device, as shown in Figure 10 , the method includes:

[0162] Step 1001: applying a first recovery voltage to all word lines of the first memory block in a process of performing a first program verify recovery operation;

[0163] Step 1002: after applying the first recovery voltage, a second recovery voltage is applied to all word lines of the first memory block to suppress leakage caused by a parasitic field effect transistor between the first memory block and the second memory block; wherein,

[0164] The word line driver of the first memory block and the word line driver of the second memory block share the same well, the first memory block is a selected memory block, and the second memory block is an unselected memory block; the first recovery voltage is the same as or different from the second recovery voltage.

[0165] In some embodiments, the first recovery voltage is applied to all word lines of the first memory block, including:

[0166] The first recovery voltage is floated to all word lines of the first memory block;

[0167] The second recovery voltage is applied to all word lines of the first memory block, including:

[0168] The second recovery voltage is floated to all word lines of the first memory block; or the second recovery voltage is continuously applied during a programming verification recovery operation.

[0169] In some embodiments, the method further includes:

[0170] Performing a first programming operation and a first programming verification operation on a storage unit coupled to a selected word line in the first memory block;

[0171] After completing the first programming verification operation, performing the first programming verification recovery operation.

[0172] In some embodiments, the programming verification operation on the storage unit coupled to the selected word line in the first memory block includes:

[0173] Applying a programming verification voltage to the selected word line in the first memory block and applying a read voltage to an unselected word line in the first memory block to perform a first programming verification operation on the selected word line in the first memory block;

[0174] The first recovery voltage is applied to all word lines of the first memory block, including:

[0175] The first recovery voltage is applied to the selected word line after the pulse drop of the programming verification voltage is completed, and the first recovery voltage is applied to the unselected word line after the pulse drop of the read voltage is completed; or the first recovery voltage is applied to the selected word line during the pulse drop of the programming verification voltage, and the first recovery voltage is applied to the unselected word line during the pulse drop of the read voltage.

[0176] In some embodiments, the first recovery voltage and the second recovery voltage each ranges from 1.5V to 4V.

[0177] In some embodiments, the method further comprises:

[0178] After applying the second recovery voltage to all word lines of the first memory block, performing a second programming operation on the selected word line in the first memory block;

[0179] The voltage applied to the selected word line when performing the first programming operation is a first programming voltage, and the voltage applied to the selected word line when performing the second programming operation is a second programming voltage; the second programming voltage is greater than the first programming voltage.

[0180] In some embodiments, the method further comprises:

[0181] performing a third programming operation and a second programming verification operation on a selected word line in a third memory block; wherein the word line driver of the third memory block and the word line driver of a fourth memory block are not shared by the same well, the third memory block is a selected memory block, and the fourth memory block is an unselected memory block;

[0182] After completing the second programming verification operation, performing a second programming verification recovery operation; during the execution of the second programming verification recovery operation, applying a first recovery voltage to all word lines of the third memory block.

[0183] It should be understood that the reference to “one embodiment” or “an embodiment” throughout the specification means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the application. Therefore, appearances of the phrases “in one embodiment” or “in an embodiment” in various places throughout the specification are not necessarily referring to the same embodiment. Furthermore, the particular features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that the size of the sequence of the above-mentioned processes does not mean the execution order in various embodiments of the application. The execution order of the processes should be determined according to the function and inherent logic, and should not constitute any limitation on the implementation process of the embodiments of the application. The sequence number of the above-mentioned embodiments of the application is only for description, and does not represent the advantages and disadvantages of the embodiments.

[0184] The methods disclosed in the several method embodiments provided by the application can be combined in any suitable manner without conflict, to obtain new method embodiments.

[0185] The above merely illustrates the specific embodiments of the present application, but the protection scope of the present application is not limited thereto, any person skilled in the art can easily think of the changes or replacements within the technical range disclosed by the present application, which should be covered in the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A memory device, characterized in that, The memory device includes: a memory array and peripheral circuitry coupled to the memory array; wherein, The memory array includes a first memory block and a second memory block sharing the same well for word line drivers; The peripheral circuit is configured as follows: During the execution of the first programming verification recovery operation, a first recovery voltage is applied to all word lines of the first memory block; after applying the first recovery voltage, a second recovery voltage is applied to all word lines of the first memory block to suppress leakage current caused by parasitic field-effect transistors between the first memory block and the second memory block; the first memory block is a selected memory block, and the second memory block is an unselected memory block; the first recovery voltage and the second recovery voltage may be the same or different.

2. The memory device according to claim 1, characterized in that, The peripheral circuit is configured as follows: All word lines of the first memory block are floated to the first recovery voltage; The second recovery voltage is floated on all word lines of the first memory block; or, the second recovery voltage is continuously applied during the programming verification recovery operation.

3. The memory device according to claim 1, characterized in that, The peripheral circuit is configured as follows: Perform a first programming operation and a first programming verification operation on the selected word-line coupled memory cell in the first memory block; After completing the first programming verification operation, the first programming verification recovery operation is executed.

4. The memory device according to claim 3, characterized in that, The peripheral circuit is configured as follows: A programming verification voltage is applied to the selected word lines in the first memory block, and a read voltage is applied to the unselected word lines in the first memory block to perform a first programming verification operation on the selected word lines in the first memory block. A first recovery voltage is applied to the selected word line after the pulse of the applied programming verification voltage has finished falling, and a first recovery voltage is applied to the unselected word line after the pulse of the applied read voltage has finished falling; or, a first recovery voltage is applied to the selected word line during the pulse of the applied programming verification voltage, and a first recovery voltage is applied to the unselected word line during the pulse of the applied read voltage.

5. The memory device according to claim 3, characterized in that, The peripheral circuit is configured as follows: After applying the second recovery voltage to all word lines of the first memory block, a second programming operation is performed on the selected word lines in the first memory block; The voltage applied to the selected word line during the first programming operation is the first programming voltage, and the voltage applied to the selected word line during the second programming operation is the second programming voltage. The second programming voltage is greater than the first programming voltage.

6. The memory device according to claim 1, characterized in that, The range of both the first recovery voltage and the second recovery voltage is 1.5V-4V.

7. The memory device according to claim 1, characterized in that, The memory array also includes a third and a fourth memory block whose word line drivers do not share the same well; The peripheral circuit is configured as follows: A third programming operation and a second programming verification operation are performed on the selected word-line coupled memory cells in the third memory block; wherein the third memory block is the selected memory block and the fourth memory block is the unselected memory block; After completing the second programming verification operation, perform the second programming verification recovery operation; During the execution of the second programming verification recovery operation, a first recovery voltage is applied to all word lines of the third memory block.

8. The memory device according to claim 1, characterized in that, The memory device includes a three-dimensional NAND type memory.

9. A memory system, comprising: One or more memory devices as described in any one of claims 1 to 8; as well as A memory controller, which is coupled to and controls the memory device.

10. The memory system according to claim 9, characterized in that, The memory system includes a memory card or a solid-state drive.

11. A method of operating a memory device, characterized in that, include: During the execution of the first programming verification recovery operation, a first recovery voltage is applied to all word lines of the first memory block; After applying the first recovery voltage, a second recovery voltage is applied to all word lines of the first memory block to suppress leakage current caused by parasitic field-effect transistors between the first and second memory blocks; wherein... The word line driver of the first memory block and the word line driver of the second memory block share the same well. The first memory block is the selected memory block, and the second memory block is the unselected memory block. The first recovery voltage is the same as or different from the second recovery voltage.

12. The method according to claim 11, characterized in that, A first recovery voltage is applied to all word lines of the first memory block, including: All word lines of the first memory block are floated to the first recovery voltage; Applying a second recovery voltage to all word lines of the first memory block includes: The second recovery voltage is floated on all word lines of the first memory block; or, the second recovery voltage is continuously applied during the programming verification recovery operation.

13. The method according to claim 11, characterized in that, The method further includes: Perform a first programming operation and a first programming verification operation on the selected word-line coupled memory cell in the first memory block; After completing the first programming verification operation, the first programming verification recovery operation is executed.

14. The method according to claim 13, characterized in that, Perform programming verification operations on the selected word-line-coupled memory cells in the first memory block, including: A programming verification voltage is applied to the selected word lines in the first memory block, and a read voltage is applied to the unselected word lines in the first memory block to perform a first programming verification operation on the selected word lines in the first memory block. Applying a first recovery voltage to all word lines of the first memory block includes: A first recovery voltage is applied to the selected word line after the pulse of the applied programming verification voltage has finished falling, and a first recovery voltage is applied to the unselected word line after the pulse of the applied read voltage has finished falling; or, a first recovery voltage is applied to the selected word line during the pulse of the applied programming verification voltage, and a first recovery voltage is applied to the unselected word line during the pulse of the applied read voltage.

15. The method according to claim 13, characterized in that, The method further includes: After applying the second recovery voltage to all word lines of the first memory block, a second programming operation is performed on the selected word lines in the first memory block; The voltage applied to the selected word line during the first programming operation is the first programming voltage, and the voltage applied to the selected word line during the second programming operation is the second programming voltage; the second programming voltage is greater than the first programming voltage.

16. The method according to claim 11, characterized in that, The range of both the first recovery voltage and the second recovery voltage is 1.5V-4V.

17. The method according to claim 11, characterized in that, The method further includes: A third programming operation and a second programming verification operation are performed on the selected word lines in the third memory block; wherein the word line driver of the third memory block and the word line driver of the fourth memory block do not share the same well, the third memory block is the selected memory block, and the fourth memory block is the unselected memory block; After the second programming verification operation is completed, a second programming verification recovery operation is performed; during the execution of the second programming verification recovery operation, a first recovery voltage is applied to all word lines of the third memory block.

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