A board-level fan-out packaging method for improving chip alignment accuracy

Abstract

The present invention provides a board-level fan-out packaging method for improving chip alignment accuracy. The method obtains a first image of a substrate feature pattern and a chip feature pattern, performs positioning processing, obtains initial position information of the chip feature pattern relative to the substrate feature pattern, and combines the second image with the chip feature pattern to perform data processing to obtain actual position information of the chip feature pattern relative to the substrate feature pattern, and corrects theoretical position information of the chip feature pattern relative to the substrate feature pattern in original exposure pattern data to obtain corrected exposure pattern data, and then performs exposure processing on a photosensitive medium layer to form a connecting through hole that exposes a metal disk, thereby achieving precise alignment, reducing manufacturing costs, improving the production yield and capacity of packaging, improving the economic benefits of the industry, and effectively promoting the development of the FOPLP industry.

Description

Technical Field

[0001] The invention belongs to the technical field of semiconductor packaging, and relates to a board-level fan-out packaging method for improving chip alignment accuracy. Background Art

[0002] Fan-out packaging is one of the most representative technologies of advanced packaging. With its development towards multi-chip, 3D SiP and other directions, it is being increasingly used in fields such as 5G, AIoT and HPC.

[0003] There are two major branches of fan-out packaging: wafer-level fan-out packaging (FOWLP) and panel-level fan-out packaging (FOPLP). As a rising star, panel-level packaging has the advantages of low cost and high production capacity due to the large size of the panel and higher carrier utilization rate, bringing economies of scale far higher than wafer-level fan-out packaging, and the core RDL (Redistribution Layer) technology has also received more attention from the industry.

[0004] The core of RDL technology is to deposit metal layers and dielectric layers and form corresponding metal wiring patterns to re-layout the I / O ports of the chip and arrange them in new areas with looser pitch. Among them, the ability to produce high-quality fine lines is the strength of RDL, but the preparation of board-level RDL still faces huge challenges. For example, in order to realize the PLP module based on buried chips and RDL, the process step of filling the plastic packaging material when burying the chip cannot avoid chip displacement (Die shift), which will cause position deviation between the connection hole and the metal plate (Pad) of the chip, affecting the alignment and interconnection between RDL and the chip Pad; secondly, when the organic substrate is cured, there is expansion, contraction and deformation, which will affect the connection between the RDL external pins and the chip internal pins; and when the chip mounter is mounting the chip, not only the cavity (Cavity) that accommodates the chip has size deviation, but the equipment also has certain precision errors. These will lead to the problem of low alignment accuracy between RDL and chip Pad, making it impossible to guarantee the alignment accuracy, which will cause problems such as collapse, short circuit, open circuit, etc., affecting product quality.

[0005] Therefore, it is very necessary to provide a board-level fan-out packaging method for improving chip alignment accuracy, so as to adopt a suitable method to detect and correct the Die shift problem in board-level packaging, improve chip alignment accuracy, achieve precise line-hole-pad interconnection, improve product quality, and reduce scrap rate. Summary of the invention

[0006] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a board-level fan-out packaging method with improved chip alignment accuracy, so as to solve the alignment problem of board-level fan-out packaging chips in the prior art.

[0007] To achieve the above-mentioned object and other related objects, the present invention provides a board-level fan-out packaging method for improving chip alignment accuracy, comprising the following steps:

[0008] Providing a substrate, the substrate comprising a first surface and a second surface opposite to each other, the substrate having a substrate characteristic pattern, and a cavity formed in the substrate;

[0009] Providing a temporary carrier, and bonding the temporary carrier to the first surface of the substrate to cover one side of the cavity;

[0010] Providing a chip, placing the chip in the cavity, wherein the active surface of the chip contacts the temporary carrier, and the active surface of the chip has a chip characteristic pattern;

[0011] forming a packaging layer, wherein the packaging layer fills the cavity;

[0012] removing the temporary carrier to expose the active surface of the chip;

[0013] Acquire a first image of the substrate characteristic pattern and the chip characteristic pattern, perform positioning processing, obtain initial position information of the chip characteristic pattern relative to the substrate characteristic pattern, and perform data processing in combination with a second image having the chip characteristic pattern to obtain actual position information of the chip characteristic pattern relative to the substrate characteristic pattern;

[0014] In combination with the actual position information of the chip characteristic pattern relative to the substrate characteristic pattern, the theoretical position information of the chip characteristic pattern relative to the substrate characteristic pattern in the original exposure pattern data is corrected to obtain the corrected exposure pattern data;

[0015] Forming a photosensitive medium layer on the first surface of the substrate, performing exposure in combination with the corrected exposure information, and forming a connecting through hole in the photosensitive medium layer to expose the metal disk located on the active surface of the chip;

[0016] A redistribution layer is formed in contact with the metal pad.

[0017] Optionally, the substrate feature pattern includes a through-hole feature pattern that penetrates the substrate.

[0018] Optionally, the substrate includes a plurality of patch modules, and the substrate characteristic pattern includes a substrate characteristic pattern corresponding to the entire substrate and a module characteristic pattern corresponding to each of the patch modules.

[0019] Optionally, the step of obtaining a first image of the substrate characteristic pattern and the chip characteristic pattern and performing positioning processing includes: using a camera to obtain the substrate characteristic pattern of the substrate for substrate positioning, obtaining the module characteristic pattern of the patch module for patch module positioning, and obtaining the chip characteristic pattern of the chip for chip positioning.

[0020] Optionally, before placing the chip in the cavity, the second image having the characteristic pattern of the chip is acquired by a camera.

[0021] Optionally, a partition exposure method is adopted when exposing the photosensitive medium layer.

[0022] Optionally, the formed connecting through hole is located above the metal disk, and the aperture of the connecting through hole is not larger than the size of the metal disk.

[0023] Optionally, the substrate includes an organic carrier.

[0024] Optionally, the chip feature pattern includes the metal disk located on the active surface of the chip.

[0025] Optionally, the method further includes forming metal solder balls on the redistribution layer.

[0026] As described above, the board-level fan-out packaging method for improving chip alignment accuracy of the present invention obtains a first image of the substrate feature pattern and the chip feature pattern, performs positioning processing, obtains the initial position information of the chip feature pattern relative to the substrate feature pattern, and combines with the second image with the chip feature pattern to perform data processing to obtain the actual position information of the chip feature pattern relative to the substrate feature pattern, and corrects the theoretical position information of the chip feature pattern relative to the substrate feature pattern in the original graphic data to obtain the corrected exposure graphic data, and then exposes the photosensitive medium layer located on the chip to form a connecting through hole that exposes the metal disk located on the active surface of the chip, thereby effectively avoiding the collapse consequences caused by Die shift, reducing manufacturing costs, and improving the production yield and capacity of packaging; reducing the cost waste caused by Die shift and improving the economic benefits of the industry; using fan-out packaging technology, a thinner packaging structure can be produced with a shorter supply chain, which can effectively promote the development of the FOPLP industry. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 It is a schematic diagram of the structure after the chip is placed in the cavity in an embodiment of the present invention.

[0028] Figure 2Shown is a schematic diagram of obtaining a second image of a chip feature pattern through a camera in an embodiment of the present invention.

[0029] Figure 3 It is a schematic diagram of the structure after the encapsulation layer is formed in an embodiment of the present invention.

[0030] Figure 4 It is a schematic diagram showing the removal of the temporary carrier and the use of a camera for positioning operation in an embodiment of the present invention.

[0031] Figure 5 Display as Figure 4 Schematic diagram of the top view of the middle substrate.

[0032] Figure 6 It is a schematic diagram of the structure after the photosensitive medium layer is formed in an embodiment of the present invention.

[0033] Figure 7 It is a schematic diagram of the structure after exposure to form connecting through holes in an embodiment of the present invention.

[0034] Figure 8 It is a schematic diagram of the structure after forming the redistribution layer and the metal solder balls in an embodiment of the present invention.

[0035] Component number description

[0036] 100 substrates

[0037] 101 Substrate Feature Pattern

[0038] 102 Module Feature Graphics

[0039] 103 SMD Module

[0040] 200 Cavity

[0041] 300 Temporary slides

[0042] 400 chips

[0043] 401 Metal Plate

[0044] 402 Chip center position

[0045] 500 cameras

[0046] 600 Encapsulation Layer

[0047] 700 Photosensitive medium layer

[0048] 800 Connection through hole

[0049] 900 Rewiring Layer

[0050] 110 Metal Solder Balls DETAILED DESCRIPTION

[0051] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0052] For example, when describing the embodiments of the present invention in detail, for the sake of convenience, the cross-sectional view showing the device structure will not be partially enlarged according to the general scale, and the schematic view is only an example, which should not limit the scope of protection of the present invention. In addition, in actual production, the three-dimensional space dimensions of length, width and depth should be included.

[0053] For ease of description, spatially relative terms such as "under", "below", "below", "below", "above", "on", etc. may be used herein to describe the relationship of one element or feature shown in the drawings to other elements or features. It will be understood that these spatially relative terms are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the drawings. In addition, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.

[0054] In the context of the present application, a structure in which a first feature is described as being "above" a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0055] It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and therefore the illustrations only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0056] This embodiment provides a board-level fan-out packaging method for improving chip alignment accuracy, comprising the following steps:

[0057] See also Figure 1 First, step S1 is performed to provide a substrate 100 , wherein the substrate 100 includes a first surface and a second surface opposite to each other, the substrate 100 has a substrate characteristic pattern, and a cavity 200 is formed in the substrate 100 .

[0058] Specifically, in this embodiment, the substrate 100 adopts an organic carrier, but the type of the substrate 100 is not limited thereto. Among them, the cavity for placing the chip 400 can be made on the organic carrier by laser cutting after the etching-development-stripping process. The size of the cavity matches the chip 400, and it is only necessary to add 5-100 μm to each side of the size of the chip 400. For example, the size of the chip 400 in this embodiment is 10×10 mm, and the size of the cavity is the size of the chip 400 plus 5-100 μm on each side. The type and size of the chip 400 and the size of the cavity can be selected according to needs, and no excessive restrictions are made here.

[0059] As an example, the substrate feature pattern may include a through-hole feature pattern penetrating the substrate 100 .

[0060] Specifically, in this embodiment, the substrate feature pattern adopts a through-hole feature pattern that penetrates the substrate 100, but is not limited to this. Other special marks located on the substrate 100 can also be used for positioning, and no excessive restrictions are made here.

[0061] Further, such as Figure 5 In this embodiment, the substrate 100 may include a plurality of patch modules 103, and preferably the substrate feature pattern includes a substrate feature pattern 101 corresponding to the entire substrate and a module feature pattern 102 corresponding to each of the patch modules 103, so as to position the substrate through the substrate feature pattern and position the chip through the chip feature pattern, so as to realize precise alignment operation.

[0062] Next, step S2 is performed to provide a temporary carrier 300 , and the temporary carrier 300 is bonded to the first surface of the substrate 100 to cover one side of the cavity 200 .

[0063] Specifically, in this embodiment, the temporary carrier 300 is a tape, but the type of the temporary carrier 300 is not limited thereto and can be selected according to needs. The tape can be used to close one side of the cavity 200 to provide support for the subsequent mounting of the chip 400.

[0064] Next, step S3 is performed to provide a chip 400 , and the chip 400 is placed in the cavity 200 , the active surface of the chip 400 is in contact with the temporary carrier 300 , and the active surface of the chip 400 has a chip characteristic pattern.

[0065] Specifically, the active surface of the chip 400 refers to the surface with the metal disk 401. In this embodiment, the chip characteristic pattern on the active surface of the chip 400 directly adopts the metal disk 401 located on the chip 400, so as to realize the positioning operation of the chip through the metal disk 401, but the type of the chip characteristic pattern is not limited thereto and can be selected according to needs. When the chip mounter puts the chip 400 into the cavity 200, due to the equipment accuracy error of the chip mounter itself (the best chip mounter accuracy is ±5μm), the chip 400 will produce an initial displacement.

[0066] See also Figure 2 In this embodiment, before the chip 400 is placed in the cavity 200, a second image having the characteristic pattern of the chip can be obtained by a camera 500 such as a CCD camera, and stored in a memory such as a computer for subsequent comparison and application. However, the method of obtaining the second image having the characteristic pattern of the chip is not limited to this. For example, it can also be obtained by a camera before picking up the chip 400, and no excessive restrictions are made here.

[0067] Then, if Figure 3 , executing step S4 to form an encapsulation layer 600 , wherein the encapsulation layer 600 fills the cavity 200 .

[0068] Specifically, after the chip 400 is placed in the cavity 200, an insulating material such as ABF needs to be pressed for plastic sealing to form the packaging layer 600 filling the cavity 200. Due to mold flow resistance and the inconsistency of thermal expansion coefficients among the plastic sealing material, the substrate 100 and the temporary carrier 300, the chip 400 will be caused to die shift during the heating process of the plastic sealing material, and thus, during the curing process, the chip 400 will be secondary shifted due to the different thermal expansion properties of the materials.

[0069] Then, if Figure 4 , execute step S5, remove the temporary carrier 300, and expose the active surface of the chip 400.

[0070] Specifically, the substrate 100 is turned over so that the temporary carrier 300, namely the Tape, faces upward, and then the Tape is removed. At this time, the active surface of the chip 400 faces upward, and the characteristic pattern on the chip 400, namely the metal disk 401, can be exposed.

[0071] Next, execute step S6, obtain the first image of the substrate characteristic pattern and the chip characteristic pattern, perform positioning processing, obtain the initial position information of the chip characteristic pattern relative to the substrate characteristic pattern, and combine with the second image with the chip characteristic pattern to perform data processing to obtain the actual position information of the chip characteristic pattern relative to the substrate characteristic pattern.

[0072] Among them, the steps of obtaining the first image of the substrate characteristic pattern and the chip characteristic pattern and performing positioning processing include: using a camera to obtain the substrate characteristic pattern of the substrate 100 for substrate positioning, obtaining the module characteristic pattern of the patch module 103 for patch module positioning, and obtaining the chip characteristic pattern of the chip 400 for chip positioning.

[0073] Specifically, a CCD camera can be used to identify the substrate feature pattern 101 of the entire substrate 100, and the substrate feature pattern 101 is a large hole located at the four corners of the substrate 100, so as to perform the initial positioning of the substrate 100. After the initial positioning is completed, the module feature pattern 102 around the patch module 103 is scanned by CCD, and the pattern is captured to perform the secondary positioning of the patch module 103. Among them, it is preferred that the aperture of the module feature pattern 102 is smaller than that of the substrate feature pattern 101 to save the space utilization rate of the substrate 100. Then, the module feature pattern 102 is compared with the chip feature pattern, that is, the metal disk 401, and the second image of the chip feature pattern obtained before patching is referred to. Through calculation and correction, the actual position information of the chip feature pattern relative to the substrate feature pattern is finally output, such as automatically generating the coordinates of the chip center position 402 of the chip 400 according to the distribution of the chip 400 in the substrate 100.

[0074] Next, step S7 is executed to correct the theoretical position information of the chip feature pattern relative to the substrate feature pattern in the original exposure pattern data in combination with the actual position information of the chip feature pattern relative to the substrate feature pattern to obtain the corrected exposure pattern data.

[0075] Specifically, the positioning of the chip 400 is usually programmed based on the chip feature pattern obtained by the customer on the chip to locate the coordinates of the center position of the chip. This center is not the geometric center of the chip, but the programming calculation center of the chip's pattern distribution. The pattern of the original exposure pattern data is the idealized position and center position of the programming, etc., but in fact the chip position is offset during the process, which will cause alignment deviation. Therefore, after the actual position information of the chip feature pattern relative to the substrate feature pattern obtained by CCD scanning in this embodiment is compared with the original exposure pattern data, the coordinate position correction can be performed to correct the position of the initial exposure pattern data, so as to finally output a new exposure pattern data, so that the pattern of the new exposure pattern data is as consistent as possible with the actual pattern position after scanning, so as to improve the effectiveness of exposure and achieve precise alignment.

[0076] Then, if Figure 6 and Figure 7 , execute step S8, form a photosensitive medium layer 700 on the first surface of the substrate 100, perform exposure in combination with the corrected exposure information, and form a connecting through hole 800 in the photosensitive medium layer 700 to expose the metal disk 401 located on the active surface of the chip 400.

[0077] Specifically, the photosensitive medium layer (Insulation layer) 700 can be formed on the substrate 100 by slit coating, wherein the main components of the material of the photosensitive medium layer 700 include polyimide, epoxy resin, etc., and then the temperature is raised for curing, and then cooled to room temperature to form the photosensitive medium layer 700. Then, the corrected new exposure pattern data is called out, and exposure is performed to form the connecting through hole 800 to reveal the metal disk 401. When the aperture of the connecting through hole 800 is less than or equal to the size of the metal disk 401, even if the exposure is effective, the interconnection of the electrical signal with the subsequently formed redistribution layer 900 circuit can be achieved, reducing the accumulation of multiple errors and forming precise alignment. In this embodiment, when performing exposure, it is preferred to use partitioned exposure to improve the accuracy of exposure, further reduce the scrap rate, and ensure the effectiveness of exposure.

[0078] In this embodiment, the precision error can be reduced through multiple alignments, and the partitioned exposure can ensure that the problem of the pattern after exposure being unable to be aligned with the metal disk on the chip due to Die shift will not be caused. That is, the problem of the entire board being scrapped can be well solved, thereby reducing cost waste and increasing production efficiency and production quality.

[0079] Next, see Figure 8 , execute step S9 to form a redistribution layer 900 in contact with the metal disk 401.

[0080] Specifically, regarding the production of the redistribution layer (RDL) 900, a metal seed layer may be first formed by a sputtering method, wherein the sputtered metal seed layer may be a nano-scale titanium metal layer and a copper metal layer. Since the titanium metal layer has high conductivity and adhesion, and good thickness flatness, the redistribution layer 900 may be firmly fixed on the photosensitive medium layer 700. Subsequently, the formed metal seed layer is coated with an anti-etching layer material (Slit Coating), exposed, and developed, and then copper electroplating is performed, and then the film formed by the anti-etching layer material is removed, and finally the excess metal seed layer is etched away to complete the preparation of the first layer in the redistribution layer 900. Regarding the number of layers of the redistribution layer 900, there is no excessive restriction here, and it can be prepared as needed.

[0081] Furthermore, after the redistribution layer 900 is manufactured, a photosensitive solder resist layer can be covered on the redistribution layer 900, and a hole exposing the redistribution layer 900 can be formed by photolithography, and then a conductive metal solder ball 110 can be formed in the hole to lead out the electrical signal of the chip 400 in the redistribution layer 900, thereby increasing the density of the circuit and improving practicality.

[0082] In summary, the board-level fan-out packaging method for improving chip alignment accuracy of the present invention obtains a first image of the substrate feature pattern and the chip feature pattern, performs positioning processing, obtains the initial position information of the chip feature pattern relative to the substrate feature pattern, and combines the second image with the chip feature pattern to perform data processing to obtain the actual position information of the chip feature pattern relative to the substrate feature pattern, and corrects the theoretical position information of the chip feature pattern relative to the substrate feature pattern in the original graphic data to obtain the corrected exposure graphic data, and then exposes the photosensitive medium layer located on the chip to form a connecting through hole that exposes the metal disk located on the active surface of the chip, thereby effectively avoiding the collapse consequences caused by Die shift, reducing manufacturing costs, and improving the production yield and capacity of packaging; reducing the cost waste caused by Die shift and improving the economic benefits of the industry; using fan-out packaging technology, a thinner packaging structure can be produced with a shorter supply chain, which can effectively promote the development of the FOPLP industry.

[0083] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A board-level fan-out packaging method for improving chip alignment accuracy, characterized in that: The following steps are involved: Providing a substrate, the substrate comprising a first surface and a second surface opposite to each other, the substrate comprising a plurality of patch modules, the substrate having a substrate characteristic pattern, the substrate characteristic pattern comprising a substrate characteristic pattern corresponding to the entire substrate and a module characteristic pattern corresponding to each of the patch modules, and a cavity is formed in the substrate; providing a temporary carrier, bonding the temporary carrier to the first surface of the substrate to cover one side of the cavity; Providing a chip, wherein an active surface of the chip has a chip characteristic pattern, and acquiring the chip characteristic pattern as a second image; placing the chip in the cavity with the active surface of the chip in contact with the temporary carrier; forming a packaging layer, wherein the packaging layer fills the cavity; removing the temporary carrier to expose the active surface of the chip; Perform positioning processing to obtain the substrate characteristic pattern of the substrate to perform substrate positioning; obtain the module characteristic pattern to perform patch module positioning; obtain the chip characteristic pattern to perform chip positioning; Acquire a first image of the substrate characteristic pattern and the chip characteristic pattern, acquire initial position information of the chip characteristic pattern relative to the substrate characteristic pattern, and perform data processing in combination with a second image having the chip characteristic pattern to acquire actual position information of the chip characteristic pattern relative to the substrate characteristic pattern; In combination with the actual position information of the chip characteristic pattern relative to the substrate characteristic pattern, the theoretical position information of the chip characteristic pattern relative to the substrate characteristic pattern in the original exposure pattern data is corrected to obtain the corrected exposure pattern data; Forming a photosensitive medium layer on the first surface of the substrate, performing exposure in combination with the corrected exposure information, and forming a connecting through hole in the photosensitive medium layer to expose the metal disk located on the active surface of the chip; A redistribution layer is formed in contact with the metal pad.

2. The board-level fan-out packaging method for improving chip alignment accuracy according to claim 1, characterized in that: The substrate feature pattern includes a through-hole feature pattern that penetrates the substrate.

3. The board-level fan-out packaging method for improving chip alignment accuracy according to claim 1, characterized in that: A camera is used to acquire the substrate characteristic pattern and a first image of the chip characteristic pattern of the chip.

4. The board-level fan-out packaging method for improving chip alignment accuracy according to claim 1, characterized in that: The second image having the characteristic pattern of the chip is acquired by a camera.

5. The board-level fan-out packaging method for improving chip alignment accuracy according to claim 1, characterized in that: The partition exposure method is adopted when exposing the photosensitive medium layer.

6. The board-level fan-out packaging method for improving chip alignment accuracy according to claim 1, characterized in that: The formed connecting through hole is located above the metal plate, and the aperture of the connecting through hole is not larger than the size of the metal plate.

7. The board-level fan-out packaging method for improving chip alignment accuracy according to claim 1, characterized in that: The substrate includes an organic carrier.

8. The board-level fan-out packaging method for improving chip alignment accuracy according to claim 1, characterized in that: The chip feature pattern includes the metal pad located on the active surface of the chip.

9. The board-level fan-out packaging method for improving chip alignment accuracy according to claim 1, characterized in that: The method also includes the step of forming metal solder balls on the redistribution layer.

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