Field effect switching device based on channel conductance enhancement

Abstract

The application discloses a field effect switch device based on channel conductance enhancement, and mainly solves the current collapse and low breakdown voltage problems of a gallium nitride-based power transistor. The device comprises, from bottom to top, a substrate, a transition layer, a channel layer and a barrier layer, wherein the upper part of the barrier layer is sequentially provided with a P-type block of a gradually-doped structure, a gate electrode and a gradually-doped modulation island array composed of m parallel back-type modulation islands, a square groove is arranged in each modulation island, and the square grooves form windows; y grooves are arranged on the left side of each modulation island, an inverted L-shaped metal strip is arranged in each groove, the upper side of each metal strip is located on the upper part of the modulation island or the window, and the horizontal part of at least one metal strip among the y metal strips corresponding to each modulation island is provided with a protrusion connected to the barrier layer in the square groove; all the metal strips form island metal, the left side of the island metal is a drain electrode, and the right side of the P-type block is a source electrode. The application can inhibit current collapse, improve the breakdown voltage and be used in a power electronic system.

Description

Technical Field

[0001] This invention belongs to the field of microelectronics technology, and specifically relates to a power transistor that can be used as a basic device in power electronic systems. Technical Background

[0002] Currently, high-performance, high-reliability power transistors have become core components of high-performance, intelligent power electronic systems, playing a crucial role in my country's energy conservation, emission reduction, and green development strategies. However, the performance of traditional silicon-based power transistors is approaching its theoretical limit, making it difficult to meet the urgent requirements of next-generation high-performance power electronic systems for high temperature, high voltage, high frequency, high efficiency, and high power density. In contrast, gallium nitride (GaN)-based power transistors, based on a P-type cap layer GaN heterojunction structure, can achieve superior characteristics such as lower on-resistance, faster switching speed, and higher power density, significantly improving the performance and reliability of power electronic systems and substantially reducing power consumption. Therefore, vigorously developing high-performance, high-reliability GaN-based power transistors is one of the effective measures to help my country achieve its strategic goals of "carbon peaking and carbon neutrality."

[0003] Traditional gallium nitride (GaN)-based power transistors are based on GaN-based heterojunction structures, which include: a substrate 1, a transition layer 2, a channel layer 3, a barrier layer 4, a P-GaN gate 5, a drain 6, a source 7, and a gate metal 8. The drain 6 is deposited on the upper left side of the barrier layer 4, the source 7 is deposited on the upper right side of the barrier layer 4, the P-GaN gate 5 is deposited in the upper middle part of the barrier layer 4, and the gate metal 8 is deposited on top of the P-GaN gate 5. Figure 1 As shown. Due to limitations in material epitaxy technology and device manufacturing processes, traditional gallium nitride-based power transistors generate a large number of defects on the transistor surface and within the transistor. The presence of these defects traps charges, leading to severe current collapse problems and further degrading the reliability and power characteristics of the device. See Effects of hole traps on the temperature dependence of current collapse in a normally-OFF gate-injection transistor, Japanese Journal of Applied Physics, 55(5), 2016.

[0004] Gallium nitride-based power transistors employing field-plate technology modulate the electric field distribution in the depletion region and expand its width by altering the distribution and structure of the field plate between the gate and drain. This effectively suppresses defect charging and discharging, inhibits current collapse during device switching, and improves the device's breakdown voltage. (See Improved Current Collapse in AlGaN / GaN MOS-HEMTs with Dual Field-Plates, 2018 IEEE International Meeting for Future of Electron Devices, Kansai (IMFEDK), pp. 1-2, 2018). However, field-plate technology introduces parasitic capacitance, which degrades the device's frequency characteristics. Furthermore, the field-plate structure increases the complexity of the device manufacturing process and reduces the yield rate. Summary of the Invention

[0005] The purpose of this invention is to address the shortcomings of the prior art by providing a field-effect switching device based on enhanced channel conductivity, which can effectively improve the device's conduction characteristics, suppress current collapse, significantly reduce device power consumption, and improve the device's breakdown voltage, reliability, and power switching characteristics.

[0006] To achieve the above objectives, the technical solution of the present invention includes the following:

[0007] 1. A field-effect switching device based on enhanced channel conductivity, comprising, from bottom to top: a substrate 1, a transition layer 2, a channel layer 3, and a barrier layer 4, wherein a P-type block 5 is disposed on the upper part of the barrier layer 4, a gate 12 is deposited on the upper part of the P-type block 5, and a drain 9 and a source 10 are respectively disposed on the upper left and right edges of the barrier layer 4, characterized in that:

[0008] The P-type block 5 is a graded doping structure, which is distributed from the bottom up as the first to the nth layer. Each layer is composed of P-type semiconductor material with decreasing doping concentration, and each layer has the same thickness.

[0009] The modulation island array 6 consists of m parallel modulation islands of the same size and at equal intervals, where m ≥ 1. Each modulation island has a gradient doping structure, and the doping concentration gradually decreases from bottom to top. Its thickness is less than the thickness of the P-type block 5. All modulation islands are provided with square slots, which form windows 7.

[0010] Inside the channel layer 3 or barrier layer 4, and on the left side of each modulation island, there are y grooves 8. These y grooves are of the same size and are arranged in parallel with equal spacing, where y ≥ 2, that is, the total number of grooves 8 is m × y. Each groove contains an inverted L-shaped metal strip, and the lower side of the vertical part of each inverted L-shaped metal strip is located inside the groove 8. The right side of the vertical part is close to the left side of m modulation islands. The horizontal parts of these inverted L-shaped metal strips are located at the upper part of m modulation islands or inside m square slots. For each modulation island, at least one of the corresponding y inverted L-shaped metal strips has a protrusion on its horizontal part to connect to the barrier layer 4 in the square slot. These m × y metal strips constitute the island metal 11.

[0011] 2. A method for fabricating the above-mentioned field-effect switching device based on enhanced channel conductivity, characterized by comprising the following steps:

[0012] A) Epitaxially grow a GaN-based wide-bandgap semiconductor material on substrate 1 to form a transition layer 2;

[0013] B) Epitaxially grow GaN material on transition layer 2 to form channel layer 3;

[0014] C) Epitaxially grow a GaN-based wide bandgap semiconductor material on the channel layer 3 to form a barrier layer 4 with a thickness of a;

[0015] D) Epitaxially grow P-type semiconductor material on barrier layer 4, and sequentially form n P-type layers with the same thickness and doping concentration gradually decreasing from bottom to top.

[0016] E) A mask is first fabricated on the P-type layer, and the P-type layer is etched using the mask until the upper surface of the barrier layer 4 is reached, forming a P-type block 5 with a thickness of 5 to 500 nm and m parallel squares of the same size and equal spacing on the left side of the P-type block 5. The thickness of these m squares is the same as the thickness of the P-type block 5, and m ≥ 1.

[0017] F) A mask is fabricated a second time on the barrier layer 4, the P-type block 5, and the m square blocks. The m square blocks are further etched using the mask. The etching depth x is less than the thickness of the P-type block 5, forming m square modulation islands with a thickness of g. These m modulation islands constitute the modulation island array 6. The square slots in each modulation island are the same size, and these square slots constitute the window 7.

[0018] G) A mask is fabricated for the third time on the barrier layer 4, P-type block 5, modulation island array 6 and window 7. The barrier layer 4 and channel layer 3 on the left side of each modulation island in the modulation island array 6 are etched using the mask. The etching depth is h. Y equally spaced parallel grooves are formed on the left side of each modulation island. That is, the total number of grooves 8 is m×y.

[0019] H) A mask is fabricated for the fourth time on the barrier layer 4, P-type block 5, modulation island array 6, window 7 and groove 8. Metal is deposited on the upper part of the barrier layer 4 on the left and right sides using the mask, and rapid thermal annealing is performed in N2 atmosphere to complete the fabrication of drain 9 and source 10.

[0020] I) A mask is fabricated for the fifth time on the barrier layer 4, P-type block 5, modulation island array 6, window 7, groove 8, drain 9 and source 10. Using the mask, metal is deposited on the upper part of the modulation island array 6, inside the window 7 and groove 8, and island metal 11 is formed by rapid thermal annealing in N2 atmosphere.

[0021] J) A sixth mask is fabricated on the barrier layer 4, P-type block 5, modulation island array 6, window 7, drain 9, source 10 and island metal 11. Metal is deposited on the upper part of the P-type block 5 using the mask to form the gate 12, thus completing the fabrication of the entire device.

[0022] Compared with traditional gallium nitride-based power transistors, the device of this invention has the following advantages:

[0023] First, it can modulate the channel resistance, improve conduction characteristics, and increase breakdown voltage.

[0024] In this invention, the island metal is placed in the groove and on the surface of the barrier layer, so that after annealing, the island metal will form an alloy with the contacting semiconductor. Each modulation island can be connected to the two-dimensional electron gas inside the device through the island metal, so that the potential of the island metal is between the potential of the device gate and the potential of the drain. When the potential difference between the device gate and the drain increases or decreases, the potential of the island metal will increase or decrease accordingly through the two-dimensional electron gas in contact with it. Therefore, when the device is turned on, the pn junction diode formed by the modulation island and the barrier layer 4 below it is in a forward biased state, and a large number of holes will enter the diode. Inside the device, a considerable number of electrons are attracted in the heterojunction channel between the barrier layer 4 and the channel layer 3, which significantly reduces the channel resistance of the device, improves the conduction characteristics of the device, and reduces the conduction loss. When the device is in blocking operation, the pn junction diode formed by the modulation island and the barrier layer 4 below it can be in a reverse bias state, which can further extend the depletion region in the semiconductor layer near the gate to between the modulation island and the drain. This can further modulate the electric field distribution and intensity in the semiconductor layer between the gate and the drain, causing the electric field in the semiconductor layer of the device to become more uniform, thereby significantly improving the breakdown voltage of the device.

[0025] Second, it can modulate trap behavior and suppress current collapse.

[0026] Because the present invention has a modulation island array on the upper part of the barrier layer 4, when the device switches from the off state to the on state, the pn junction diode formed by each modulation island and the barrier layer 4 below it will be converted to a forward bias state. The pn junction will inject a large number of holes into the device, thereby modulating the trap behavior in the device and suppressing the trap charging and discharging. Therefore, it can effectively suppress the current collapse phenomenon.

[0027] Third, it can achieve high threshold voltage and enhanced channel conductivity.

[0028] This invention employs a P-type layer with a doping concentration that gradually decreases from bottom to top. P-type blocks 5 and modulation islands are formed by etching the P-type layer. The top layer of the P-type block 5 is a lightly doped P-type semiconductor material, which facilitates the formation of a high barrier region between the gate and the P-type block. This high barrier region can withstand high gate bias voltage, thus significantly improving the device's threshold voltage and reducing gate leakage. Each modulation island is formed by further etching m squares formed after etching the P-type layer. Therefore, the top layer of each modulation island is a heavily doped P-type semiconductor material, which facilitates the formation of ohmic contacts between the island metal and each modulation island. This enhances the effect of improving device conductance and suppressing current collapse in the pn junction diode formed by each modulation island and the barrier layer 4 below.

[0029] Fourth, the process is simple and the yield is high.

[0030] Since each modulation island and P-type block in the device of this invention adopts the same gradient doping structure, the only difference is that different thicknesses can be achieved through etching. Therefore, this invention can ensure that the device has good reliability and output power characteristics, while being compatible with the current manufacturing process of power transistors, without increasing process complexity and achieving high yield. Attached Figure Description

[0031] Figure 1 This is a structural diagram of a traditional gallium nitride-based power transistor;

[0032] Figure 2 This is a top view of the field-effect switching device based on enhanced channel conductivity according to the present invention;

[0033] Figure 3 yes Figure 2 Cross-sectional view along AB;

[0034] Figure 4 yes Figure 2 A cross-sectional view of P-type block 5 in the diagram;

[0035] Figure 5 yes Figure 2 A top view of the modulation island and windows in the image;

[0036] Figure 6 yes Figure 2A cross-sectional view of the inverted L-shaped metal strip in the image;

[0037] Figure 7 This is a schematic diagram of the overall process for fabricating a field-effect switching device based on enhanced channel conductivity according to the present invention.

[0038] Figure 8 This is a current collapse characteristic curve obtained from simulations of traditional devices and the device of this invention. Detailed Implementation

[0039] The embodiments and effects of the present invention will be further described in detail below with reference to the accompanying drawings.

[0040] Reference Figure 2 and Figure 3 The field-effect switching device based on enhanced channel conductivity given in this example includes: substrate 1, transition layer 2, channel layer 3, barrier layer 4, P-type block 5, modulation island array 6, window 7, groove 8, drain 9, source 10, island metal 11, and gate 12, wherein:

[0041] The transition layer 2 is located on the upper part of the substrate 1 and is composed of GaN-based wide bandgap semiconductor material;

[0042] The channel layer 3 is located above the transition layer 2 and is made of GaN material;

[0043] The barrier layer 4 is located above the channel layer 3 and is composed of several layers of the same or different GaN-based wide bandgap semiconductor materials with a thickness of 5nm to 100nm.

[0044] The P-type block 5 is located on the upper part of the barrier layer 4. It has a gradient doping structure, with the doping concentration gradually decreasing from bottom to top.

[0045] The modulation island array 6 is located above the barrier layer 4 and to the left of the P-type block 5. It consists of m parallel modulation islands of the same size and at equal intervals. Each modulation island is also a gradient doping structure, with the doping concentration gradually decreasing from bottom to top, and its thickness is less than that of the P-type block 5.

[0046] The window 7 is composed of square slots located in each modulation island of the modulation island array 6, and there are m square slots in total, with each square slot being the same size.

[0047] The grooves 8 are located in the channel layer 3 or barrier layer 4 on the left side of each of the m modulation islands, and each modulation island has y grooves on its left side.

[0048] The drain 9 and source 10 are located on the left and right sides of the upper part of the barrier layer 4, and are in ohmic contact with the barrier layer 4.

[0049] The island metal 11 is composed of m×y inverted L-shaped metal strips. The lower side of the vertical part of each inverted L-shaped metal strip is located inside the groove 8. The right side of the vertical part is close to the left side of the m modulation islands. The horizontal parts of these inverted L-shaped metal strips are located at the upper part of the m modulation islands or inside the m square grooves.

[0050] The gate 12 is located above the P-type block 5, and its length is less than the length of the P-type block 5.

[0051] Reference Figure 4 The P-type blocks 5 are distributed from bottom to top in layers 1 to n, each layer being composed of P-type semiconductor material with decreasing doping concentration, wherein the doping concentration of the first layer is 10. 18 cm -3 ~10 20 cm -3 The doping concentration of the nth layer is 10. 15 cm -3 ~10 17 cm -3 Each layer has the same thickness, with a total thickness of 8nm to 500nm. The number of layers, n, is determined according to the actual requirements of the device, and n≥2.

[0052] Reference Figure 5 In the modulation island array 6, the distance between the first modulation island and the upper boundary of the device is k1, the distance between the m-th modulation island and the lower boundary of the device is k3, and the spacing between two adjacent modulation islands is k2, where k1, k2, and k3 are all greater than 0 μm; the outer ring length b of these m modulation islands is 0.012 μm to 1000 μm, and the outer ring width c is 0.012 μm to 1000 μm.

[0053] Reference Figure 5 The window 7 includes m square slots of the same size, each with a length of e and a width of f. The geometric center of each square slot coincides with the geometric center of its corresponding modulation island. The upper and lower boundaries of each square slot are parallel to the upper and lower boundaries of its corresponding modulation island, and be ≥ 10 nm and cf ≥ 10 nm.

[0054] Reference Figure 5 The distance between the upper boundary of the first groove 8 and the upper boundary of the corresponding modulation island is S1, the distance between the lower boundary of the y-th groove and the lower boundary of the corresponding modulation island is S2, and the distance between two adjacent grooves on the left side of the same modulation island is t, where S1, S2, and t are all greater than 0 μm; the y grooves on the left side of the same modulation island have the same size and are arranged in parallel with equal spacing, y≥2, that is, the total number of grooves is m×y, and the depth of all grooves is h, where h>0 μm.

[0055] Reference Figure 5 and Figure 6 The width of each inverted L-shaped metal strip in the island metal 11 is w, where 2c≥w>0μm, and c is the outer ring width of each modulation island; for each inverted L-shaped metal strip, the distance d between the left side of its vertical part and the left side of the m modulation islands is 0.05μm~5μm, and the distance r between the right side of its horizontal part and the left side of the m modulation islands, and satisfying b≥r>(be) / 2, where b is the outer ring length of each modulation island, and e is the length of the square groove in the modulation island; for each modulation island, at least one of its corresponding y inverted L-shaped metal strips has a protrusion in its horizontal part to connect the barrier layer 4 in the square groove.

[0056] Reference Figure 7 The present invention provides three embodiments for fabricating a field-effect switching device based on enhanced channel conductivity.

[0057] Example 1: A barrier layer 4 with a thickness of 30 nm was fabricated on a silicon substrate. There are three P-type blocks, with doping concentrations of 1×10⁻⁶ from bottom to top. 18 cm -3 2×10 16 cm -3 4×10 15 cm -3 A field-effect switching device based on channel conductivity enhancement is constructed, with each layer having a thickness of 80nm, one modulation island, two corresponding grooves on the left side of the modulation island, a groove depth h of 30nm, an outer ring length b of 1000μm, an outer ring width c of 1000μm, and a square groove length e and width f of 600μm.

[0058] Step 1. Epitaxially fabricate a transition layer 2 of AlN material on silicon substrate 1, such as... Figure 7 a.

[0059] Using metal-organic chemical vapor deposition (MOCVD), under process conditions of 830°C, 41 Torr, hydrogen flow rate of 4300 sccm, ammonia flow rate of 4300 sccm, and aluminum source flow rate of 21 μmol / min, a 2 μm thick AlN material was epitaxially deposited on a silicon substrate 1 to form a transition layer 2.

[0060] Step 2. Epitaxially grow GaN material on transition layer 2 to form channel layer 3, such as... Figure 7 b.

[0061] Using metal-organic chemical vapor deposition (MOCVD), under process conditions of 980°C, 45 Torr, hydrogen flow rate of 4500 sccm, ammonia flow rate of 4500 sccm, and gallium source flow rate of 120 μmol / min, a 20 μm thick GaN material was epitaxially deposited on the transition layer 2 to form the channel layer 3.

[0062] Step 3. Deposit undoped Al on channel layer 3. 0.2 Ga 0.8 N constructs barrier layer 4, such as Figure 7 c.

[0063] Undoped Al with an aluminum composition of 0.2 was deposited on GaN channel layer 3 using metal-organic chemical vapor deposition (MOCVD) at a temperature of 970 °C, a pressure of 43 Torr, a hydrogen flow rate of 4400 sccm, an ammonia flow rate of 4400 sccm, a gallium source flow rate of 35 μmol / min, and an aluminum source flow rate of 7 μmol / min. 0.2 Ga 0.8 N-barrier layer 4.

[0064] Step 4. Fabricate a P-type layer on barrier layer 4.

[0065] Using magnetron sputtering technology, under the process conditions of sputtering power of 120W, temperature of 310℃, Ar flow rate of 22sccm, and O2 flow rate of 32sccm, a doping concentration of 1×10⁻⁶ was sequentially grown on barrier layer 4. 18 cm -3 2×10 16 cm -3 4×10 15 cm -3 The P-type NiO material was used to form P-type NiO layers with each layer having a thickness of 80 nm and a total thickness of 240 nm, such as... Figure 7 d;

[0066] Step 5. Etch the P-type layer to form P-type block 5, as shown. Figure 7 e.

[0067] A mask was first fabricated on the P-type NiO layer. Using this mask, reactive ion etching was performed on the P-type NiO layer under the process conditions of Cl2 flow rate of 16 sccm, pressure of 12 mTorr, and power of 140 W until the upper surface of the barrier layer 4 was reached, forming a P-type block 5 with a thickness of 240 nm and a square block with a back-shaped shape on the left side of the P-type block 5. The distance between the square block and the upper boundary of the device is k1, and the distance between the square block and the lower boundary of the device is k3, where k1 and k3 are both greater than 0 μm.

[0068] Step 6. Etch the P-type layer again to form the modulation island array 6 and window 7.

[0069] A second mask is fabricated on the barrier layer 4, the P-type block 5, and this square block. This mask is then used to further etch the square block to a depth x of 80 nm, forming a square modulation island with a thickness of 160 nm. This modulation island is the modulation island array 6. The square slots in this modulation island have a length e and a width f of 600 μm, and their geometric centers coincide with the geometric centers of the modulation islands. The upper and lower boundaries of the square slots are parallel to the upper and lower boundaries of the modulation islands. These square slots are the windows 7. Figure 7 f.

[0070] Step 7. Etch the barrier layer 4 to form the groove 8.

[0071] A third mask was fabricated on barrier layer 4, P-type block 5, modulation island array 6, and window 7. Using this mask, reactive ion etching was performed on the left side of modulation island array 6 under the following conditions: Cl2 flow rate of 18 sccm, pressure of 14 mTorr, and power of 120 W. The etching depth h was 30 nm, forming two parallel grooves 8. The distance between the upper boundary of the first groove and the upper boundary of the modulation island is S1, the distance between the lower boundary of the second groove and the lower boundary of the modulation island is S2, and the distance between the two grooves is t. S1, S2, and t are all greater than 0 μm. Figure 7 g.

[0072] Step 8. Fabricate drain 9 and source 10 on barrier layer 4, as follows: Figure 7 h.

[0073] A fourth mask was fabricated on barrier layer 4, P-type block 5, modulation island array 6, window 7, and groove 8. Using this mask, electron beam evaporation was performed on the upper part of barrier layer 4 on both the left and right sides at a vacuum level of less than 1.9 × 10⁻⁶. -3 Pa, power is 520W, evaporation rate is less than Under the specified process conditions, a multilayer metal was deposited, consisting of Ta, Pt, and Au from bottom to top, with thicknesses of 0.122 μm, 0.258 μm, and 0.160 μm, respectively. The material was then rapidly thermally annealed for 30 seconds in an N2 atmosphere at 880 °C to complete the fabrication of the drain 9 and source 10.

[0074] Step 9. Create Island Metal 11, as follows Figure 7 i.

[0075] A fifth mask was fabricated on barrier layer 4, P-type block 5, modulation island array 6, window 7, groove 8, drain 9, and source 10. Using this mask, electron beam evaporation was performed on the upper part of modulation island array 6, the upper part of window 7, and in groove 8 at a vacuum level of 1.7 × 10⁻⁶. -3 Pa, power is 900W, evaporation rate Under the process conditions, a Ti / Al / Au metal combination was deposited with thicknesses of 0.145μm / 0.161 / 0.094μm, and then rapidly annealed in a N2 atmosphere at 840℃ for 40s to form island metal 11.

[0076] The island metal 11 contains 1×2 inverted L-shaped metal strips, each with a width w of 1000μm. The lower side of the vertical portion of these two inverted L-shaped metal strips is located in the groove 8. The distance d between the left side of the vertical portion and the left side of the modulation island is 5μm, and the distance r between the right side of the horizontal portion and the left side of the modulation island is 800μm.

[0077] Step 10. Fabricate gate 12 on P-type block 5, as follows: Figure 7 j.

[0078] A sixth mask was fabricated on barrier layer 4, P-type block 5, modulation island array 6, window 7, drain 9, source 10, and island metal 11. Using this mask, electron beam evaporation technology was employed to achieve a vacuum level of less than 1.8 × 10⁻⁶. -3 Pa, power is 530W, evaporation rate is less than Under the specified process conditions, a metal assembly, consisting of a Ti / Au metal assembly with thicknesses of 0.478 μm and 0.322 μm respectively, is deposited on the upper part of the P-type block 5 to form the gate 12, thus completing the fabrication of the entire device.

[0079] Example 2: A barrier layer 4 with a thickness of 5 nm was fabricated on a sapphire substrate. There are four P-type blocks, with doping concentrations of 1×10⁻⁶ from bottom to top. 19 cm -3 2×10 17 cm -3 1×10 16 cm -3 1×10 15 cm -3 A field-effect switching device based on channel conductivity enhancement is constructed, with each layer having a thickness of 2nm, two modulation islands, three corresponding grooves on the left side of each modulation island, a groove depth h of 12nm, an outer ring length b of 360μm, an outer ring width c of 300μm, and a square groove length e and width f of 300μm and 240μm, respectively.

[0080] Step 1. Epitaxially fabricate a transition layer 2 of GaN material on a sapphire substrate 1, such as... Figure 7 a.

[0081] A transition layer 2 was formed by epitaxially depositing GaN material with a thickness of 20 nm on a sapphire substrate 1 using metal-organic chemical vapor deposition (MOCVD). The process conditions were: temperature 500℃, pressure 45 Torr, hydrogen flow rate 4200 sccm, ammonia flow rate 4200 sccm, and gallium source flow rate 20 μmol / min.

[0082] Step 2. Epitaxially grow GaN material on transition layer 2 to form channel layer 3, such as... Figure 7 b.

[0083] An undoped channel layer 3 was formed by epitaxially depositing 3 μm thick GaN material on the transition layer 2 using metal-organic chemical vapor deposition. The process conditions were: temperature 970℃, pressure 47 Torr, hydrogen flow rate 4600 sccm, ammonia flow rate 4600 sccm, and gallium source flow rate 140 μmol / min.

[0084] Step 3. Deposit Al on undoped channel layer 3 0.3 Ga 0.7 N constructs barrier layer 4, such as Figure 7 c.

[0085] Undoped Al with a thickness of 5 nm and an aluminum composition of 0.3 was deposited on channel layer 3 using metal-organic chemical vapor deposition (MOCVD). 0.3 Ga 0.7 N-barrier layer 4; its process conditions are: temperature 990℃, pressure 44 Torr, hydrogen flow rate 4400 sccm, ammonia flow rate 4400 sccm, gallium source flow rate 35 μmol / min, and aluminum source flow rate 7 μmol / min.

[0086] Step 4. Fabricate a P-type layer on barrier layer 4.

[0087] Using metal-organic chemical vapor deposition, a doping concentration of 1×10⁻⁶ was sequentially epitaxially grown on barrier layer 4. 19 cm -3 2×10 17 cm -3 1×10 16 cm -3 1×10 15 cm -3 The p-type GaN material is used to form p-type GaN layers with each layer having a thickness of 2nm and a total thickness of 8nm, such as... Figure 7 d.

[0088] The epitaxial process conditions were: temperature 950℃, pressure 40 Torr, hydrogen flow rate 4000 sccm, high-purity Mg source as dopant, ammonia flow rate 4000 sccm, and gallium source flow rate 100 μmol / min.

[0089] Step 5. Etch the P-type layer to form P-type block 5, as shown. Figure 7 e.

[0090] A mask was first fabricated on the P-type GaN layer. The P-type GaN layer was then etched using reactive ion etching technology using this mask until the upper surface of the barrier layer 4 was reached, forming a P-type block 5 with a thickness of 8 nm and two identical square blocks of the same size to the left of the P-type block 5. The distance between the first square block and the upper boundary of the device is k1, the distance between the second square block and the lower boundary of the device is k3, and the spacing between the two square blocks is k2. k1, k2, and k3 are all greater than 0 μm.

[0091] The process conditions for reactive ion etching are: Cl2 flow rate of 10 sccm, pressure of 12 mTorr, and power of 80 W.

[0092] Step 6. Etch the P-type layer again to form the modulation island array 6 and window 7.

[0093] A second mask is fabricated on the barrier layer 4, the P-type block 5, and the two rectangular blocks. This mask is then used to further etch the rectangular blocks to a depth x of 4 nm, forming two rectangular modulation islands with a thickness of 4 nm. These two modulation islands constitute a modulation island array 6. The square slots in each modulation island are of the same size, with a length e of 300 μm and a width f of 240 μm. The geometric center of each square slot coincides with the geometric center of the corresponding modulation island, and the upper and lower boundaries of the square slots are parallel to the upper and lower boundaries of the corresponding modulation islands. These two square slots together form a window 7. Figure 7 f.

[0094] The etching process conditions were as follows: Cl2 flow rate of 15 sccm, pressure of 10 mTorr, and power of 100 W.

[0095] Step 7. Etch grooves 8 on barrier layer 4 and channel layer 3.

[0096] A third mask is fabricated on the barrier layer 4, P-type block 5, modulation island array 6, and window 7. Using this mask, the barrier layer 4 and channel layer 3 are etched to the left of the two modulation islands, with an etching depth h of 12 nm. Three equally spaced parallel grooves 8 are formed on the left side of each modulation island. The distance between the upper boundary of the first groove and the upper boundary of the corresponding modulation island is S1, the distance between the lower boundary of the third groove and the lower boundary of the corresponding modulation island is S2, and the distance between two adjacent grooves on the left side of the same modulation island is t. S1, S2, and t are all greater than 0 μm. Figure 7 g.

[0097] The etching process conditions were as follows: Cl2 flow rate of 18 sccm, pressure of 14 mTorr, and power of 120 W.

[0098] Step 8. Fabricate drain 9 and source 10 on barrier layer 4, as follows: Figure 7 h.

[0099] A fourth mask was fabricated on barrier layer 4, P-type block 5, modulation island array 6, window 7 and groove 8. Using this mask, an electron beam evaporation technique was used to deposit a metal combination on the upper part of barrier layer 4 on the left and right sides. The metal combination consists of Al, Ni and Au from bottom to top, with thicknesses of 0.168μm / 0.052μm / 0.040μm, respectively. Rapid thermal annealing was then performed in an N2 atmosphere to complete the fabrication of drain 9 and source 10.

[0100] The process conditions for electron beam evaporation are: vacuum degree less than 1.8 × 10⁻⁶. -3 Pa, power is 500W, evaporation rate is less than

[0101] The process conditions for rapid hot annealing are: temperature 870℃ and time 35s.

[0102] Step 9. Create island metal 11, as follows Figure 7 i.

[0103] A mask is fabricated for the fifth time on the barrier layer 4, P-type block 5, modulation island array 6, window 7, groove 8, drain 9 and source 10. Using this mask, multiple layers of metal are deposited on the upper part of modulation island array 6, the upper part of window 7 and groove 8 using electron beam evaporation technology. The metal combination from bottom to top is Ti, Al, Ni and Au, with thicknesses of 0.003μm / 0.012μm / 0.006μm / 0.009μm, respectively. The island metal 11 is formed by rapid thermal annealing in N2 atmosphere.

[0104] The island metal 11 contains 2×3 inverted L-shaped metal strips, each with a width w of 80μm; the lower side of the vertical portion of these 6 inverted L-shaped metal strips is located in the groove 8, the distance d between the left side of the vertical portion and the left side of the two modulation islands is 1.5μm, and the distance r between the right side of the horizontal portion and the left side of the two modulation islands is 40μm.

[0105] The process conditions used for metal deposition are: vacuum degree less than 1.8 × 10⁻⁶. -3 Pa, power is 200W, evaporation rate is less than

[0106] The process conditions for rapid hot annealing are: temperature 800℃ and time 30s.

[0107] Step 10. Fabricate gate 12 on P-type block 5, as follows: Figure 7 j.

[0108] A sixth mask is fabricated on barrier layer 4, P-type block 5, modulation island array 6, window 7, drain 9, source 10 and island metal 11. Using this mask, a metal combination Ni / Au is deposited on the upper part of P-type block 5 using electron beam evaporation technology. The metals are Ni and Au from bottom to top, with thicknesses of 0.065μm and 0.035μm, respectively, to form gate 12, thus completing the fabrication of the entire device.

[0109] The process conditions for electron beam evaporation are: vacuum degree less than 1.8 × 10⁻⁶. -3 Pa, power is 500W, evaporation rate is less than

[0110] Example 3: A barrier layer 4 with a thickness of 100 nm was fabricated on a silicon carbide substrate. There are five P-type blocks, with doping concentrations of 1×10⁻⁶ from bottom to top. 19 cm -3 6×10 18 cm -3 2×10 17 cm -3 3×10 16 cm -3 1×10 15 cm -3 A field-effect switching device based on channel conductivity enhancement is constructed, with each layer having a thickness of 100nm, five modulation islands, four corresponding grooves on the left side of each modulation island, a groove depth h of 80nm, an outer ring length b of 12nm, an outer ring width c of 12nm, and a square groove length e and width f of 2nm.

[0111] Step A. Epitaxially fabricate a transition layer 2 of AlN material on a silicon carbide substrate 1, such as... Figure 7 a.

[0112] The temperature was set to 1050℃, the pressure to 46 Torr, the hydrogen flow rate to 4600 sccm, the ammonia flow rate to 4600 sccm, and the aluminum source flow rate to 6 μmol / min. Metal-organic chemical vapor deposition was used to epitaxially deposit AlN material with a thickness of 170 nm on silicon carbide substrate 1 to form transition layer 2.

[0113] Step B. Epitaxially grow GaN material on transition layer 2 to form channel layer 3, as shown below. Figure 7 b.

[0114] The temperature was set to 1020℃, the pressure to 48 Torr, the hydrogen flow rate to 4800 sccm, the ammonia flow rate to 4800 sccm, and the gallium source flow rate to 100 μmol / min. A GaN material with a thickness of 39.83 μm was epitaxially deposited on the transition layer 2 using metal-organic chemical vapor deposition technology to form the channel layer 3.

[0115] Step C. Deposit undoped Al on channel layer 3 0.1 Ga 0.9 N constructs barrier layer 4, such as Figure 7 c.

[0116] The temperature was set at 970℃, the pressure at 46 Torr, the hydrogen flow rate at 4500 sccm, the ammonia flow rate at 4500 sccm, the gallium source flow rate at 37 μmol / min, and the aluminum source flow rate at 7 μmol / min. Undoped Al with an aluminum composition of 0.1 was deposited on channel layer 3 with a thickness of 100 nm using metal-organic chemical vapor deposition (MOCVD). 0.1 Ga 0.9 N-barrier layer 4.

[0117] Step D. Fabricate a P-type layer on barrier layer 4, such as... Figure 7 d.

[0118] The process conditions were set as follows: the target material was copper with a purity of 99.999%; the sputtering gas was high-purity argon; and high-purity oxygen of the same purity was used as the reaction gas. The vacuum degree of the reaction chamber before sputtering was 2.0 × 10⁻⁶. -4 Pa, during sputtering, the Ar gas flow rate was maintained at 20 sccm, the O2 flow rate at 10 sccm, the gas pressure in the deposition chamber was 0.5 Pa, the RF power was 35 W, and the substrate temperature was 200 °C.

[0119] Using magnetron sputtering, a doping concentration of 1×10⁻⁶ was sequentially epitaxially grown on barrier layer 4. 19 cm -3 6×10 18 cm -3 2×10 17 cm -3 3×1016 cm -3 1×10 15 cm -3 The CuO material was used to form a P-type CuO layer with each layer having a thickness of 100 nm and a total thickness of 500 nm.

[0120] Step E. Etch the P-type layer to form P-type block 5, as shown. Figure 7 e.

[0121] The etching process conditions were set as follows: Cl2 flow rate of 15 sccm, pressure of 11 mTorr, and power of 120 W. A mask was fabricated on the P-type CuO layer for the first time. The P-type CuO layer was etched using reactive ion etching technology using this mask until the upper surface of the barrier layer 4 was reached, forming a P-type block 5 with a thickness of 500 nm and five identical square blocks of the same size to the left of the P-type block 5. The distance between the first square block and the upper boundary of the device is k1, the distance between the fifth square block and the lower boundary of the device is k3, and the spacing between any two adjacent square blocks is k2. k1, k2, and k3 are all greater than 0 μm.

[0122] Step F. Etch the P-type layer again to form the modulation island array 6 and window 7, as shown. Figure 7 f.

[0123] A second mask is fabricated on the barrier layer 4, the P-type block 5, and the five square blocks. The square blocks are then further etched using the mask to a depth of 200 nm, forming five square modulation islands with a thickness of 300 nm each. These five modulation islands constitute a modulation island array 6. The square slots in each modulation island are the same size, with a length e and a width f of 2 nm each. The geometric center of each square slot coincides with the geometric center of the corresponding modulation island. The upper and lower boundaries of the square slots are parallel to the upper and lower boundaries of the corresponding modulation islands. These five square slots together form a window 7.

[0124] Step G. Etch the barrier layer 4 to form the groove 8.

[0125] Under process conditions of 18 sccm Cl2 flow rate, 13 mTorr pressure, and 130 W power, a third mask was fabricated on barrier layer 4, P-type block 5, modulation island array 6, and window 7. Using this mask, reactive ion etching (RIE) was employed to etch barrier layer 4 to the left side of the five modulation islands in modulation island array 6, with an etching depth h of 80 nm. This resulted in four equally spaced parallel grooves 8 on the left side of each modulation island. The distance between the upper boundary of the first groove and the upper boundary of the corresponding modulation island is S1; the distance between the lower boundary of the fourth groove and the lower boundary of the corresponding modulation island is S2; and the distance between two adjacent grooves on the left side of the same modulation island is t. All of S1, S2, and t are greater than 0 μm. Figure 7 g.

[0126] Step H. Fabricate drain 9 and source 10 on barrier layer 4, as follows: Figure 7 h.

[0127] Set the vacuum level to less than 1.8 × 10⁻⁶. -3 Pa, power is 400W, evaporation rate is less than Under the specified process conditions, a mask was fabricated for the fourth time on the barrier layer 4, P-type block 5, modulation island array 6, window 7, and groove 8. Using this mask, multiple layers of metal were deposited on the upper part of the barrier layer 4 on the left and right sides using electron beam evaporation technology. The multiple layers of metal, from bottom to top, are Ta / Ni / Au, with thicknesses of 0.015μm / 0.179μm / 0.062μm, respectively. The material was then rapidly thermally annealed for 35s in an N2 atmosphere at 870℃ to complete the fabrication of the drain 9 and source 10.

[0128] Step I. Create island metal 11, as follows Figure 7 i.

[0129] Set the vacuum level to 1.7 × 10⁻⁶. -3 Pa, power is 530W, evaporation rate Under the specified process conditions, a mask was fabricated for the fifth time on the barrier layer 4, P-type block 5, modulation island array 6, window 7, groove 8, drain 9, and source 10. Using this mask, Ta / Ni / Au multilayer metals were deposited on the upper part of the modulation island array 6, the upper part of the window 7, and the groove 8 using electron beam evaporation technology. The thicknesses were 0.206μm / 0.258μm / 0.371μm, respectively. The island metal 11 was formed by rapid thermal annealing in a N2 atmosphere at 860℃ for 45s.

[0130] The island metal 11 contains 5×4 inverted L-shaped metal strips, each with a width w of 2nm. The lower side of the vertical portion of these 20 inverted L-shaped metal strips is located in the groove 8. The distance d between the left side of the vertical portion and the left side of the five modulation islands is 50nm, and the distance r between the right side of the horizontal portion and the left side of the five modulation islands is 8nm.

[0131] Step J. Fabricate gate 12 on P-type block 5, as follows: Figure 7 j.

[0132] With the sputtering pressure set at approximately 0.1 Pa, the Ar flow rate at 8 sccm, the substrate temperature fixed at 200℃, and the target RF power at 150 W, a sixth mask was fabricated on the barrier layer 4, P-type block 5, modulation island array 6, window 7, drain 9, source 10, and island metal 11. Using this mask, metal combinations Ta / Au with thicknesses of 0.023 μm and 0.27 μm were deposited on the upper part of the P-type block 5 using sputtering technology to form the gate 12; thus completing the fabrication of the entire device.

[0133] The effects of this invention can be further illustrated by the following simulation results.

[0134] Simulation parameters: The parameters of the barrier layer and P-type block in a conventional gallium nitride-based power transistor are set to be the same as those of the device in Embodiment 2 of this invention. Current collapse characteristics simulations are performed on both the conventional device and the device in Embodiment 2 of this invention. The results are as follows: Figure 8 ,in:

[0135] Figure 8 (a) shows the simulation results of a traditional gallium nitride-based power transistor. Figure 8 (b) shows the simulation results of Example 2, from Figure 8 It can be seen that traditional devices suffer from severe current collapse, while the device of the present invention can effectively suppress the current collapse effect, indicating that the current collapse suppression effect of the device of the present invention is significantly better than that of traditional devices.

[0136] In the above three embodiments, the fabrication of the P-type block 5 and the modulation island array 6 can also be achieved by first etching to form the height difference between the P-type block 5 and the modulation island array 6, and then further etching the P-type layer to form the P-type block 5 and the modulation island array 6.

[0137] The above description is merely three specific embodiments of the present invention and does not constitute a limitation on the present invention. Obviously, those skilled in the art, after understanding the content and principles of the present invention, can make various modifications and changes in form and detail according to the method of the present invention without departing from the principles and scope of the present invention. However, these modifications and changes based on the present invention are still within the protection scope of the claims of the present invention.

Claims

1. A field effect switching device based on channel conductance enhancement, comprising, from bottom to top: The substrate (1), the transition layer (2), the channel layer (3) and the barrier layer (4), the upper part of the barrier layer (4) is provided with a P-type block (5), the upper part of the P-type block (5) is deposited with a gate (12), the upper left and right edges of the barrier layer (4) are respectively provided with a drain (9) and a source (10), characterized in that: further comprising a modulation island array (6); The P-type block (5) is a gradual doping structure, which is distributed from the first layer (51) to the nth layer (5n) from bottom to top, each layer is composed of P-type semiconductor material with decreasing doping concentration, and the thickness of each layer is the same; The modulation island array (6) is composed of m parallelly arranged back-shaped modulation islands with the same size and equal interval, m ≥ 1, each modulation island is a gradual doping structure, and the doping concentration gradually decreases from bottom to top, and the thickness is less than that of the P-type block (5); square grooves are arranged in all the modulation islands, and the square grooves form a window (7); The channel layer (3) or the barrier layer (4) is internally provided with y grooves (8) on the left side of each modulation island, the y grooves are the same in size and are arranged in parallel with equal interval, y ≥ 2, that is, the total number of the grooves (8) is m×y; a reverse L-shaped metal strip is arranged in each groove, and the vertical part of each reverse L-shaped metal strip is located inside the groove (8) on the lower side, and the vertical part is closely arranged on the left side of the m modulation islands, and the horizontal part of the reverse L-shaped metal strip is located on the upper part of the m modulation islands or in the m square grooves; for each modulation island, at least one metal strip of the y reverse L-shaped metal strips corresponding to the modulation island has a protrusion on the horizontal part to connect the barrier layer (4) in the square groove, and the m×y metal strips form an island metal (11).

2. The device of claim 1, wherein, The thickness of the P-type block (5) is 8 nm ~ 500 nm, and the doping concentration gradually decreases from bottom to top, wherein the doping concentration of the first layer (51) is 10 18 cm -3 ~ 10 20 cm -3 , the doping concentration of the nth layer (5n) is 10 15 cm -3 ~ 10 18 cm -3 , and the thickness of each layer is the same, wherein the number of layers n is determined according to the actual use requirement of the device, and n ≥ 3.

3. The device of claim 1, wherein: The position parameters of the m modulation islands are as follows: The distance between the first modulation island and the upper boundary of the device is k1, the distance between the mth modulation island and the lower boundary of the device is k3, and the distance between adjacent two modulation islands is k2, wherein k1, k2 and k3 are all greater than 0 μm; The outer ring length b of the m modulation islands is 0.012 μm ~1000 μm, the outer ring width c is 0.012 μm ~1000 μm, the modulation islands and the P-type block (5) are made of the same material, but the thickness g of the modulation islands is less than that of the P-type block (5); Each modulation island is provided with a square groove, the square grooves are the same in size, the length of the square groove is e, the width of the square groove is f, and the geometric center of each square groove coincides with the geometric center of the corresponding modulation island, the upper boundary and the lower boundary of each square groove are parallel to the upper boundary and the lower boundary of the corresponding modulation island, and the m square grooves jointly form a window (7), and b-e ≥10 nm, c-f ≥10 nm.

4. The device of claim 1, wherein The total number of the grooves (8) is m×y, and the depth of each groove is h, where h > 0 μm; each of the channel layers (3) or the barrier layers (4) on the left side of each modulation island is provided with y grooves arranged in parallel at equal intervals, the distance between the upper boundary of the first groove and the upper boundary of the corresponding modulation island is S1, the distance between the lower boundary of the yth groove and the lower boundary of the corresponding modulation island is S2, and the distance between two adjacent grooves on the left side of the same modulation island is t, where S1, S2 and t are all greater than 0 μm.

5. The device of claim 1, wherein, The position parameters of the m×y inverted L-shaped metal strips are as follows: The width of each inverted L-shaped metal strip is w, where 2c > w > 0 μm, and c is the outer ring width of each modulation island; The distance d between the vertical part of each inverted L-shaped metal strip and the left side of the m modulation islands is 0.05 μm ~ 5 μm, the distance r between the horizontal part of each inverted L-shaped metal strip and the left side of the m modulation islands is 0.05 μm ~ 5 μm, and b ≥ r > (b - e) / 2, where b is the outer ring length of each modulation island, and e is the length of each square groove in the modulation island.

6. The device according to claim 1, characterized in that: The drain (9) and the source (10) are both in ohmic contact with the barrier layer (4); The island metal (11) is arranged in the groove and is in contact with the surface of the barrier layer, and after annealing treatment, an alloy is formed between the island metal (11) and the semiconductor.

7. A method of fabricating the switching device of claim 1, wherein The method comprises the following steps: A) epitaxially growing a GaN-based wide-bandgap semiconductor material on the substrate (1) to form a transition layer (2); B) epitaxially growing a GaN material on the transition layer (2) to form a channel layer (3); C) epitaxially growing a GaN-based wide-bandgap semiconductor material on the channel layer (3) to form a barrier layer (4) with a thickness of a; D) epitaxially growing a P-type semiconductor material on the barrier layer (4) to form n P-type layers with the same thickness and gradually decreasing doping concentration from bottom to top; E) first making a mask on the P-type layer, and etching the P-type layer using the mask until the upper surface of the barrier layer (4) is reached, thereby forming a P-type block (5) with a thickness of 5-500 nm and m H-shaped blocks on the left side of the P-type block (5) which are arranged in parallel at equal intervals and have the same size and thickness as the P-type block (5), where m ≥ 1; F) secondly making a mask on the barrier layer (4), the P-type block (5) and the m H-shaped blocks, and further etching the m H-shaped blocks using the mask, where the etching depth x is less than the thickness of the P-type block (5), thereby forming m H-shaped modulation islands with a thickness of g, which constitute a modulation island array (6), and the square grooves in each modulation island have the same size, and these square grooves constitute windows (7); G) thirdly making a mask on the barrier layer (4), the P-type block (5), the modulation island array (6) and the windows (7), and etching the barrier layer (4) and the channel layer (3) on the left side of each modulation island in the modulation island array (6) using the mask, where the etching depth is h, and y grooves arranged in parallel at equal intervals are formed on the left side of each modulation island, i.e. the total number of the grooves (8) is m×y. H) The fourth time, a mask is made on the barrier layer (4), P-type block (5), modulation island array (6), window (7) and groove (8), using the mask to deposit metal on the left and right sides of the barrier layer (4) upper part, and rapid thermal annealing is performed in N2 atmosphere, to complete the fabrication of the drain (9) and source (10); I) The fifth time, a mask is made on the barrier layer (4), P-type block (5), modulation island array (6), window (7), groove (8), drain (9) and source (10), using the mask to deposit metal on the modulation island array (6) upper part, window (7) inside and groove (8), and rapid thermal annealing is performed in N2 atmosphere, to form island metal (11); J) The sixth time, a mask is made on the barrier layer (4), P-type block (5), modulation island array (6), window (7), drain (9), source (10) and island metal (11), using the mask to deposit metal on the P-type block (5) upper part, to form the gate (12), to complete the fabrication of the entire device.

8. The method of claim 7, wherein: The epitaxial technology used in steps A), B), C), D) includes: metal organic chemical vapor deposition technology, molecular beam epitaxy technology, plasma enhanced atomic layer deposition technology, magnetron sputtering.

9. The method of claim 7, wherein: The metal deposition process used in steps H), I), J) includes: electron beam evaporation process, sputtering process.

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