Array substrate and preparation method thereof

Abstract

The present application provides an array substrate and a method for manufacturing the same. The array substrate comprises: a substrate; a buffer layer located on one side of the substrate; the buffer layer comprising a first surface, a first inclined surface, and a second inclined surface, the first inclined surface and the second inclined surface respectively connected to two ends of the first surface, and the first inclined surface and the second inclined surface respectively inclined relative to the first surface; and an active layer located on the buffer layer; the active layer comprising a source region, a drain region, and a channel region located between the source region and the drain region; the channel region, the source region, and the drain region respectively located on the first surface, the first inclined surface, and the second inclined surface; a gate located on one side of the active layer and opposite to the channel region; and a source electrode and a drain electrode located on one side of the active layer and electrically connected to the source region and the drain region, respectively. The present application utilizes a three-dimensional TFT structure design to reduce the footprint of the TFT while maintaining the physical dimensions of the TFT, thereby reducing the overall size of the TFT.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to an array substrate and a method for preparing the same. Background Art

[0002] With the development of display technology, the requirements for the display effect of display devices are getting higher and higher. In order to achieve the ultimate display effect, the array substrate needs to have characteristics such as high pixel density, high aperture ratio, and narrow frame.

[0003] In order to achieve the above technical effects, it is necessary to reduce the space occupied by thin film transistors (TFTs) and reduce the display size of TFT devices. However, directly reducing the size of TFT devices proportionally will degrade the performance of TFT devices. Summary of the Invention

[0004] In view of this, the present application provides an array substrate and a preparation method thereof, which reduces the footprint of the TFT while ensuring that the physical size of the TFT remains unchanged through a three-dimensional TFT structure design, thereby reducing the overall size of the TFT.

[0005] The present application provides an array substrate, comprising:

[0006] substrate;

[0007] a buffer layer located on one side of the substrate; the buffer layer includes a first surface, a first inclined surface, and a second inclined surface, the first inclined surface and the second inclined surface are respectively connected to two ends of the first surface, and the first inclined surface and the second inclined surface are respectively inclined relative to the first surface; and

[0008] an active layer located on the buffer layer; the active layer comprising a source region, a drain region, and a channel region located between the source region and the drain region; the channel region, the source region, and the drain region are located on the first surface, the first inclined surface, and the second inclined surface, respectively;

[0009] a gate, located on one side of the active layer and opposite to the channel region;

[0010] The source and the drain are located on one side of the active layer and are electrically connected to the source region and the drain region respectively.

[0011] In an optional embodiment of the present application, the first inclined surface and the second inclined surface are located on the same side of the first surface, a groove is formed on the buffer layer, the first surface is the bottom surface of the groove, and the first inclined surface and the second inclined surface are the two side walls of the groove respectively.

[0012] In an optional embodiment of the present application, the first inclined surface and the second inclined surface are located on the same side of the first surface, and a boss is formed on the buffer layer. The first surface is the top surface of the boss, and the first inclined surface and the second inclined surface are respectively two inclined surfaces of the boss.

[0013] In an optional embodiment of the present application, the first inclined surface and the second inclined surface are located on different sides of the first surface.

[0014] In an optional embodiment of the present application, the slope angle between the first inclined surface and the first surface is α1, the slope angle between the second inclined surface and the first surface is α2, and the difference between the area of ​​the active layer and the projected area of ​​the active layer on the substrate is L1*W1*(1-cosα1)

[0015] +L2*W2*(1-cosα2), where L1 is the slope length of the first inclined surface, L2 is the slope length of the second inclined surface, W1 is the width of the first inclined surface, and W2 is the width of the second inclined surface.

[0016] In an optional embodiment of the present application, the slope angle α1 is equal to the slope angle α2.

[0017] In an optional embodiment of the present application, the slope angle α1 is not equal to the slope angle α2.

[0018] In an optional embodiment of the present application, the source region includes a first heavily doped region and a first lightly doped region located between the first heavily doped region and the channel region, and the drain region includes a second heavily doped region and a second lightly doped region located between the second heavily doped region and the channel region; the source is electrically connected to the first heavily doped region, and the drain is electrically connected to the second heavily doped region.

[0019] In an optional embodiment of the present application, the array substrate further includes:

[0020] a light-shielding layer, the light-shielding layer being located between the substrate and the buffer layer, wherein a projection of the light-shielding layer on the substrate overlaps with a projection of the first lightly doped region, the channel region, and the second lightly doped region on the substrate;

[0021] a gate insulating layer, the gate insulating layer being located between the active layer and the gate;

[0022] A dielectric layer is located between the gate and the source and drain; the dielectric layer has a first region parallel to the first inclined surface, a second region parallel to the second inclined surface, and a third region parallel to the first surface, the source is located on the first region, and the drain is located on the second region

[0023] The present application provides a method for preparing an array substrate, comprising the following steps:

[0024] providing a substrate;

[0025] forming a buffer layer on the substrate, and forming a pattern on the buffer layer, wherein the pattern has a first surface, a first inclined surface, and a second inclined surface, wherein the first inclined surface and the second inclined surface are respectively connected to two ends of the first surface, and the first inclined surface and the second inclined surface are respectively inclined relative to the first surface;

[0026] forming an active layer on the buffer layer, the active layer comprising a source region, a drain region, and a channel region located between the source region and the drain region, wherein the channel region, the source region, and the drain region are respectively located on the first surface, the first inclined surface, and the second inclined surface;

[0027] forming a gate insulating layer on the active layer;

[0028] forming a gate on the gate insulating layer, wherein the gate is opposite to the channel region;

[0029] forming a dielectric layer on the gate;

[0030] forming a first via hole and a second via hole on the dielectric layer and the gate insulating layer, wherein the first via hole and the second via hole are respectively located on two sides of the gate;

[0031] A source electrode and a drain electrode are formed on the dielectric layer, wherein the source electrode is electrically connected to the source region through the first via hole, and the drain electrode is electrically connected to the drain region through the second via hole.

[0032] The present application provides an array substrate and a method for preparing the same. The present application forms an inclined surface with a certain slope on the buffer layer by patterning the buffer layer of the array substrate, and positions at least a portion of the active layer on the inclined surface. This can reduce the footprint of the active layer (i.e., the projected area of ​​the active layer on the substrate) while ensuring that the physical length of the active layer remains unchanged, thereby reducing the overall size of the TFT, thereby facilitating the production of an array substrate with high pixel density, high aperture ratio, and narrow bezel. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0034] Figure 1The figure is a structural diagram of an array substrate in the prior art.

[0035] Figure 2 A schematic structural diagram of an array substrate provided in one embodiment of the present application.

[0036] Figure 3 A schematic structural diagram of an array substrate provided in another embodiment of the present application.

[0037] Figure 4 A schematic structural diagram of an array substrate provided in yet another embodiment of the present application.

[0038] Figure 5 A schematic diagram of a process for preparing an array substrate provided in this application. DETAILED DESCRIPTION

[0039] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the embodiments described are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative efforts are within the scope of protection of this application.

[0040] In the description of this application, it should be understood that the orientation or positional relationship indicated by the terms "upper" and "lower" is based on the orientation or positional relationship shown in the accompanying drawings, and is only for the convenience of describing this application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on this application. In addition, the terms "first" and "second" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the said features. In the description of this application, the meaning of "multiple" is two or more, unless otherwise clearly and specifically defined.

[0041] The present application may repeat reference numerals and / or reference letters in different embodiments. This repetition is for the purpose of simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or settings discussed.

[0042] The array substrate and the manufacturing method thereof provided in the present application will be described in detail below with reference to specific embodiments and drawings.

[0043] To achieve the ultimate display effect, the array substrate must have high pixel density, high aperture ratio, and narrow bezels. Existing technologies typically reduce the display size of TFT devices by reducing the space occupied by the TFTs. However, directly scaling down the TFT device size can degrade its performance.

[0044] like Figure 1 As shown, it is a schematic diagram of an array substrate structure commonly used in the prior art. The entire active layer 400 of the array substrate 10 is on the same plane, occupying a large area, so that the corresponding TFT device size is large, affecting the display effect of the panel.

[0045] See also Figure 2 、 Figure 3 and Figure 4 , is a schematic diagram of an array substrate structure provided by the present application. The present application forms an inclined surface with a certain slope on the buffer layer 300 by patterning the buffer layer 300, and locates at least a portion of the active layer 400 on the inclined surface. This can reduce the footprint of the active layer 400 (i.e., the projected area of ​​the active layer 400 on the substrate 100) while ensuring that the physical length of the active layer 400 remains unchanged, thereby reducing the overall size of the TFT, which is conducive to the production of an array substrate with high pixel density, high aperture ratio, and narrow frame.

[0046] See also Figure 2 , is a specific embodiment of an array substrate provided in this application.

[0047] The array substrate 10 includes a base 100 , a light shielding layer 200 , a buffer layer 300 , an active layer 400 , a gate insulating layer 500 , a gate 600 , a dielectric layer 700 , a planarization layer 800 , a source electrode 810 , and a drain electrode 820 .

[0048] The substrate 100 may be, but is not limited to, a glass substrate, a resin substrate, or the like.

[0049] The light shielding layer 200 is located on one side of the substrate 100 and is used to shield part of the incident light. The material of the light shielding layer 200 can be at least one of molybdenum (Mo), aluminum (Al), or a molybdenum-aluminum alloy.

[0050] The buffer layer 300 is located on the side of the light shielding layer 200 away from the substrate 100 and covers the light shielding layer 200. The material of the buffer layer 300 can be SiO x and SiN x The buffer layer 300 plays a role in buffering and isolating alkali metal ions in the glass substrate.

[0051] Specifically, a groove-shaped pattern is formed on the side of the buffer layer 300 away from the substrate 100, and the groove has a first surface 301 (i.e., the bottom surface of the groove), a first inclined surface 302 and a second inclined surface 303 (i.e., the two side walls of the groove), the first inclined surface 302 and the second inclined surface 303 are respectively connected to the two ends of the first surface 301, the first inclined surface 302 and the second inclined surface 303 are respectively inclined relative to the first surface 301, and the first surface 301 is parallel to the substrate 100.

[0052] Specifically, such as Figure 2 As shown, the slope angle (taper angle) α1 between the first inclined surface 302 and the first surface 301 is in the range of 0° < α1 < 90°, preferably 45° ≤ α1 ≤ 60°, to reduce process difficulty and balance process risks; the slope angle (taper angle) α2 between the second inclined surface 303 and the first surface 301 is in the range of 0° < α2 < 90°, preferably 45° ≤ α1 ≤ 60°, to reduce process difficulty and balance process risks. The taper angle α1 and the taper angle α2 can be equal or unequal, and can be set according to actual process requirements.

[0053] The buffer layer 300 is selected to form an inclined surface pattern because it is a film layer independent of the TFT structure and only serves to buffer and isolate the alkali metal ions in the glass substrate. Changes to the buffer layer 300 do not play a decisive role in the electrical properties of the TFT. During the design process, the projected area of ​​the TFT can be adjusted by adjusting the thickness of the buffer layer 300 and the taper angle of the inclined surface without affecting the electrical function of the TFT.

[0054] The active layer 400 is located on a side of the buffer layer 300 away from the substrate 100. The active layer 400 includes a source region 410, a drain region 420, and a channel region 430 located between the source region 410 and the drain region 420. The channel region 430, the source region 410, and the drain region 420 are respectively located on the first surface 301, the first inclined surface 302, and the second inclined surface 303. The material of the active layer 400 can be, but is not limited to, amorphous silicon (a-Si).

[0055] Specifically, the source region 410 and the drain region 420 are both ion-doped through a doping process. The doped ions may be, but are not limited to, phosphorus ions. Ion doping of the active layer is performed to change its conductive properties.

[0056] Specifically, the source region 410 includes a first heavily doped region 411 and a first lightly doped region 412 located between the first heavily doped region 411 and the channel region 430. The drain region 420 includes a second heavily doped region 421 and a second lightly doped region 422 located between the second heavily doped region 421 and the channel region 430. The first heavily doped region 411 and the second heavily doped region 421 are highly N-type doped, which facilitates ohmic contact in the TFT. The first lightly doped region 412 and the second lightly doped region 422 are intended to reduce the electric field strength at the source-drain junction and improve device stability.

[0057] The difference between the area of ​​the active layer 400 and the projected area of ​​the active layer 400 on the substrate 100 is L1*W1*(1-cosα1)+L2*W2*(1-cosα2), where L1 is the slope length of the first inclined surface, L2 is the slope length of the second inclined surface, W1 is the width of the first inclined surface, and W2 is the width of the second inclined surface. During the design process, the projected area of ​​the active layer 400 on the substrate 100 can be controlled by adjusting the taper angle α1 and the taper angle α2, thereby reducing the active layer's footprint.

[0058] The projection of the light-shielding layer 200 on the substrate 100 overlaps with the projections of the first lightly doped region 412, the channel region 430 and the second lightly doped region 422 on the substrate 100, so that the light-shielding layer 200 blocks the backlight (the light source below the TFT) from entering the TFT to generate photogenerated leakage current.

[0059] The gate insulating layer 500 is located on a side of the active layer 400 away from the buffer layer 300 and covers the active layer 400 to insulate the gate 600 from the active layer 400. The material of the gate insulating layer 500 may be, but is not limited to, SiO x .

[0060] The gate 600 is located on a side of the gate insulating layer 500 away from the active layer 400, and the projection of the gate 600 on the substrate 100 coincides with the projection of the channel region 430 on the substrate 100, so that the gate 600 serves as a shield to facilitate ion doping of the source region 410 on the first inclined surface 302 and the drain region 420 on the second inclined surface 303.

[0061] The dielectric layer 700 is located on the side of the gate 600 away from the gate insulating layer 500 and covers the gate 600 to insulate the gate 600 from the source and drain. The dielectric layer 700 can be made of SiO x and SiN xThe dielectric layer 700 includes a first via hole 701 and a second via hole 702, the first via hole 701 and the second via hole 702 being located on either side of the gate 600. The first via hole 701 penetrates the gate insulating layer 500 to expose one side of the first heavily doped region 411; the second via hole 702 penetrates the gate insulating layer 500 to expose one side of the second heavily doped region 421.

[0062] The source electrode 810 is located on a side of the dielectric layer 700 away from the gate 600 and is electrically connected to one side of the first heavily doped region 411 through the first via 701. The material of the source electrode 810 can be, but is not limited to, a Ti / Al / Ti / or Mo / Al / Mo metal stack.

[0063] The drain electrode 820 is located on a side of the dielectric layer 700 away from the gate 600 and is electrically connected to a side of the second heavily doped region 421 through the second via 702. The material of the drain electrode 820 may be, but is not limited to, a Ti / Al / Ti / or Mo / Al / Mo metal stack.

[0064] Specifically, the dielectric layer 700 has a first region 710 parallel to the first inclined surface 302, a second region 720 parallel to the second inclined surface 303, and a third region 730 parallel to the first surface 301. The source electrode 810 is located on the first region 710, and the drain electrode 820 is located on the second region 720. The source electrode 810 and the drain electrode 820 are located on the inclined first region 710 and the second region 720, respectively, which can reduce the thickness of the TFT.

[0065] The planarization layer 800 is located on a side of the dielectric layer 700 away from the gate 600 and covers the source 810 and the drain 820 to planarize the surface of the pattern on the array substrate 10. The material of the planarization layer 800 can be, but is not limited to, an organic photoresist material.

[0066] In some other embodiments, the array substrate 10 further includes a BITO (Back side Indium Tin Oxides) layer 900 , a passivation layer 1000 and a TITO (Top-Indium Tin Oxides) layer 1100 .

[0067] Specifically, the planar layer 800 includes a first through hole, and the first through hole exposes one side of the drain electrode 820 .

[0068] The BITO layer 900 is located on a side of the planar layer 800 away from the dielectric layer 700. The material of the BITO layer 900 is indium tin oxide (ITO). The BITO layer includes a second through hole corresponding to the first through hole.

[0069] The passivation layer 1000 is located on the side of the BITO layer 900 away from the flat layer 800. The material of the passivation layer 1000 can be SiO x and SiN x The passivation layer 1000 includes a third through hole corresponding to the second through hole.

[0070] The TITO layer 1100 is located on a side of the passivation layer 1000 away from the BITO layer 900 . The TITO layer 1100 is electrically connected to the drain electrode 820 through the third through hole, the second through hole, and the first through hole to form a pixel electrode.

[0071] See also Figure 3 , is another specific embodiment of an array substrate provided in this application.

[0072] The structure of the array substrate 10 provided in another specific embodiment of the present application is substantially the same as the structure of the array substrate 10 described in the specific embodiment of the above array substrate, with the only difference being that:

[0073] A boss-shaped pattern is formed on the side of the buffer layer 300 away from the substrate 100, and the boss has a first surface 301 (i.e., the top surface of the boss), a first inclined surface 302 and a second inclined surface 303 (i.e., the two inclined surfaces of the boss), the first inclined surface 302 and the second inclined surface 303 are respectively connected to the two ends of the first surface 301, the first inclined surface 302 and the second inclined surface 303 are respectively inclined relative to the first surface 301, and the first surface 301 is parallel to the substrate 100.

[0074] See also Figure 4 , is another specific embodiment of an array substrate provided in this application.

[0075] The structure of the array substrate 10 provided in another specific embodiment of the present application is substantially the same as the structure of the array substrate 10 described in the specific embodiment of the above array substrate, with the only difference being that:

[0076] The buffer layer 300 is formed on a side away from the substrate 100 with a pattern consisting of a first surface 301, a first inclined surface 302, and a second inclined surface 303. The first inclined surface 302 and the second inclined surface 303 are respectively connected to the two ends of the first surface 301. The first inclined surface 302 and the second inclined surface 303 are respectively inclined relative to the first surface 301. The first surface 301 is parallel to the substrate 100. The first inclined surface 302 and the second inclined surface 303 are located on different sides of the first surface 301. Specifically, Figure 4 As shown, the first inclined surface 302 is located on a side of the first surface 301 away from the substrate 100 , and the second inclined surface 303 is located on a side of the first surface 301 close to the substrate 100 .

[0077] In the above-described embodiment of the present application, a first surface, a first inclined surface, and a second inclined surface are formed on the buffer layer by patterning the buffer layer. The first inclined surface and the second inclined surface are respectively connected to two ends of the first surface. The first surface is parallel to the substrate. The first inclined surface and the second inclined surface are respectively inclined relative to the first surface. The taper angle α1 of the first inclined surface and the taper angle α2 of the second inclined surface are adjustable. The channel region, the source region, and the drain region are respectively located on the first surface, the first inclined surface, and the second inclined surface. By controlling the angles α1 and α2 (the angles α1 and α2 are easily controlled by etching process parameters) and adjusting the slopes of the first and second inclined surfaces, the active layer footprint (i.e., the projected area of ​​the active layer on the substrate) can be reduced while maintaining the physical length of the active layer unchanged, thereby reducing the TFT footprint, thereby facilitating the manufacture of an array substrate with a high pixel density, a high aperture ratio, and a narrow bezel. Furthermore, the channel region is located on the first surface, i.e., the channel region remains on a plane, which helps maintain device stability.

[0078] See also Figure 5 , the present application also provides a method for preparing an array substrate, comprising the steps of:

[0079] Providing a substrate 100;

[0080] A buffer layer 300 is formed on the substrate 100, and a pattern is formed on the buffer layer 300, wherein the pattern has a first surface 301, a first inclined surface 302, and a second inclined surface 303, wherein the first inclined surface 302 and the second inclined surface 303 are respectively connected to two ends of the first surface 301, and the first inclined surface 302 and the second inclined surface 303 are respectively inclined relative to the first surface 301;

[0081] An active layer 400 is formed on the buffer layer 300. The active layer 400 includes a source region 410, a drain region 420, and a channel region 430 located between the source region 410 and the drain region 420. The channel region 430, the source region 410, and the drain region 420 are respectively located on the first surface 301, the first inclined surface 302, and the second inclined surface 303.

[0082] forming a gate insulating layer 500 on the active layer 400;

[0083] forming a gate 600 on the gate insulating layer 500 , wherein the gate 600 is opposite to the channel region 430 ;

[0084] forming a dielectric layer 700 on the gate 600;

[0085] A first via hole 701 and a second via hole 702 are formed on the dielectric layer 700 and the gate insulating layer 500 , wherein the first via hole 701 and the second via hole 702 are respectively located on two sides of the gate 600 ;

[0086] A source electrode 810 and a drain electrode 820 are formed on the dielectric layer 700 . The source electrode 810 is electrically connected to the source region 410 through a first via hole 701 , and the drain electrode 820 is electrically connected to the drain region 420 through a second via hole 702 .

[0087] In some embodiments, the method for manufacturing the array substrate further includes the following steps:

[0088] A planarization layer 800 is formed on the dielectric layer 700 and covers the source electrode 810 and the drain electrode 820 .

[0089] A BITO layer 900 is formed on the planar layer 800 .

[0090] A passivation layer 1000 is formed on the BITO layer 900 .

[0091] A TITO layer 1100 is formed on the passivation layer 1000 .

[0092] The present application provides a specific method for preparing an array substrate 10, comprising the following steps:

[0093] A substrate 100 is provided. The substrate 100 may be, but is not limited to, a glass substrate.

[0094] A light shielding layer 200 is first formed on the substrate 100 using a physical vapor deposition (PVD) process. The light shielding layer 200 is then patterned using a patterning process (e.g., including exposure, development, and etching) to obtain a light shielding layer pattern. The light shielding layer 200 can be made of molybdenum (Mo), aluminum (Al), or a molybdenum-aluminum alloy.

[0095] The buffer layer 300 is deposited on the surface of the light shielding layer 200 by a chemical vapor deposition (CVD) process. The material of the buffer layer 300 can be SiO x and SiN x At least one of the following. Then, the buffer layer 300 is patterned by a patterning process (e.g., including exposure, development, and etching) to form a groove-shaped pattern on the buffer layer 300. The groove has a first surface 301 (i.e., the bottom surface of the groove), a first inclined surface 302, and a second inclined surface 303 (i.e., the sidewalls of the groove). The first inclined surface 302 and the second inclined surface 303 are respectively connected to the ends of the first surface 301. The first inclined surface 302 and the second inclined surface 303 are respectively inclined relative to the first surface 301. The first surface 301 is parallel to the substrate 100. The taper angle α1 between the first inclined surface 302 and the first surface 301 is in the range of 0°<α1<90°, preferably 45°≤α1≤60°; the taper angle α2 between the second inclined surface 303 and the first surface 301 is in the range of 0°<α2<90°, preferably 45°≤α1≤60°. The taper angle α1 and the taper angle α2 may be equal or unequal, and are set according to actual process requirements.

[0096] An active layer 400 is deposited on the buffer layer 300 by a chemical vapor deposition process. The material of the active layer 400 can be, but is not limited to, amorphous silicon a-Si. The a-Si is converted into polycrystalline silicon by an excimer laser annealing (ELA) process to form a polycrystalline silicon active layer. The active layer 400 is patterned by a composition process (e.g., including exposure, development, and etching) to obtain an active layer pattern. The active layer 400 includes a source region 410, a drain region 420, and a channel region 430 located between the source region 410 and the drain region 420; the channel region 430, the source region 410, and the drain region 420 are respectively located on the first surface 301, the first inclined surface 302, and the second inclined surface 303.

[0097] Phosphorus ions are heavily doped on the source region 410 and the drain region 420 through exposure and development processes to form a first heavily doped region 411 on the first inclined surface 302 and a second heavily doped region 421 on the second inclined surface 303 .

[0098] A gate insulating layer 500 is deposited on the buffer layer 300 and the active layer 400 by a chemical vapor deposition process, and the gate insulating layer 500 covers the active layer 400. The material of the gate insulating layer can be but is not limited to SiO x .

[0099] The gate 600 is deposited on the gate insulating layer 500 by a physical vapor deposition process. The material of the gate 600 can be, but is not limited to, a metal such as molybdenum (Mo). Then, the gate 600 is patterned by a composition process (for example, including exposure, development, and etching) to produce a gate pattern. The gate 600 is positioned opposite to the channel region 430. The gate 600 is then used as a mask to lightly dope the active layer 400 with phosphorus ions to form a first lightly doped region 412 and a second lightly doped region 422. The first lightly doped region 412 is located between the first heavily doped region 411 and the channel region 430; the second lightly doped region 422 is located between the second heavily doped region 421 and the channel region 430.

[0100] A dielectric layer 700 is deposited on the gate insulating layer 500 and the gate 600 by a chemical vapor deposition process. The dielectric layer 700 covers the gate 600. The material of the dielectric layer can be SiO x and SiN x At least one of the following. The channel region 430 is then hydrogenated and activated by a rapid thermal annealing process, and the dielectric layer 700 is patterned by a composition process (e.g., including exposure, development, and etching) to form a first via hole 701 and a second via hole 702 in the dielectric layer 700. The first via hole 701 and the second via hole 702 are respectively located on either side of the gate 600. The first via hole 701 penetrates the gate insulating layer 500 to expose one side of the first heavily doped region 411; the second via hole 702 penetrates the gate insulating layer 500 to expose one side of the second heavily doped region 421.

[0101] A source and drain metal layer is deposited on the dielectric layer 700 using a physical vapor deposition process. Subsequently, a patterning process (e.g., including exposure, development, and etching) is used to form source and drain electrodes 810 and 820 patterns on the dielectric layer 700. The materials of the source and drain electrodes 810 and 820 may be Ti / Al / Ti / , Mo / Al / Mo metal stacks, etc. The source electrode 810 is electrically connected to one side of the first heavily doped region 411 through the first via 701; the drain electrode 820 is electrically connected to one side of the second heavily doped region 421 through the second via 702.

[0102] A layer of organic photoresist is coated on the dielectric layer 700 as a planarization layer 800, which covers the source electrode 810 and the drain electrode 820. A first through-hole is then formed in the planarization layer 800 through a patterning process (e.g., including exposure, development, and etching), exposing one side of the drain electrode 820.

[0103] A BITO layer 900 is deposited on the flat layer 800 by a physical vapor deposition process, wherein the material of the BITO layer 900 is indium tin oxide. Then, a BITO pattern is formed on the BITO layer 900 by a composition process (for example, including exposure, development, and etching), and a second through hole corresponding to the first through hole is made on the BITO layer 900.

[0104] A passivation layer 1000 is deposited on the planar layer 800 and the BITO layer 900 by a chemical vapor deposition process. The passivation layer 1000 covers the BITO layer 900. The material of the passivation layer 1000 can be SiO x and SiN x Then, a third through hole corresponding to the second through hole is formed in the passivation layer 1000 through a patterning process (eg, including exposure, development, and etching).

[0105] A TITO layer 1100 is deposited on the passivation layer 1000 using a physical vapor deposition process. The material of the TITO layer 1100 is indium tin oxide. A TITO pattern is then formed on the TITO layer 1100 through a patterning process (e.g., including exposure, development, and etching). The TITO layer 1100 is electrically connected to the drain electrode 820 through the third through hole, the second through hole, and the first through hole to form a pixel electrode.

[0106] This application provides another specific method for preparing the array substrate 10:

[0107] Another specific preparation method provided in this application has substantially the same steps as the above-mentioned specific preparation method of the array substrate 10 , the only difference being that the pattern of the buffer layer is formed differently. The specific steps are as follows:

[0108] The buffer layer 300 is deposited on the surface of the light shielding layer 200 by a chemical vapor deposition (CVD) process. The material of the buffer layer 300 can be SiO x and SiN x Then, the buffer layer 300 is patterned by a patterning process (e.g., including exposure, development, and etching) to form a boss-shaped pattern on the buffer layer 300. The boss has a first surface 301 (i.e., the top surface of the boss), a first inclined surface 302, and a second inclined surface 303 (i.e., the two inclined surfaces of the boss). The first inclined surface 302 and the second inclined surface 303 are respectively connected to the two ends of the first surface 301. The first inclined surface 302 and the second inclined surface 303 are respectively inclined relative to the first surface 301. The first surface 301 is parallel to the substrate 100.

[0109] This application provides another specific method for preparing the array substrate 10:

[0110] Another specific preparation method provided in the present application has substantially the same steps as the above-mentioned specific preparation method for the array substrate 10, with the only difference being that the pattern of the buffer layer is different. The specific steps are as follows:

[0111] The buffer layer 300 is deposited on the surface of the light shielding layer 200 by a chemical vapor deposition (CVD) process. The material of the buffer layer 300 can be SiO x and SiN x Then, the buffer layer 300 is patterned by a patterning process (e.g., including exposure, development, and etching) to form a pattern on the buffer layer 300 including a first surface 301, a first inclined surface 302, and a second inclined surface 303. The first inclined surface 302 and the second inclined surface 303 are respectively connected to two ends of the first surface 301. The first inclined surface 302 and the second inclined surface 303 are respectively inclined relative to the first surface 301. The first surface 301 is parallel to the substrate 100. The first inclined surface 302 and the second inclined surface 303 are located on opposite sides of the first surface 301. Specifically, the first inclined surface 302 is located on a side of the first surface 301 away from the substrate 100, and the second inclined surface 303 is located on a side of the first surface 301 close to the substrate 100.

[0112] In other embodiments, the structures and steps are not limited to the above structures and steps and can be adjusted according to actual conditions.

[0113] In summary, although the present application has been disclosed as above with preferred embodiments, the above preferred embodiments are not intended to limit the present application. Ordinary technicians in this field can make various changes and modifications without departing from the spirit and scope of the present application. Therefore, the scope of protection of the present application shall be based on the scope defined by the claims.

Claims

1. An array substrate, characterized in that: include: substrate; a patterned buffer layer located on one side of the substrate; the patterned buffer layer includes a first surface, a first inclined surface, and a second inclined surface, wherein the first inclined surface and the second inclined surface are respectively connected to two ends of the first surface, and the first inclined surface and the second inclined surface are respectively inclined relative to the first surface; and an active layer located on the buffer layer; the active layer comprising a source region, a drain region, and a channel region located between the source region and the drain region; the channel region, the source region, and the drain region are located on the first surface, the first inclined surface, and the second inclined surface, respectively; a gate, located on one side of the active layer and opposite to the channel region; a source electrode and a drain electrode, located on one side of the active layer and electrically connected to the source region and the drain region respectively; The slope angle between the first inclined surface and the first surface is α1, the slope angle between the second inclined surface and the first surface is α2, and the difference between the area of ​​the active layer and the projected area of ​​the active layer on the substrate is L1*W1*(1-cosα1)+L2*W2*(1-cosα2), where L1 is the slope length of the first inclined surface, L2 is the slope length of the second inclined surface, W1 is the width of the first inclined surface, and W2 is the width of the second inclined surface.

2. The array substrate according to claim 1, wherein: The first inclined surface and the second inclined surface are located on the same side of the first surface. A groove is formed on the buffer layer. The first surface is the bottom surface of the groove. The first inclined surface and the second inclined surface are two side walls of the groove.

3. The array substrate according to claim 1, wherein: The first inclined surface and the second inclined surface are located on the same side of the first surface, forming a boss on the buffer layer. The first surface is the top surface of the boss, and the first inclined surface and the second inclined surface are two inclined surfaces of the boss respectively.

4. The array substrate according to claim 1, wherein: The first inclined surface and the second inclined surface are located on different sides of the first surface.

5. The array substrate according to claim 1, wherein: The slope angle α1 is equal to the slope angle α2.

6. The array substrate according to claim 1, wherein: The slope angle α1 is not equal to the slope angle α2.

7. The array substrate according to claim 1, wherein: The source region includes a first heavily doped region and a first lightly doped region located between the first heavily doped region and the channel region; the drain region includes a second heavily doped region and a second lightly doped region located between the second heavily doped region and the channel region; the source is electrically connected to the first heavily doped region, and the drain is electrically connected to the second heavily doped region.

8. The array substrate according to claim 7, wherein: The array substrate further includes: a light-shielding layer, the light-shielding layer being located between the substrate and the buffer layer, wherein a projection of the light-shielding layer on the substrate overlaps with a projection of the first lightly doped region, the channel region, and the second lightly doped region on the substrate; a gate insulating layer, the gate insulating layer being located between the active layer and the gate; A dielectric layer is located between the gate and the source and drain; the dielectric layer has a first region parallel to the first inclined surface, a second region parallel to the second inclined surface, and a third region parallel to the first surface, the source is located on the first region, and the drain is located on the second region.

9. A method for preparing an array substrate, characterized in that: A method for preparing the array substrate according to any one of claims 1 to 8, wherein the method comprises the following steps: providing a substrate; forming a buffer layer on the substrate, and patterning the buffer layer to form a pattern on the buffer layer, wherein the pattern has a first surface, a first inclined surface, and a second inclined surface, wherein the first inclined surface and the second inclined surface are respectively connected to two ends of the first surface, and the first inclined surface and the second inclined surface are respectively inclined relative to the first surface; forming an active layer on the buffer layer, the active layer comprising a source region, a drain region, and a channel region located between the source region and the drain region, wherein the channel region, the source region, and the drain region are respectively located on the first surface, the first inclined surface, and the second inclined surface; forming a gate insulating layer on the active layer; forming a gate on the gate insulating layer, wherein the gate is opposite to the channel region; forming a dielectric layer on the gate; forming a first via hole and a second via hole on the dielectric layer and the gate insulating layer, wherein the first via hole and the second via hole are respectively located on two sides of the gate; A source electrode and a drain electrode are formed on the dielectric layer, wherein the source electrode is electrically connected to the source region through the first via hole, and the drain electrode is electrically connected to the drain region through the second via hole.

Images