Display substrate and manufacturing method thereof, and display device

Abstract

A display substrate and a preparation method thereof, and a display device, the display substrate comprising: a substrate and a driving circuit layer arranged on the substrate, the driving circuit layer comprising: at least one pixel circuit and a light shielding layer, the light shielding layer being located on a side of the at least one pixel circuit away from the substrate; the pixel circuit comprising: at least one first transistor, at least one second transistor and at least one capacitor, the capacitor comprising at least one first sub-capacitor; the orthographic projection of the light shielding layer on the substrate does not overlap with the orthographic projection of the at least one first transistor on the substrate; the orthographic projection of the light shielding layer on the substrate overlaps with the orthographic projections of the at least one second transistor and the at least one first sub-capacitor on the substrate.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to, but are not limited to, the field of display technology, and specifically relate to a display substrate and a method for preparing the same, and a display device. Background Art

[0002] Organic Light Emitting Diode (OLED) and Quantum-dot Light Emitting Diode (QLED) are active light-emitting display devices with the advantages of self-luminescence, wide viewing angle, high contrast, low power consumption, extremely high response speed, light weight, flexibility and low cost.

[0003] In recent years, low temperature polysilicon thin film transistors (LTPS TFT) and oxide thin film transistors have attracted much attention in the display industry, each with its own advantages. Low temperature polysilicon thin film transistors have the advantages of high mobility and fast charging, while oxide thin film transistors have the advantages of low leakage current and low power consumption. Summary of the invention

[0004] The following is a summary of the subject matter of the detailed description of the present disclosure. This summary is not intended to limit the scope of the claims.

[0005] In a first aspect, an embodiment of the present disclosure provides a display substrate, comprising: a substrate and a driving circuit layer disposed on the substrate, the driving circuit layer comprising: at least one pixel circuit and a light shielding layer, the light shielding layer being located on a side of the at least one pixel circuit away from the substrate;

[0006] The pixel circuit comprises: at least one first transistor, at least one second transistor and at least one capacitor, wherein the capacitor comprises at least one first sub-capacitor;

[0007] The orthographic projection of the light shielding layer on the substrate does not overlap with the orthographic projection of the at least one first transistor on the substrate;

[0008] The orthographic projection of the light shielding layer on the substrate overlaps with the orthographic projections of the at least one second transistor and the at least one first sub-capacitor on the substrate.

[0009] In an exemplary embodiment, the orthographic projection of the at least one first sub-capacitor on the substrate is located in the orthographic projection of the light-shielding layer on the substrate, and the area of ​​the orthographic projection of the at least one first sub-capacitor on the substrate is not larger than the area of ​​the orthographic projection of the light-shielding layer on the substrate.

[0010] In an exemplary embodiment, the at least one first sub-capacitor is located on a side of the at least one second transistor close to the substrate, and an orthographic projection of the at least one first sub-capacitor on the substrate overlaps with an orthographic projection of the at least one second transistor on the substrate.

[0011] In an exemplary embodiment, the pixel circuit further includes at least one third transistor, and an orthographic projection of a first sub-capacitor on the substrate overlaps with both an orthographic projection of the at least one second transistor and an orthographic projection of the at least one third transistor on the substrate.

[0012] In an exemplary embodiment, the first sub-capacitor includes a first electrode plate and a second electrode plate sequentially disposed on the substrate, and the first electrode plate and the second electrode plate overlap in their orthographic projections on the substrate.

[0013] In an exemplary embodiment, the orthographic projection of the first electrode plate on the substrate is located in the orthographic projection of the second electrode plate on the substrate, and the orthographic projection area of ​​the first electrode plate on the substrate is not greater than the orthographic projection area of ​​the second electrode plate on the substrate.

[0014] In an exemplary embodiment, the first transistor includes at least a first active layer pattern and a first gate which are sequentially disposed on the substrate, and the first active layer pattern and the first gate overlap in an orthographic projection of the substrate.

[0015] In an exemplary embodiment, the driving circuit layer further includes: a semiconductor layer and a first conductive layer sequentially disposed on the substrate;

[0016] The semiconductor layer includes the first active layer pattern and the first electrode plate;

[0017] The first conductive layer includes the first gate and the second plate.

[0018] In an exemplary embodiment, the driving circuit layer further includes: a semiconductor layer, a first conductive layer, and a second conductive layer sequentially disposed on the substrate;

[0019] The semiconductor layer includes the first active layer pattern;

[0020] The first conductive layer includes the first gate and the first electrode plate;

[0021] The second conductive layer includes the second electrode plate.

[0022] In an exemplary embodiment, the material of the first active layer pattern is low temperature polysilicon.

[0023] In an exemplary embodiment, the capacitor further includes: at least one second sub-capacitor, the at least one second sub-capacitor is electrically connected to the at least one first sub-capacitor, and the orthographic projection of the at least one second sub-capacitor on the substrate does not overlap with the orthographic projection of the light-shielding layer on the substrate.

[0024] In an exemplary embodiment, an orthographic projection of the at least one second sub-capacitor on the substrate overlaps with an orthographic projection of the at least one first transistor on the substrate.

[0025] In an exemplary embodiment, the second sub-capacitor includes a third plate and a fourth plate sequentially disposed on the substrate, and the third plate and the fourth plate overlap in their orthographic projections on the substrate.

[0026] In an exemplary embodiment, the orthographic projection of the third electrode plate on the substrate is located in the orthographic projection of the fourth electrode plate on the substrate, and the orthographic projection area of ​​the third electrode plate on the substrate is not greater than the orthographic projection area of ​​the fourth electrode plate on the substrate.

[0027] In an exemplary embodiment, the first transistor includes at least a first active layer pattern and a first gate sequentially disposed on the substrate, the first active layer pattern and the first gate overlap in an orthographic projection of the substrate, and the third electrode plate is reused as the first gate.

[0028] In an exemplary embodiment, the second transistor includes a second gate, a second active layer pattern and a third gate sequentially arranged on the substrate, the second gate is located on a side of the second active layer pattern close to the substrate, the third gate is located on a side of the second active layer pattern away from the substrate, and the second gate, the second active layer pattern and the third gate overlap in their orthographic projections on the substrate.

[0029] In an exemplary embodiment, the second transistor includes a second active layer pattern and a third gate which are sequentially disposed on the substrate, and the second active layer pattern and the third gate overlap in an orthographic projection of the substrate.

[0030] In exemplary embodiments, the second active layer pattern material includes an oxide semiconductor.

[0031] In a second aspect, an embodiment of the present disclosure provides a display device, comprising the display substrate as described above.

[0032] In a third aspect, an embodiment of the present disclosure provides a method for preparing a display substrate, comprising:

[0033] forming at least one first transistor and at least one first sub-capacitor on a substrate;

[0034] forming at least one second transistor on a side of the at least one first sub-capacitor away from the substrate;

[0035] forming a light shielding layer on a side of the at least one second transistor away from the substrate;

[0036] Make the orthographic projection of the light shielding layer on the substrate not overlap with the orthographic projection of the at least one first transistor on the substrate;

[0037] The orthographic projection of the light shielding layer on the substrate overlaps with the orthographic projections of the at least one second transistor and the at least one first sub-capacitor on the substrate.

[0038] Other aspects will be apparent upon reading and understanding the drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] The accompanying drawings are used to provide an understanding of the technical solution of the present application and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the technical solution of the present application and do not constitute a limitation on the technical solution of the present application.

[0040] Figure 1 A cross-sectional view of a display substrate of the related art;

[0041] Figure 2 A top view showing a light shielding layer in a substrate according to an embodiment of the present disclosure;

[0042] Figure 3 A top view showing a first sub-capacitor in a substrate according to an embodiment of the present disclosure;

[0043] Figure 4 It is a structural schematic diagram of a display device according to an embodiment of the present disclosure;

[0044] Figure 5 A schematic diagram showing the structure of a substrate according to an embodiment of the present disclosure;

[0045] Figure 6 It is a schematic cross-sectional structure diagram of a display area of ​​a display substrate according to an embodiment of the present disclosure;

[0046] Figure 7 is an equivalent circuit diagram of a pixel circuit according to an embodiment of the present disclosure;

[0047] Fig. 8A A cross-sectional view of a substrate showing an embodiment of the present disclosure Figure 1 ;

[0048] Figure 8B A cross-sectional view of a substrate showing an embodiment of the present disclosure Figure 2 ;

[0049] Figure 8C A cross-sectional view of a substrate showing an embodiment of the present disclosure Figure 3 ;

[0050] Fig.8D A cross-sectional view of a substrate showing an embodiment of the present disclosure Figure 4 ;

[0051] Fig. 8E A cross-sectional view of a substrate showing an embodiment of the present disclosure Figure 5 . DETAILED DESCRIPTION

[0052] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the embodiments of the present disclosure will be described in detail in conjunction with the accompanying drawings below. Note that the embodiments can be implemented in multiple different forms. A person of ordinary skill in the art can easily understand the fact that the methods and contents can be transformed into various forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. In the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be arbitrarily combined with each other.

[0053] In the drawings, the size of each component, the thickness of a layer, or the area is sometimes exaggerated for the sake of clarity. Therefore, one embodiment of the present disclosure is not necessarily limited to this size, and the shape and size of each component in the drawings do not reflect the true proportion. In addition, the drawings schematically show ideal examples, and one embodiment of the present disclosure is not limited to the shapes or values ​​shown in the drawings.

[0054] In the present specification, ordinal numbers such as “first”, “second” and “third” are provided to avoid confusion among constituent elements, and are not intended to limit the number.

[0055] In this specification, for the sake of convenience, the words and phrases indicating the orientation or positional relationship, such as "middle", "upper", "lower", "front", "back", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., are used to illustrate the positional relationship of the constituent elements with reference to the drawings. This is only for the convenience of describing this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore cannot be understood as a limitation of the present disclosure. The positional relationship of the constituent elements is appropriately changed according to the direction in which each constituent element is described. Therefore, it is not limited to the words and phrases described in the specification, and can be appropriately replaced according to the situation.

[0056] In this specification, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal communication of two elements. For ordinary technicians in this field, the specific meanings of the above terms in this disclosure can be understood according to specific circumstances.

[0057] In this specification, a transistor refers to an element including at least three terminals: a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to a region where current mainly flows.

[0058] In this specification, the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode. In the case of using transistors with opposite polarities or when the direction of current changes during circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged. Therefore, in this specification, the "source electrode" and the "drain electrode" may be interchanged.

[0059] In this specification, "electrical connection" includes the case where components are connected together through an element having some electrical function. There is no particular limitation on the "element having some electrical function" as long as it can transmit and receive electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.

[0060] In this specification, "parallel" means a state where the angle formed by two straight lines is greater than -10° and less than 10°, and therefore, also includes a state where the angle is greater than -5° and less than 5°. In addition, "perpendicular" means a state where the angle formed by two straight lines is greater than 80° and less than 100°, and therefore, also includes a state where the angle is greater than 85° and less than 95°.

[0061] In this specification, "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced by "conductive film". Similarly, "insulating film" may be replaced by "insulating layer".

[0062] The term "about" in the present disclosure refers to a numerical value that is not strictly limited to allow for process and measurement errors.

[0063] Figure 1 FIG. 4 is a cross-sectional view of a display substrate of the related art. Figure 1 As shown, the display substrate of the related art includes a substrate 101 and a driving circuit layer arranged on the substrate 101, the driving circuit layer includes at least one pixel circuit, and the pixel circuit includes: a first transistor T3, a second transistor T1, a third transistor T2 and a capacitor C'.

[0064] The first transistor T3 may be a low temperature polysilicon thin film transistor (LTPS TFT for short), which has the advantages of high mobility and fast charging. The first transistor T3 may be used as a driving transistor. The second transistor T1 and the third transistor T2 may both be oxide thin film transistors, which have the advantages of low leakage current. The second transistor T1 and the third transistor T2 may both be used as switching transistors. The display substrate combines the low temperature polysilicon thin film transistor and the oxide thin film transistor to form an LTPO product, which improves the display effect of the display substrate.

[0065] After research by the inventors of the present disclosure, it was found that the capacitor C' is located on the side of the active layer of the first transistor T3 away from the substrate 101, and the capacitor C' overlaps with the positive projection of the active layer of the first transistor T3 on the substrate 101, and the capacitor C' is used to stabilize the potential of the N1 point in the first transistor T3. Since the capacitor C' overlaps with the positive projection of the active layer of the first transistor T3 on the substrate 101, the capacitor C' will reduce the resolution, aperture ratio and transmittance of the pixel. For a display substrate with fingerprint recognition, if the transmittance is too low, it will affect the sensitivity and accuracy of its fingerprint recognition. In addition, the area of ​​the positive projection of the capacitor C' on the substrate 101 will be limited. If the area of ​​the positive projection of the capacitor C' on the substrate 101 is too large, it will seriously affect the aperture ratio of the pixel opening, so that the capacitance of the capacitor C' is limited and cannot be increased, affecting the stability of the potential of the N1 point in the first transistor T3.

[0066] The embodiment of the present disclosure provides a display substrate, comprising: a substrate and a driving circuit layer arranged on the substrate, the driving circuit layer comprising: at least one pixel circuit and a light shielding layer, the light shielding layer being located on a side of the at least one pixel circuit away from the substrate;

[0067] The pixel circuit comprises: at least one first transistor, at least one second transistor and at least one capacitor, wherein the capacitor comprises at least one first sub-capacitor;

[0068] The orthographic projection of the light shielding layer on the substrate does not overlap with the orthographic projection of the at least one first transistor on the substrate;

[0069] The orthographic projection of the light shielding layer on the substrate overlaps with the orthographic projections of the at least one second transistor and the at least one first sub-capacitor on the substrate.

[0070] In an exemplary embodiment, the light-shielding layer has a light-shielding function, and the orthographic projection of the light-shielding layer on the substrate overlaps with the active layer in at least one second transistor, so that the light-shielding layer blocks light from irradiating to the active layer in the second transistor, thereby preventing the light from affecting the characteristics of the second transistor.

[0071] Figure 2 The top view of the light shielding layer in the display substrate of the embodiment of the present disclosure. In an exemplary embodiment, the light shielding layer 20 in the display substrate of the embodiment of the present disclosure has a larger area of ​​the positive projection on the substrate. The display substrate of the embodiment of the present disclosure can increase the area of ​​the positive projection of the first sub-capacitor on the substrate without occupying the area of ​​the region where the first transistor is located, thereby increasing the capacitance of the first sub-capacitor, making the potential at the point N1 in the first transistor T3 more stable, and improving the display effect of the display substrate.

[0072] The display substrate of the disclosed embodiment makes the light shielding layer overlap with the first sub-capacitor of the capacitor on the orthographic projection of the substrate, makes the first sub-capacitor of the capacitor not overlap with the orthographic projection of at least one first transistor on the substrate, and moves the first sub-capacitor of the capacitor to the side of the light shielding layer close to the substrate, so that the first sub-capacitor of the capacitor does not affect the resolution, aperture ratio and transmittance of the pixel. For the display substrate with fingerprint recognition, the sensitivity and accuracy of fingerprint recognition are guaranteed.

[0073] In an exemplary embodiment, the orthographic projection of the at least one first sub-capacitor on the substrate is located in the orthographic projection of the light-shielding layer on the substrate, and the area of ​​the orthographic projection of the at least one first sub-capacitor on the substrate is not larger than the area of ​​the orthographic projection of the light-shielding layer on the substrate.

[0074] In an exemplary embodiment, the at least one first sub-capacitor is located on a side of the at least one second transistor close to the substrate, and an orthographic projection of the at least one first sub-capacitor on the substrate overlaps with an orthographic projection of the at least one second transistor on the substrate.

[0075] In an exemplary embodiment, the pixel circuit further includes at least one third transistor, and an orthographic projection of a first sub-capacitor on the substrate overlaps with both an orthographic projection of the at least one second transistor and an orthographic projection of the at least one third transistor on the substrate.

[0076] Figure 3 FIG. 1 is a top view of a first sub-capacitor in a substrate according to an embodiment of the present disclosure. In an exemplary embodiment, as shown in FIG. Figure 3As shown, the first sub-capacitor includes a first electrode plate 21 and a second electrode plate 22 sequentially arranged on the substrate 101, the first electrode plate 21 is located on the side of the second electrode plate 22 close to the substrate 101, and the first electrode plate 21 and the second electrode plate 22 overlap in their orthographic projections on the substrate.

[0077] In an exemplary embodiment, if Figure 3 As shown, the orthographic projection of the first electrode plate 21 on the substrate is located in the orthographic projection of the second electrode plate 22 on the substrate, and the area of ​​the orthographic projection of the first electrode plate 21 on the substrate is not larger than the area of ​​the orthographic projection of the second electrode plate 22 on the substrate. For example, the orthographic projection of the edges around the second electrode plate 22 on the substrate exceeds the orthographic projection of the edges around the first electrode plate 21 on the substrate, so that the second electrode plate 22 completely covers the first electrode plate 21, thereby ensuring the size and uniformity of the first sub-capacitor.

[0078] Figure 4 FIG. 1 is a schematic diagram of the structure of the display device according to an embodiment of the present disclosure. Figure 4 As shown, the display device may include: a timing controller, a data driver, a scan driver, a light-emitting driver and a pixel array. The timing controller is connected to the data driver, the scan driver and the light-emitting driver respectively. The data driver is connected to a plurality of data signal lines (e.g., D1 to Dn), the scan driver is connected to a plurality of scan signal lines (e.g., S1 to Sm), and the light-emitting driver is connected to a plurality of light-emitting control lines (e.g., E1 to Eo). Wherein, n, m and o may be natural numbers. The pixel array may include a plurality of sub-pixels Pxij, and i and j may be natural numbers. At least one sub-pixel Pxij may include: a pixel circuit and a light-emitting element connected to the pixel circuit. The pixel circuit may be connected to the scan signal line, the light-emitting control line and the data signal line, respectively.

[0079] In an exemplary embodiment, the timing controller may provide a grayscale value and a control signal suitable for the specifications of the data driver to the data driver, a clock signal, a scan start signal, etc. suitable for the specifications of the scan driver to the scan driver, and a clock signal, an emission stop signal, etc. suitable for the specifications of the light emitting driver to the light emitting driver. The data driver may generate a data voltage to be provided to the data signal lines D1, D2, D3, ... and Dn using the grayscale value and the control signal received from the timing controller. For example, the data driver may sample the grayscale value using the clock signal, and apply the data voltage corresponding to the grayscale value to the data signal lines D1 to Dn in units of pixel rows. The scan driver may generate a scan signal to be provided to the scan signal lines S1, S2, S3, ... and Sm by receiving a clock signal, a scan start signal, etc. from the timing controller. For example, the scan driver may sequentially provide a scan signal having an on-level pulse to the scan signal lines S1 to Sm. For example, the scan driver may be constructed in the form of a shift register, and may generate a scan signal in a manner that sequentially transmits a scan start signal provided in the form of an on-level pulse to a next-level circuit under the control of a clock signal. The light-emitting driver may generate a light-emitting control signal to be provided to the light-emitting control lines E1, E2, E3, ... and Eo by receiving a clock signal, an emission stop signal, etc. from a timing controller. For example, the light-emitting driver may sequentially provide an emission signal with an off-level pulse to the light-emitting control lines E1 to Eo. For example, the light-emitting driver may be constructed in the form of a shift register, and may generate a light-emitting control signal in a manner that sequentially transmits an emission stop signal provided in the form of an off-level pulse to a next-level circuit under the control of a clock signal.

[0080] Figure 5 FIG. 1 is a schematic diagram showing the structure of a substrate in an embodiment of the present disclosure. Figure 5 As shown, the display substrate of the embodiment of the present disclosure may include a display area 100, a binding area 200 located on one side of the display area 100, and a frame area 300 located on the other side of the display area 100. In some examples, the display area 100 may be a flat area, including a plurality of sub-pixels Pxij constituting a pixel array, and the plurality of sub-pixels Pxij may be configured to display dynamic pictures or still images, and the display area 100 may be referred to as an active area (AA). In some examples, the display substrate may be a flexible substrate, so that the display substrate may be deformable, such as curling, bending, folding, or rolling up.

[0081] In an exemplary embodiment, the binding area 200 may include a fan-out area, a bending area, a driver chip area, and a binding pin area arranged in sequence along a direction away from the display area 100. The fan-out area is connected to the display area 100 and includes at least a data fan-out line, and a plurality of data fan-out lines are configured to connect the data signal lines of the display area 100 in a fan-out routing manner. The bending area is connected to the fan-out area and may include a composite insulating layer provided with a groove, which is configured to bend the driver chip area and the binding pin area to the back of the display area 100. An integrated circuit (IC) may be provided in the driver chip area, and the integrated circuit may be configured to be connected to a plurality of data fan-out lines. The binding pin area may include a binding pad (Bonding Pad), and the binding pad may be configured to be bound and connected to an external flexible printed circuit (FPC).

[0082] In some exemplary embodiments, the display substrate may include a plurality of pixel units arranged in a matrix. For example, at least one pixel unit may include a first sub-pixel emitting a first color light, a second sub-pixel emitting a second color light, and a third sub-pixel and a fourth sub-pixel emitting a third color light. Each sub-pixel may include a pixel circuit and a light-emitting element, the pixel circuit being electrically connected to a scan signal line, a data signal line, and a light-emitting control line, respectively, and the pixel circuit may be configured to receive a data voltage transmitted by the data signal line under the control of the scan signal line and the light-emitting control line, and output a corresponding current to the light-emitting element. The light-emitting element in each sub-pixel is respectively connected to the pixel circuit of the sub-pixel in which it is located, and the light-emitting element is configured to emit light of corresponding brightness in response to the current output by the pixel circuit of the sub-pixel in which it is located.

[0083] In an exemplary embodiment, the first sub-pixel may be a red sub-pixel (R) that emits red light, the second sub-pixel may be a blue sub-pixel (B) that emits blue light, and the third sub-pixel and the fourth sub-pixel may be green sub-pixels (G) that emit green light. In some examples, the shape of the light-emitting element of the sub-pixel may be a rectangle, a rhombus, a pentagon, or a hexagon, and the light-emitting elements of the four sub-pixels may be arranged in a diamond shape to form an RGBG pixel arrangement. In other exemplary embodiments, the light-emitting elements of the four sub-pixels may be arranged in a horizontal parallel arrangement, a vertical parallel arrangement, or a square arrangement, which is not limited in the present disclosure. In other exemplary embodiments, the pixel unit may include three sub-pixels, and the light-emitting elements of the three sub-pixels may be arranged in a horizontal parallel arrangement, a vertical parallel arrangement, or a triangle arrangement, which is not limited in the present disclosure.

[0084] Figure 6 It is a schematic diagram of the cross-sectional structure of the display area of ​​the display substrate according to the embodiment of the present disclosure. Figure 6Schematic diagram of the structure of three sub-pixels in the display area 100. Figure 6 As shown, in a direction perpendicular to the display substrate, the display substrate may include: a substrate 101, a driving circuit layer 102, a light emitting structure layer 103, and a packaging structure layer 104 sequentially arranged on the substrate 101. In some possible implementations, the display substrate may include other film layers, such as a touch structure layer, etc., which is not limited in the present disclosure.

[0085] In an exemplary embodiment, the substrate 101 may be a flexible substrate or a rigid substrate. The driving circuit layer 102 of each sub-pixel may include a pixel circuit composed of a plurality of transistors and capacitors. The light-emitting structure layer 103 of each sub-pixel may include at least an anode 301, a pixel definition layer 302, an organic light-emitting layer 303 and a cathode 304, wherein the anode 301 is connected to the pixel circuit, the organic light-emitting layer 303 is connected to the anode 301, and the cathode 304 is connected to the organic light-emitting layer 303, and the organic light-emitting layer 303 emits light of corresponding colors under the drive of the anode 301 and the cathode 304. The encapsulation structure layer 104 may include a first encapsulation layer 401, a second encapsulation layer 402 and a third encapsulation layer 403 stacked together. The first encapsulation layer 401 and the third encapsulation layer 403 may be made of inorganic materials, and the second encapsulation layer 402 may be made of organic materials. The second encapsulation layer 402 is arranged between the first encapsulation layer 401 and the third encapsulation layer 403 to form an inorganic material / organic material / inorganic material stacked structure, which can ensure that external water vapor cannot enter the light-emitting structure layer 103.

[0086] In an exemplary embodiment, the organic light emitting layer 303 may include a light emitting layer (EML) and any one or more of the following layers: a hole injection layer (HIL), a hole transport layer (HTL), an electron blocking layer (EBL), a hole blocking layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL). In some examples, one or more of the hole injection layer, the hole transport layer, the electron blocking layer, the hole blocking layer, the electron transport layer, and the electron injection layer of all sub-pixels may be a common layer connected together, and the light emitting layers of adjacent sub-pixels may overlap slightly, or may be isolated from each other.

[0087] Figure 7 is an equivalent circuit diagram of a pixel circuit of an embodiment of the present disclosure. In some examples, the pixel circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C or 8T1C structure. The pixel circuit of this exemplary embodiment is described by taking a 7T1C structure as an example. However, this embodiment is not limited to this.

[0088] In some examples, such as Figure 7As shown, the pixel circuit of this example may include seven transistors (i.e., the second transistor T1 to the seventh transistor T7) and a capacitor C. The pixel circuit is respectively connected to ten signal lines (e.g., including: a data signal line DL, a first scanning signal line GL1, a second scanning signal line GL2, a third scanning signal line RST1, a fourth scanning signal line RST2, a light emitting control line EML, a first initial signal line INIT1, a second initial signal line INIT2, a first power line VDD, and a second power line VSS).

[0089] In some examples, the seven transistors of the pixel circuit may be N-type transistors. Using the same type of transistors in the pixel circuit can simplify the process flow, reduce the process difficulty of the display substrate, and improve the yield of the product.

[0090] In some examples, the seven transistors of the pixel circuit may be oxide thin film transistors. The active layer of the oxide thin film transistor may be oxide semiconductor (Oxide). The oxide thin film transistor has the advantages of low leakage current, and the display substrate provided with the oxide thin film transistor can realize low-frequency driving, reduce power consumption, and improve display quality.

[0091] In some examples, the first power line VDD can be configured to provide a constant first voltage signal to the pixel circuit, the second power line VSS can be configured to provide a constant second voltage signal to the pixel circuit, and the first voltage signal is greater than the second voltage signal. The first scan signal line GL1 can be configured to provide a first scan signal SCAN1 to the pixel circuit, the second scan signal line GL1 can be configured to provide a second scan signal SCAN2 to the pixel circuit, the data signal line DL can be configured to provide a data signal DATA to the pixel circuit, and the emission control line EML can be configured to provide an emission control signal EM to the pixel circuit. The third scan signal line RST1 can be configured to provide a third scan signal Reset1 to the pixel circuit, and the fourth scan signal line RST2 can be configured to provide a fourth scan signal Reset2 to the pixel circuit. In some examples, in the nth row of pixel circuits, the third scan signal line RST1 can be electrically connected to the first scan signal line GL1 of the n-1th row of pixel circuits to be input with the first scan signal SCAN1(n-1). The fourth scan signal line RST2 of the n-th row of pixel circuits can be electrically connected to the first scan signal line GL1 of the n-th row of pixel circuits to be input with the first scan signal SCAN1(n). In some examples, the fourth scan signal line RST2 electrically connected to the n-th row of pixel circuits and the third scan signal line RST1 electrically connected to the n+1-th row of pixel circuits can be an integrated structure. Wherein n is an integer greater than 0. In this way, the signal lines of the display substrate can be reduced, and a narrow frame design of the display substrate can be realized. However, this embodiment is not limited to this.

[0092] In some examples, the first initial signal line INIT1 can be configured to provide a first initial signal to the pixel circuit, and the second initial signal line INIT2 can be configured to provide a second initial signal to the pixel circuit. For example, the first initial signal can be different from the second initial signal. The first initial signal and the second initial signal can be constant voltage signals, and their magnitudes can be, for example, between the first voltage signal provided by the first power line VDD and the second voltage signal provided by the second power line VSS, but are not limited thereto. In other examples, the first initial signal and the second initial signal can be the same, and only the first initial signal line can be set to provide the first initial signal.

[0093] In some examples, such as Figure 7 As shown, the gate of the second transistor T1 is electrically connected to the third scan signal line RST1, the first electrode of the second transistor T1 is electrically connected to the first initial signal line INIT1, and the second electrode of the second transistor T1 is electrically connected to the gate of the first transistor T3. The gate of the third transistor T2 is electrically connected to the first scan signal line GL1, the first electrode of the third transistor T2 is electrically connected to the gate of the first transistor T3, and the second electrode of the third transistor T2 is electrically connected to the first electrode of the first transistor T3. The gate of the first transistor T3 is electrically connected to the first node N1, the first electrode of the first transistor T3 is electrically connected to the second node N2, and the second electrode of the first transistor T3 is electrically connected to the third node N3. The first transistor T3 can be called a driving transistor, and the first transistor T3 determines the amount of driving current flowing between the first power line VDD and the second power line VSS according to the potential difference between its gate and its first electrode. The gate of the fourth transistor T4 is electrically connected to the second scan signal line GL2, the first electrode of the fourth transistor T4 is electrically connected to the data signal line DL, and the second electrode of the fourth transistor T4 is electrically connected to the second electrode of the first transistor T3. The gate of the fifth transistor T5 is electrically connected to the light emitting control line EML, the first electrode of the fifth transistor T5 is electrically connected to the first power line VDD, and the second electrode of the fifth transistor T5 is electrically connected to the first electrode of the first transistor T3. The gate of the sixth transistor T6 is electrically connected to the light emitting control line EML, the first electrode of the sixth transistor T6 is electrically connected to the second electrode of the first transistor T3, and the second electrode of the sixth transistor T6 is electrically connected to the anode of the light emitting element EL. The fifth transistor T5 and the sixth transistor T6 can be called light emitting transistors. The gate of the seventh transistor T7 is electrically connected to the fourth scanning signal line RST2, the first electrode of the seventh transistor T7 is electrically connected to the second initial signal line INIT2, and the second electrode of the seventh transistor T7 is electrically connected to the anode of the light emitting element EL. The first sub-capacitor plate of the capacitor C is electrically connected to the gate of the first transistor T3, and the second sub-capacitor plate of the capacitor is electrically connected to the anode of the light emitting element EL.

[0094] In this example, the first node N1 is the connection point of the capacitor C, the second transistor T1, the first transistor T3 and the third transistor T2, the second node N2 is the connection point of the third transistor T2, the fifth transistor T5 and the first transistor T3, the third node N3 is the connection point of the first transistor T3, the fourth transistor T4 and the sixth transistor T6, and the fourth node N4 is the connection point of the sixth transistor T6, the seventh transistor T7, the capacitor C and the light-emitting element EL.

[0095] In some examples, the light emitting element EL may be an OLED, including a stacked first electrode (anode), an organic light emitting layer, and a second electrode (cathode), or may be a QLED, including a stacked first electrode (anode), a quantum dot light emitting layer, and a second electrode (cathode). The second electrode of the light emitting element is connected to a second power line VSS, a signal of the second power line VSS is a continuously provided low level signal, and a signal of the first power line VDD is a continuously provided high level signal.

[0096] In some examples, taking the example that the second transistor T1 to the seventh transistor T7 included in the pixel circuit are all N-type transistors, the operation process of the pixel circuit may include the following stages.

[0097] The first stage A1 is called the initialization stage. The high level signal provided by the third scan signal line RST1 turns on the second transistor T1, and the first initial signal provided by the first initial signal line INIT1 is provided to the first node N1 to initialize the first node N1 and clear the original data voltage in the capacitor C. The first scan signal line GL1, the second scan signal line GL2, the fourth scan signal line RST2 and the light control line EML provide low level signals to turn off the third transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7. In this stage, the light emitting element EL does not emit light.

[0098] The second stage A2 is called the data writing stage or the threshold compensation stage. The first scanning signal line GL1 provides a high level signal, the second scanning signal line GL2 provides a high level signal, and the data signal line DL outputs the data signal DATA. In this stage, since the first sub-capacitor plate of the capacitor C is at a high level, the first transistor T3 is turned on. The first scanning signal line GL1 provides a high level signal to turn on the third transistor T2, the first scanning signal line GL2 provides a high level signal to turn on the fourth transistor T4, and the fourth scanning signal line RST2 provides a high level signal to turn on the seventh transistor T7. The third transistor T2 and the fourth transistor T4 are turned on, so that the data voltage Vdata output by the data signal line DL is provided to the first node N1 through the third node N3, the turned-on first transistor T3, the second node N2, and the turned-on third transistor T2, and the difference between the data voltage Vdata output by the data signal line DL and the threshold voltage Vth of the first transistor T3 is charged into the capacitor. The seventh transistor T7 is turned on, so that the second initial signal provided by the second initial signal line INIT2 is provided to the anode of the light emitting element EL, the anode of the light emitting element EL is initialized (reset), the pre-stored voltage inside it is cleared, the initialization is completed, and the light emitting element EL is ensured not to emit light. The third scanning signal line RST1 provides a low level signal to turn off the second transistor T1. The light emitting control line EML provides a low level signal to turn off the fifth transistor T5 and the sixth transistor T6.

[0099] The third stage A3 is called the light-emitting stage. The light-emitting control line EML provides a high-level signal, and the first scanning signal line GL1, the second scanning signal line GL2, the third scanning signal line RST1 and the fourth scanning signal line RST2 all provide low-level signals. The light-emitting control line EML provides a high-level signal to turn on the fifth transistor T5 and the sixth transistor T6, and the first voltage signal output by the first power line VDD provides a driving voltage to the anode of the light-emitting element EL through the turned-on fifth transistor T5, the first transistor T3 and the sixth transistor T6, driving the light-emitting element EL to emit light.

[0100] During the driving process of the pixel driving circuit, the driving current flowing through the first transistor T3 (ie, the driving transistor) is determined by the voltage difference between its gate and the first electrode. Since the voltage of the first node N1 is Vdata-|Vth|, the driving current of the first transistor T3 is:

[0101] I=K×(Vgs-Vth) 2 =K×[(Vdd-Vdata+|Vth|)-Vth] 2 =K×[Vdd-Vdata] 2 .

[0102] Among them, I is the driving current flowing through the first transistor T3, that is, the driving current driving the light emitting element EL, K is a constant, Vgs is the voltage difference between the gate and the first electrode of the first transistor T3, Vth is the threshold voltage of the first transistor T3, Vdata is the data voltage output by the data signal line DL, and Vdd is the first voltage signal output by the first power line VDD.

[0103] It can be seen from the above formula that the current flowing through the light emitting element EL has nothing to do with the threshold voltage of the first transistor T3. The pixel circuit of this embodiment can better compensate for the threshold voltage of the first transistor T3.

[0104] The display substrate of this embodiment is described below by means of some examples.

[0105] Fig. 8A A cross-sectional view of a substrate showing an embodiment of the present disclosure Figure 1 In an exemplary embodiment, as Fig. 8A As shown, in a direction parallel to the display substrate, the driving circuit layer of the display substrate of the embodiment of the present disclosure may include at least one pixel circuit, and the driving circuit layer includes at least: a first transistor T3, a second transistor T1, a third transistor T2 and a capacitor, and the capacitor includes at least one first sub-capacitor.

[0106] In an exemplary embodiment, the first transistor T3 in the substrate of the present disclosure can be used as a driving transistor. The first transistor T1 can be a low-temperature polysilicon transistor. The first transistor T1 can be one of a top-gate transistor, a bottom-gate transistor, and a double-gate transistor. For example, the first transistor T1 can be a top-gate transistor, and the active layer in the first transistor is located on the side of the gate of the first transistor close to the substrate. The stability of the top-gate transistor is better, such as Fig. 8A shown.

[0107] In an exemplary embodiment, the second transistor T1 and the third transistor T2 in the display substrate of the present disclosure can both be used as switch transistors. The second transistor T1 and the third transistor T2 can both be oxide transistors. The second transistor T1 and the third transistor T2 can both be one of a top-gate transistor, a bottom-gate transistor, and a double-gate transistor. For example, the second transistor T1 and the third transistor T2 can both be double-gate transistors. The second transistor T1 and the third transistor T2 are double-gate transistors, which can improve the on-state current and uniformity of the second transistor T1 and the third transistor T2, such as Fig. 8A shown.

[0108] In an exemplary embodiment, if Fig. 8AAs shown, in a direction perpendicular to the display substrate, the driving circuit layer of the display substrate of the embodiment of the present disclosure includes: a first semiconductor layer, a first conductive layer, a second conductive layer, a second semiconductor layer, a third conductive layer, a fourth conductive layer and a fifth conductive layer arranged in sequence on the substrate 101.

[0109] In an exemplary embodiment, the substrate 101 may be a rigid substrate or a flexible substrate. For example, the rigid substrate may be, but is not limited to, one or more of glass and quartz, and the flexible substrate may be, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fiber.

[0110] In an exemplary embodiment, the flexible substrate may include a first flexible material layer, a first inorganic material layer, a second flexible material layer, and a second inorganic material layer stacked together. The materials of the first flexible material layer and the second flexible material layer may be polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer soft film, and the materials of the first inorganic material layer and the second inorganic material layer may be silicon nitride (SiNx) or silicon oxide (SiOx), etc., to improve the substrate's resistance to water and oxygen.

[0111] In an exemplary embodiment, if Fig. 8A As shown, the first semiconductor layer at least includes a first active layer pattern 2 and a first electrode plate 21. The first active layer pattern 2 and the first electrode plate 21 are both located on one side of the substrate 101. The first active layer pattern 2 and the first electrode plate 21 can be made of the same material and prepared by the same preparation process. Among them, the first active layer pattern 2 and the first electrode plate 21 can both be made of semiconductor materials. For example, the first active layer pattern 2 and the first electrode plate 21 can both be made of low temperature polysilicon (English: Low Temperature Poly-Silicon; abbreviated as: LTPS). However, the embodiments of the present disclosure are not limited to this.

[0112] In an exemplary embodiment, if Fig. 8AAs shown, the first conductive layer at least includes a first gate 3 and a second electrode plate 22, and the first gate 3 and the second electrode plate 22 are both located on the side of the first active layer pattern 2 and the first electrode plate 21 away from the substrate 101. The first gate 3 overlaps with the first active layer pattern 2 in the orthographic projection on the substrate 101. The first gate 3 can be used as the gate of the first transistor T1, and the first active layer pattern 2 can be used as the active layer of the first transistor T1. The second electrode plate 22 overlaps with the orthographic projection of the first electrode plate 21 on the substrate 101, and the first electrode plate 21 can be used as an electrode plate in the first sub-capacitor, and the second electrode plate 22 can be used as another electrode plate in the first sub-capacitor. The first gate 3 and the second electrode plate 22 can both be made of the same material and prepared by the same preparation process. Among them, the first gate 3 and the second electrode plate 22 can both be made of metal materials. However, the embodiments of the present disclosure are not limited to this.

[0113] In an exemplary embodiment, if Fig. 8A As shown, the second conductive layer at least includes a second gate 4 and a third gate 5, and the second gate 4 and the third gate 5 are located on the side of the first gate 3 and the second electrode 22 away from the substrate 101. At least part of the second gate 4 overlaps with the orthographic projection of at least part of the first electrode 21 and at least part of the second electrode 22 on the substrate 101; at least part of the third gate 5 overlaps with the orthographic projection of at least part of the first electrode 21 and at least part of the second electrode 22 on the substrate 101. The second gate 4 can be used as the bottom gate of the second transistor T1, and the third gate 5 can be used as the bottom gate of the third transistor T2. The second gate 4 and the third gate 5 can be made of the same material and prepared by the same preparation process. Among them, the second gate 4 and the third gate 5 can be made of metal materials. However, the embodiments of the present disclosure are not limited to this.

[0114] In an exemplary embodiment, if Fig. 8A As shown, the second semiconductor layer at least includes a second active layer pattern 61 and a third active layer pattern 62, and the second active layer pattern 61 and the third active layer pattern 62 are both located on the side of the second gate 4 and the third gate 5 away from the substrate 101. The second active layer pattern 61 overlaps with the orthographic projection of the second gate 4 on the substrate 101, and the second active layer pattern 61 can be used as the active layer of the second transistor T1; the third active layer pattern 62 overlaps with the orthographic projection of the third gate 5 on the substrate 101, and the third active layer pattern 62 can be used as the active layer of the third transistor T2. The second active layer pattern 61 and the third active layer pattern 62 can both be made of the same material and prepared by the same preparation process. Among them, the second active layer pattern 61 and the third active layer pattern 62 can both be made of oxide semiconductor (Oxide). For example, the second active layer pattern 61 and the third active layer pattern 62 can both be made of one of indium gallium zinc oxide material and indium tin zinc oxide material.

[0115] In an exemplary embodiment, if Fig. 8A As shown, the third conductive layer at least includes a fourth gate 71 and a fifth gate 72, and the fourth gate 71 and the fifth gate 72 are both located on the side of the second active layer pattern 61 and the third active layer pattern 62 away from the substrate 101. The fourth gate 71 overlaps with the orthographic projection of the second active layer pattern 61 and the second gate 4 on the substrate 101. The fourth gate 71 can be used as the top gate of the first transistor T1. The fifth gate 72 overlaps with the orthographic projection of the third active layer pattern 62 and the third gate 5 on the substrate 101. The fifth gate 72 can be used as the top gate of the third transistor T2. The fourth gate 71 and the fifth gate 72 can be made of the same material and prepared by the same preparation process. Among them, the fourth gate 71 and the fifth gate 72 can be made of metal materials. However, the embodiments of the present disclosure are not limited thereto.

[0116] In an exemplary embodiment, if Fig. 8A As shown, the fourth conductive layer at least includes a first electrode 81, a second electrode 82, a third electrode 83 and a fourth electrode 84, and the first electrode 81, the second electrode 82, the third electrode 83 and the fourth electrode 84 are all located on the side of the fourth gate 71 and the fifth gate 72 away from the substrate 101. The first electrode 81 is connected to the third active layer pattern 62 through a first via hole, and the first end of the second electrode 82 is connected to the third active layer pattern 62 through a second via hole. The first electrode 81 can be used as the source of the third transistor T2, and the second electrode 82 can be used as the drain of the third transistor T2. The second end of the second electrode 82 is connected to the second active layer pattern 61 through a third via hole, and the first end of the third electrode 83 is connected to the second active layer pattern 61 through a fourth via hole. The second electrode 82 can be used as the source of the second transistor T1, and the third electrode 83 can be used as the drain of the second transistor T1. The second end of the third electrode 83 is connected to the first active layer pattern 2 through the fifth via hole, and the fourth electrode 84 is connected to the first active layer pattern 2 through the sixth via hole. The third electrode 83 can be used as the source electrode of the first active layer pattern 2, and the fourth electrode 84 can be used as the drain electrode of the first active layer pattern 2. The first electrode 81, the second electrode 82, the third electrode 83 and the fourth electrode 84 can all be made of the same material and prepared by the same preparation process. Among them, the first electrode 81, the second electrode 82, the third electrode 83 and the fourth electrode 84 can all be made of metal materials. However, the embodiments of the present disclosure are not limited thereto.

[0117] In an exemplary embodiment, if Fig. 8AAs shown, the first active layer pattern 2, the first gate 3, the third electrode 83 and the fourth electrode 84 form a first transistor T3; the second gate 4, the second active layer pattern 61, the fourth gate 71, the second electrode 82 and the third electrode 83 form a second transistor T1; the third gate 5, the third active layer pattern 62, the fifth gate 72, the first electrode 81 and the second electrode 82 form a third transistor T2; the first electrode plate 21 and the second electrode plate 22 form a first sub-capacitor. The orthographic projection of a first sub-capacitor on the substrate overlaps with the orthographic projection of at least one second transistor T1 and at least one third transistor T2 on the substrate.

[0118] In an exemplary embodiment, if Fig. 8A As shown, the fifth conductive layer at least includes a light shielding layer 30. The light shielding layer 30 is located on the side of the first electrode 81, the second electrode 82, the third electrode 83 and the fourth electrode 84 away from the substrate 101. The orthographic projection of the light shielding layer 30 on the substrate 101 does not overlap with the orthographic projection of the first transistor T3 on the substrate 101; the orthographic projection of the light shielding layer 30 on the substrate 101 overlaps with the orthographic projection of the second active layer pattern 61 of the second transistor T1 on the substrate 101 and the orthographic projection of the third active layer pattern 62 of the third transistor T2 on the substrate 101. For example, the orthographic projection of the second active layer pattern 61 of the second transistor T1 on the substrate 101 is located in the orthographic projection of the light shielding layer 30 on the substrate 101, and the area of ​​the orthographic projection of the second active layer pattern 61 of the second transistor T1 on the substrate 101 is not larger than the area of ​​the orthographic projection of the light shielding layer 30 on the substrate 101, so that the light shielding layer 30 covers the second active layer pattern 61 of the second transistor T1; the orthographic projection of the third active layer pattern 62 of the third transistor T2 on the substrate 101 is located in the orthographic projection of the light shielding layer 30 on the substrate 101, and the area of ​​the orthographic projection of the third active layer pattern 62 of the third transistor T2 on the substrate 101 is not larger than the area of ​​the orthographic projection of the light shielding layer 30 on the substrate 101, so that the light shielding layer 30 covers the third active layer pattern 62 of the third transistor T2.

[0119] In an exemplary embodiment, if Fig. 8AAs shown, the orthographic projection of the light shielding layer 30 on the substrate 101 overlaps with the orthographic projection of the first sub-capacitor on the substrate 101. For example, the orthographic projection of the first sub-capacitor on the substrate 101 is located in the orthographic projection of the light shielding layer 30 on the substrate 101, and the orthographic projection area of ​​the first sub-capacitor on the substrate 101 is not greater than the orthographic projection area of ​​the light shielding layer 30 on the substrate 101. Specifically, the orthographic projection of the light shielding layer 30 on the substrate 101 overlaps with the orthographic projections of the first electrode plate 21 and the second electrode plate 22 on the substrate 101. For example, the orthographic projection of the first electrode plate 21 on the substrate 101 is located in the orthographic projection of the light-shielding layer 30 on the substrate 101, and the area of ​​the orthographic projection of the first electrode plate 21 on the substrate 101 is not larger than the area of ​​the orthographic projection of the light-shielding layer 30 on the substrate 101; and the orthographic projection of the second electrode plate 22 on the substrate 101 is located in the orthographic projection of the light-shielding layer 30 on the substrate 101, and the area of ​​the orthographic projection of the second electrode plate 22 on the substrate 101 is not larger than the area of ​​the orthographic projection of the light-shielding layer 30 on the substrate 101.

[0120] In an exemplary embodiment, the light shielding layer 30 may be made of a light-proof material or a light-reflecting material. For example, the light shielding layer 30 may be made of a metal material.

[0121] In an exemplary embodiment, if Fig. 8A As shown, the driving circuit layer may also include: a first barrier layer 11, a first inorganic dielectric layer 12, a second inorganic dielectric layer 13, a first interlayer dielectric layer 14, a second barrier layer 15, a third inorganic dielectric layer 16, a second interlayer dielectric layer 17 and a planar layer 18, which are sequentially arranged on the substrate 101. The first barrier layer 11 is located between the substrate 101 and the first semiconductor layer; the first inorganic dielectric layer 12 is located between the first semiconductor layer and the first conductive layer; the second inorganic dielectric layer 13 is located between the first conductive layer and the second conductive layer; the first interlayer dielectric layer 14 and the second barrier layer 15 are located between the second conductive layer and the second semiconductor layer, and the first interlayer dielectric layer 14 is located on the side of the second barrier layer 15 close to the substrate; the third inorganic dielectric layer 16 is located between the second semiconductor layer and the third conductive layer; the second interlayer dielectric layer 17 is located between the third conductive layer and the fourth conductive layer; and the planar layer 18 is located between the fourth conductive layer and the fifth conductive layer. The first inorganic dielectric layer 12 may also be referred to as a first gate insulating layer (GI1), the second inorganic dielectric layer may also be referred to as a second gate insulating layer (GI2), and the third inorganic dielectric layer 16 may also be referred to as a third gate insulating layer (GI3).

[0122] In an exemplary embodiment, the materials of the first inorganic dielectric layer 12, the second inorganic dielectric layer 13 and the third inorganic dielectric layer 16 may all be silicon nitride (SiNx). Silicon nitride may improve the performance of the first transistor T3. However, the embodiments of the present disclosure are not limited thereto.

[0123] Figure 8B A cross-sectional view of a substrate showing an embodiment of the present disclosure Figure 2 In an exemplary embodiment, as Figure 8B As shown, the capacitor of the display substrate of the embodiment of the present disclosure further includes: at least one second sub-capacitor. The at least one second sub-capacitor is electrically connected to the at least one first capacitor. The second sub-capacitor of the display substrate of the embodiment of the present disclosure can increase the capacitance of the capacitor, make the potential of the point N1 in the first transistor T3 more stable, and improve the display effect of the display substrate.

[0124] In an exemplary embodiment, if Figure 8B As shown, the orthographic projection of the second sub-capacitor on the substrate 101 does not overlap with the orthographic projection of the light shielding layer 30 on the substrate 101 , and the second sub-capacitor may not be covered by the light shielding layer 30 .

[0125] In an exemplary embodiment, if Figure 8B As shown, the second sub-capacitor overlaps with the orthographic projection of the first transistor T3 on the substrate 101. For example, the second sub-capacitor overlaps with the orthographic projection of the first active layer pattern 23 in the first transistor T3 on the substrate 101. For example, the orthographic projection of the second sub-capacitor on the substrate 101 is located in the orthographic projection of the first active layer pattern 23 on the substrate 101, and the area of ​​the orthographic projection of the second sub-capacitor on the substrate 101 is not greater than the area of ​​the orthographic projection of the first active layer pattern 23 on the substrate 101.

[0126] In an exemplary embodiment, if Figure 8B As shown, the second sub-capacitor includes a third plate and a fourth plate 24 sequentially arranged on the substrate 101, and the orthographic projections of the third plate and the fourth plate 24 on the substrate 101 overlap. For example, the orthographic projection of the fourth plate 24 on the substrate is located in the orthographic projection of the third plate on the substrate, and the area of ​​the orthographic projection of the fourth plate 24 on the substrate is not greater than the area of ​​the orthographic projection of the third plate on the substrate.

[0127] In an exemplary embodiment, if Figure 8B As shown, the embodiment of the present disclosure shows that the first gate 3 of the first transistor T3 in the substrate is reused as the third electrode plate of the second sub-capacitor, that is, the first gate 3 of the first transistor T3 can be used as the gate of the first transistor T3 and can also be used as the electrode plate of the second sub-capacitor.

[0128] In an exemplary embodiment, if Figure 8B As shown, the second conductive layer in the substrate of the embodiment of the present disclosure includes at least a second gate 4, a third gate 5 and a fourth electrode plate 24. The fourth electrode plate 24 can be made of the same material as the second gate 4 and the third gate 5 and prepared by the same preparation process.

[0129] Figure 8C A cross-sectional view of a substrate showing an embodiment of the present disclosure Figure 3 In an exemplary embodiment, as Figure 8CAs shown, the pixel circuit of the display substrate of the embodiment of the present disclosure can eliminate the second conductive layer, and the second transistor T1 and the third transistor T2 in the pixel circuit are both top-gate transistors. The pixel circuit can eliminate the second sub-capacitor, the second gate in the second transistor T1, and the third gate in the third transistor T2, thereby reducing the preparation steps and the production cost.

[0130] Fig.8D A cross-sectional view of a substrate showing an embodiment of the present disclosure Figure 4 In an exemplary embodiment, as Fig.8D As shown, the second transistor T1 and the third transistor T2 in the pixel circuit are both top-gate transistors. The first conductive layer in the pixel circuit at least includes the first gate 3 and the first electrode 21, and the second conductive layer at least includes the second electrode 22, and the second conductive layer does not include the second gate and the third gate. The first electrode 21 and the second electrode 22 form a first sub-capacitor, so that the first sub-capacitor does not affect the resolution, aperture ratio and transmittance of the pixel.

[0131] In some embodiments, the second transistor T1 and the third transistor T2 in the pixel circuit are both dual-gate transistors. The second electrode plate is multiplexed as the bottom gate of the second transistor T1 and the bottom gate of the third transistor T2; or, the second conductive layer includes a second electrode plate, a second gate and a third gate, the second gate is used as the bottom gate of the second transistor T1, and the third gate is used as the bottom gate of the third transistor T2.

[0132] Fig. 8E A cross-sectional view of a substrate showing an embodiment of the present disclosure Figure 5 In an exemplary embodiment, as Fig. 8E As shown, the capacitor of the display substrate of the embodiment of the present disclosure further includes: at least one second sub-capacitor. The at least one second sub-capacitor is electrically connected to the at least one first capacitor. The second sub-capacitor of the display substrate of the embodiment of the present disclosure can increase the capacitance of the capacitor, make the potential of the point N1 in the first transistor T3 more stable, and improve the display effect of the display substrate.

[0133] In an exemplary embodiment, if Fig. 8E As shown, the orthographic projection of the second sub-capacitor on the substrate 101 does not overlap with the orthographic projection of the light shielding layer 30 on the substrate 101, and the second sub-capacitor may not be covered by the light shielding layer 30. The second sub-capacitor overlaps with the orthographic projection of the first transistor T3 on the substrate 101. The second sub-capacitor includes a third electrode plate and a fourth electrode plate 24 sequentially arranged on the substrate 101, and the orthographic projections of the third electrode plate and the fourth electrode plate 24 overlap on the substrate 101. The embodiment of the present disclosure shows that the first gate 3 of the first transistor T3 in the substrate is reused as the third electrode plate of the second sub-capacitor, that is, the first gate 3 of the first transistor T3 can be used as the gate of the first transistor T3, and can also be used as the electrode plate of the second sub-capacitor.

[0134] like Fig. 8E As shown, the second transistor T1 and the third transistor T2 in the pixel circuit are both top-gate transistors. The first conductive layer in the pixel circuit includes at least the first gate 3 and the first electrode 21, the second conductive layer includes at least the fourth electrode 24 and the second electrode 22, and the second conductive layer does not include the second gate and the third gate. The first gate 3 and the fourth electrode 24 form a second sub-capacitor, and the first electrode 21 and the second electrode 22 form a first sub-capacitor, so that the second sub-capacitor can increase the capacitance of the capacitor, and the first sub-capacitor will not affect the resolution, aperture ratio and transmittance of the pixel.

[0135] In some embodiments, the second transistor T1 and the third transistor T2 in the pixel circuit are both dual-gate transistors. The second electrode plate is multiplexed as the bottom gate of the second transistor T1 and the bottom gate of the third transistor T2; or, the second conductive layer includes a second electrode plate, a second gate and a third gate, the second gate is used as the bottom gate of the second transistor T1, and the third gate is used as the bottom gate of the third transistor T2.

[0136] This embodiment also provides a method for preparing a display substrate, comprising:

[0137] forming at least one first transistor and at least one first sub-capacitor on a substrate;

[0138] forming at least one second transistor on a side of the at least one first sub-capacitor away from the substrate;

[0139] forming a light shielding layer on a side of the at least one second transistor away from the substrate;

[0140] Make the orthographic projection of the light shielding layer on the substrate not overlap with the orthographic projection of the at least one first transistor on the substrate;

[0141] The orthographic projection of the light shielding layer on the substrate overlaps with the orthographic projections of the at least one second transistor and the at least one first sub-capacitor on the substrate.

[0142] This embodiment also provides a display device, including the display substrate as described above.

[0143] In some exemplary embodiments, the display substrate may be a flexible OLED display substrate, a QLED display substrate, a Micro-LED display substrate, or a Mini-LED display substrate. The display device may be: an OLED display, a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, or any other product or component with a display function, but the embodiments of the present disclosure are not limited thereto.

[0144] The drawings in this disclosure only relate to the structures involved in this disclosure, and other structures can refer to the general design. In the absence of conflict, the embodiments of this disclosure, that is, the features in the embodiments, can be combined with each other to obtain new embodiments.

[0145] Those skilled in the art should understand that the technical solutions of the present disclosure may be modified or replaced by equivalents without departing from the spirit and scope of the technical solutions of the present disclosure, and all should be included in the scope of the claims of the present disclosure.

Claims

1. A display substrate, characterized in that: include: A substrate and a driving circuit layer disposed on the substrate, wherein the driving circuit layer comprises: at least one pixel circuit and a light shielding layer, wherein the light shielding layer is located on a side of the at least one pixel circuit away from the substrate; The pixel circuit comprises: at least one first transistor, at least one second transistor and at least one capacitor, wherein the capacitor comprises at least one first sub-capacitor; The orthographic projection of the light shielding layer on the substrate does not overlap with the orthographic projection of the at least one first transistor on the substrate; The orthographic projection of the light shielding layer on the substrate overlaps with the orthographic projection of the at least one second transistor and the at least one first sub-capacitor on the substrate; The capacitor further includes: at least one second sub-capacitor, the at least one second sub-capacitor is electrically connected to the at least one first sub-capacitor, and the orthographic projection of the at least one second sub-capacitor on the substrate does not overlap with the orthographic projection of the light shielding layer on the substrate.

2. The display substrate according to claim 1, characterized in that: The orthographic projection of the at least one first sub-capacitor on the substrate is located in the orthographic projection of the light shielding layer on the substrate, and the orthographic projection area of ​​the at least one first sub-capacitor on the substrate is not larger than the orthographic projection area of ​​the light shielding layer on the substrate.

3. The display substrate according to claim 1, characterized in that: The at least one first sub-capacitor is located on a side of the at least one second transistor close to the substrate, and an orthographic projection of the at least one first sub-capacitor on the substrate overlaps with an orthographic projection of the at least one second transistor on the substrate.

4. The display substrate according to claim 3, characterized in that: The pixel circuit further includes at least one third transistor, and an orthographic projection of a first sub-capacitor on the substrate overlaps with both the orthographic projections of the at least one second transistor and the at least one third transistor on the substrate.

5. The display substrate according to claim 1, characterized in that: The first sub-capacitor includes a first electrode plate and a second electrode plate sequentially arranged on the substrate, and the first electrode plate and the second electrode plate overlap in their orthographic projections on the substrate.

6. The display substrate according to claim 5, characterized in that: The orthographic projection of the first electrode plate on the substrate is located in the orthographic projection of the second electrode plate on the substrate, and the area of ​​the orthographic projection of the first electrode plate on the substrate is not greater than the area of ​​the orthographic projection of the second electrode plate on the substrate.

7. The display substrate according to claim 5, characterized in that: The first transistor at least includes a first active layer pattern and a first gate which are sequentially arranged on the substrate, and the first active layer pattern and the first gate overlap in orthographic projection on the substrate.

8. The display substrate according to claim 7, characterized in that: The driving circuit layer further includes: a semiconductor layer and a first conductive layer sequentially arranged on the substrate; The semiconductor layer includes the first active layer pattern and the first electrode plate; The first conductive layer includes the first gate and the second plate.

9. The display substrate according to claim 7, characterized in that: The driving circuit layer further includes: a semiconductor layer, a first conductive layer and a second conductive layer sequentially arranged on the substrate; The semiconductor layer includes the first active layer pattern; The first conductive layer includes the first gate and the first electrode plate; The second conductive layer includes the second electrode plate.

10. The display substrate according to claim 7, characterized in that: The material of the first active layer pattern is low temperature polysilicon.

11. The display substrate according to claim 1, characterized in that: An orthographic projection of the at least one second sub-capacitor on the substrate overlaps with an orthographic projection of the at least one first transistor on the substrate.

12. The display substrate according to claim 1, characterized in that: The second sub-capacitor includes a third plate and a fourth plate which are sequentially arranged on the substrate, and the third plate and the fourth plate overlap in their orthographic projections on the substrate.

13. The display substrate according to claim 12, characterized in that: The orthographic projection of the third electrode plate on the substrate is located in the orthographic projection of the fourth electrode plate on the substrate, and the orthographic projection area of ​​the third electrode plate on the substrate is not greater than the orthographic projection area of ​​the fourth electrode plate on the substrate.

14. The display substrate according to claim 12, characterized in that: The first transistor at least includes a first active layer pattern and a first gate which are sequentially arranged on the substrate, the first active layer pattern and the first gate overlap in the orthographic projection of the substrate, and the third electrode plate is reused as the first gate.

15. The display substrate according to claim 1, characterized in that: The second transistor includes a second gate, a second active layer pattern and a third gate which are sequentially arranged on the substrate, the second gate is located on a side of the second active layer pattern close to the substrate, the third gate is located on a side of the second active layer pattern away from the substrate, and the second gate, the second active layer pattern and the third gate overlap in their orthographic projections on the substrate.

16. The display substrate according to claim 1, characterized in that: The second transistor includes a second active layer pattern and a third gate which are sequentially disposed on the substrate, and the second active layer pattern and the third gate overlap in an orthographic projection of the substrate.

17. The display substrate according to claim 15 or 16, characterized in that: The second active layer pattern material includes an oxide semiconductor.

18. A display device, characterized in that: The display substrate comprises any one of claims 1 to 17.

19. A method for preparing a display substrate, characterized in that: include: forming at least one first transistor and at least one first sub-capacitor on a substrate; forming at least one second transistor on a side of the at least one first sub-capacitor away from the substrate; forming a light shielding layer on a side of the at least one second transistor away from the substrate; Make the orthographic projection of the light shielding layer on the substrate not overlap with the orthographic projection of the at least one first transistor on the substrate; Make the orthographic projection of the light shielding layer on the substrate overlap with the orthographic projections of the at least one second transistor and the at least one first sub-capacitor on the substrate; The capacitor further includes: at least one second sub-capacitor, the at least one second sub-capacitor is electrically connected to the at least one first sub-capacitor, and the orthographic projection of the at least one second sub-capacitor on the substrate does not overlap with the orthographic projection of the light shielding layer on the substrate.

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