A duty cycle regulator

Abstract

The present invention relates to a duty cycle regulator, comprising: a first duty cycle regulation DCA module, the first DCA module comprising M parallel-connected regulation units, each regulation unit comprising a NOR gate and a PMOS transistor, each regulation unit being configured to: cause a timing delay inputted to the NOR gate from a low level to a high level to turn on the PMOS at a rising edge of a signal, thereby delaying the rising edge of the signal to reduce the duty cycle of the signal; and cause a timing delay inputted to the NOR gate from a high level to a low level to prevent the PMOS from being turned on at a falling edge of the signal, thereby preventing the PMOS from changing the falling edge of the signal.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor devices, and more particularly, to a duty cycle regulator. Background Art

[0002] For some semiconductor devices, there may be a need to adjust the duty cycle. In some cases, it may be desirable to adjust only the rising edge while keeping the falling edge unchanged.

[0003] For example, for DDR5, the duty cycle of the bidirectional data control pin (DQS) internal clock can be adjusted according to Section 4.41 of the JEDEC (Solid State Electronics Association) JESD79-5A specification standard. However, the duty cycle adjustment may affect the tDQSCK timing, which is not expected. Summary of the Invention

[0004] The present invention relates to a duty cycle regulator, comprising: a first duty cycle regulation DCA module, wherein the first DCA module comprises M parallel-connected regulation units, each regulation unit comprising a NOR gate and a PMOS transistor, and each regulation unit being configured to: cause a timing delay inputted to the NOR gate from a low level to a high level to turn on the PMOS transistor at a rising edge of a signal, thereby delaying the rising edge of the signal to reduce the duty cycle of the signal; and cause a timing delay inputted to the NOR gate from a high level to a low level to prevent the PMOS transistor from being turned on at a falling edge of the signal, thereby preventing the PMOS transistor from changing the duty cycle of the signal. The falling edge of the signal, and / or a second duty cycle adjustment DCA module, the second DCA module includes N parallel adjustment units, each adjustment unit includes an NOR gate and an NMOS transistor, and each adjustment unit is configured to: the timing delay of the input to the NOR gate from the low level to the high level causes the NMOS to be turned on at the rising edge of the signal, so that the NMOS advances the rising edge of the signal to increase the duty cycle of the signal; and the timing delay of the input to the NOR gate from the high level to the low level causes the NMOS to not be turned on at the falling edge of the signal, so that the NMOS does not change the falling edge of the signal.

[0005] In the duty cycle regulator described above, the gate of the PMOS is coupled to the output of the NOR gate, the drain of the PMOS is coupled to the input signal whose duty cycle is to be adjusted, and the source of the PMOS is coupled to a power supply, and / or the gate of the NMOS is coupled to the output of the NOR gate, the drain of the NMOS is coupled to the input signal whose duty cycle is to be adjusted, and the source of the NMOS is coupled to ground.

[0006] As described above, in the first DCA module, an inverter is included between the NOR gate and the PMOS.

[0007] As described above, the input signal passes through an inverter before being input to the drain of the NMOS or the PMOS, and the final output signal of the duty cycle regulator includes an inverter before it.

[0008] In the duty cycle regulator as described above, the first input line of the NOR gate of each regulating unit includes an inverter; the first input of the NOR gate of each regulating unit is a high level or a low level, when the first input is a high level, the high level controls the regulating unit to be in a valid state, and when the first input is a low level, the low level controls the regulating unit to be in an invalid state; the second input line of the NOR gate of each regulating unit includes a delay device, so that the second input of the NOR gate of each regulating unit is a delayed input signal, and the state of each regulating unit can be independently controlled.

[0009] As described above, the delay amount generated by the delay device on the input signal is set to: at least make the entire rising edge of the signal whose duty cycle is to be adjusted fall within the low-level area of ​​the delayed input signal, and correspondingly, make the entire falling edge of the signal whose duty cycle is to be adjusted fall within the high-level area of ​​the delayed input signal.

[0010] The duty cycle regulator as described above is provided in a delay phase-locked loop (DLL) circuit, and the change of the rising edge is performed during the DLL locking period.

[0011] The duty cycle regulator as described above is arranged after the MIMIC circuit in the DLL circuit.

[0012] As described above, when the duty cycle regulator includes both the first DCA module and the second DCA module, the first DCA module and the second DCA module are connected in parallel.

[0013] As described above for the duty cycle regulator, M is equal to N.

[0014] The duty cycle regulator as described above includes a duty cycle regulator for the internal clock of the DDR5 four-phase bidirectional data control pin DQS.

[0015] As described above, the duty cycle regulator includes four duty cycle regulators, each phase of the four-phase signal is independently regulated by the corresponding duty cycle regulator, and each duty cycle regulator includes the first DCA module and the second DCA module connected in parallel; the duty cycle regulator for the first phase of the four-phase signal does not change the duty cycle of the first phase; the corresponding duty cycle regulators for the second, third, and fourth phases of the four-phase signal independently adjust the duty cycles of the second, third, and fourth phases.

[0016] As described above, in each duty cycle regulator, the first DCA module includes 7 adjustment units, and the second DCA module includes 7 adjustment units; and the duty cycle regulator is configured to: use the mode register MR43 OP[2:0] to specify the step of the second phase duty cycle adjustment, and use MR43 OP[3] to specify the positive or negative sign of the step, and the step includes 14 steps from -7 to +7; use the mode register MR43 OP[6:4] to specify the step of the third phase duty cycle adjustment, and use MR43 OP[7] to specify the positive or negative sign of the step, and the step includes 14 steps from -7 to +7; use the mode register MR44 OP[2:0] to specify the step of the fourth phase duty cycle adjustment, and use MR44 OP[3] to specify the positive or negative sign of the step, and the step includes 14 steps from -7 to +7.

[0017] As described above, the duty cycle regulator has 14 steps which are realized by utilizing different state combinations of 14 regulating units connected in parallel.

[0018] As described above, the first DCA module of each duty cycle regulator is configured to execute steps +1 to +7, and the second DCA module is configured to execute steps -1 to -7, and wherein steps +1 to +7 correspond to 1 to 7 of the 7 adjustment units in the first DCA module being valid, and steps -1 to -7 correspond to 1 to 7 of the 7 adjustment units in the second DCA module being valid.

[0019] As described above, the duty cycle regulator has an adjustment range of 2ps-4ps for each step, and a total adjustment range of 28ps-56ps for 14 steps.

[0020] As described above, the duty cycle regulator is arranged in a delay locked loop (DLL) circuit, and the DLL circuit includes a frequency divider, which is configured to divide a four-phase input signal into a first phase, a second phase, a third phase and a fourth phase with a phase difference of π / 2 between adjacent phases.

[0021] The present invention also relates to a delay phase-locked loop (DLL) circuit, which includes the duty cycle regulator as described in any one of the above items. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to further illustrate various embodiments of the present invention, a more specific description of various embodiments of the present invention will be presented with reference to the accompanying drawings. It should be understood that these drawings only depict typical embodiments of the present invention and are therefore not to be considered as limiting the scope of protection claimed in the present invention.

[0023] In addition, it should be understood that the drawings illustrate the main connection relationships of the various components, rather than all connection relationships. Moreover, for the purpose of explaining the technical solutions of the present invention, the drawings show exemplary components. More or fewer components may be included in actual applications.

[0024] Figure 1 It is a schematic diagram of the duty cycle adjustment of the four-phase signal;

[0025] Figure 2 is a schematic diagram showing the range and steps of duty cycle adjustment;

[0026] Figure 3a-3b is a schematic diagram of an adjustment unit of a first duty cycle adjustment (DCA) module for increasing a signal duty cycle and a timing diagram thereof;

[0027] Figure 4a-4b is a schematic diagram of an adjustment unit of a second DCA module for reducing a signal duty cycle and its timing diagram;

[0028] Figure 5 This is a circuit diagram of a duty cycle regulator that can increase and decrease the duty cycle of a signal;

[0029] Figure 6a-6b is a schematic diagram of a delay-locked loop (DLL) circuit including a duty cycle regulator and a timing diagram of an output signal of the duty cycle regulator circuit; and

[0030] Figure 7 It is a schematic diagram of the correspondence between the mode register control bits and the steps used for duty cycle adjustment and the control signals received by each adjustment unit in the DDR5 application scenario of the present invention. DETAILED DESCRIPTION

[0031] The following detailed description refers to the accompanying drawings. The accompanying drawings illustrate, by way of example, specific embodiments in which the claimed subject matter may be practiced. It should be understood that the following specific embodiments are intended to provide specific descriptions of typical examples for illustrative purposes and should not be construed as limiting the present invention. Persons skilled in the art, provided they fully understand the spirit and purpose of the present invention, may make appropriate modifications and adjustments to the disclosed embodiments without departing from the spirit and scope of the claimed subject matter.

[0032] In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of each described embodiment. However, it will be apparent to one of ordinary skill in the art that the various described embodiments can be practiced without these specific details. Unless otherwise defined, technical and scientific terms used herein shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs.

[0033] The terms "first", "second", etc. in the specification and claims of this application do not imply any order, quantity or importance, but are merely used to distinguish different components or features. An embodiment is an exemplary implementation or example. References in the specification to "an embodiment", "one embodiment", "some embodiments", "various embodiments" or "other embodiments" mean that the specific features, configurations or characteristics described in conjunction with the embodiment are included in at least some embodiments of the present technology, but not necessarily all embodiments. The various appearances of "an embodiment", "one embodiment", or "some embodiments" do not necessarily refer to the same embodiment. Elements or aspects from one embodiment may be combined with elements or aspects of another embodiment.

[0034] One embodiment of the present invention relates to a duty cycle regulator including a first DCA module. The first DCA module may include M parallel-connected regulation units. Each regulation unit may include a NOR gate and a PMOS transistor. Each regulation unit may be configured such that: a timing delay from a low-level input to a high-level input to the NOR gate causes the PMOS transistor to be turned on at the rising edge of the signal, thereby delaying the rising edge of the signal and reducing the duty cycle of the signal; and a timing delay from a high-level input to a low-level input to the NOR gate causes the PMOS transistor to not be turned on at the falling edge of the signal, thereby preventing the PMOS transistor from changing the falling edge of the signal.

[0035] Another embodiment of the present invention relates to a duty cycle regulator including a second DCA module. The second DCA module may include N parallel-connected regulation units. Each regulation unit may include a NOR gate and an NMOS transistor. Each regulation unit may be configured such that: a timing delay of a low-level to high-level input to the NOR gate causes the NMOS transistor to turn on at the rising edge of the signal, thereby advancing the rising edge of the signal and increasing the duty cycle of the signal; and a timing delay of a high-level to low-level input to the NOR gate causes the NMOS transistor to not turn on at the falling edge of the signal, thereby preventing the NMOS transistor from changing the falling edge of the signal.

[0036] Another embodiment of the present invention may be directed to a duty cycle regulator including the first DCA module and the second DCA module. The first DCA module and the second DCA module may be connected in parallel to achieve both increasing and decreasing the duty cycle, as described in more detail below.

[0037] In the solution of the present invention, only the rising edge of the signal is changed, and the falling edge of the signal is not changed. This complies with the relevant provisions of the DDR5 four-phase DQS internal clock duty cycle adjustment. In a more preferred embodiment, the duty cycle regulator of the present invention can be set in a delay phase-locked loop (DLL) circuit, and the duty cycle can be adjusted after the DLL is locked. Therefore, the solution of the present invention does not change the tDQSCK timing.

[0038] The following description primarily focuses on DDR5. However, it should be understood that the duty cycle adjustment technology of the present invention is not limited to DDR5. The technical solution of the present invention can be used in any scenario requiring duty cycle adjustment. In particular, the technology of the present application is particularly beneficial when it is desirable to adjust the rising edge while keeping the falling edge unchanged.

[0039] For DDR5, the DDR5 duty cycle regulator can be applied to the bidirectional data control pin (DQS) clock tree according to Section 4.41 of the JEDEC (Solid State Electronics Association) JESD79-5A specification standard. Different mode register definitions can be used for single-phase and multi-phase DQS internal clocks. For example, the mode register MR43 OP[3:0] can be used for a single-phase DQS internal clock, while MR43OP[7:0] or MR44 OP[3:0] can be used for a multi-phase DQS internal clock. When applied to DDR5, the present invention is mainly aimed at the duty cycle adjustment of the four-phase DQS internal clock. The four phases of the DQS internal clock may include: ICLK (0°), QCLK (90°), IBCLK (180°) and QBCLK (270°), as described in the DDR5 specification. The duty cycle adjustment for QCLK, IBCLK and QBCLK can be as follows. Figure 1 As shown. Among them, since the rising edge is adjusted, the increase of DCA code corresponds to the postponement of the rising edge (correspondingly, the duty cycle is reduced), and the decrease of DCA code corresponds to the advancement of the rising edge (correspondingly, the duty cycle is increased). In addition, for some applications, the duty cycle adjustment technology of the present invention can generally be used to adjust the three clock signals QCLK (90°), IBCLK (180°) and QBCLK (270°), while ICLK (0°) can remain unchanged. As mentioned above, for the four-phase DQS of DDR5, the duty cycle adjustment circuit only changes the rising edge of the signal, but does not change the falling edge of the signal.

[0040] If combined Figure 2As shown, the duty cycle step adjustment from -7 to +7 can be specified using mode registers MR43 and MR44, respectively. For example, for QCLK duty cycle adjustment, MR43 OP[2:0] can be used to specify the duty cycle adjustment step, and OP[3] can be used to specify the positive or negative sign of the step. For IBCLK duty cycle adjustment, MR43 OP[6:4] can be used to specify the duty cycle adjustment step, and MR43 OP[7] can be used to specify the positive or negative sign of the step. For QBCLK duty cycle adjustment, MR44 OP[2:0] can be used to specify the duty cycle adjustment step, and MR44 OP[3] can be used to specify the positive or negative sign of the step. Generally speaking, circuit design should comply with JEDEC specifications.

[0041] DQS duty cycle adjustment can be located before the DQS clock tree or equivalent. Duty cycle adjustment requires a locked DLL state and will affect the DQS and DQ duty cycle in the following operations:

[0042] a) read;

[0043] b) Read the preamble training;

[0044] c) Read the training pattern;

[0045] d) Mode register read.

[0046] In the scenario where the DQS clock tree uses a four-phase clock, the odd and even duty cycles of all DQS of each device can be adjusted accordingly because the internal four-phase clocks can be independently controlled by the DCA code.

[0047] Reference again Figure 2 , for DDR5's four-phase DQS, adjust the rising edge of the pulse signal. In the duty cycle adjustment of QCLK, IBCLK, and QBCLK, there can be 7 steps for positive and negative adjustment respectively. Therefore, a total of 14 steps can be included. In the present invention, the adjustment range of each step can be approximately 2ps-4ps. Therefore, the total duty cycle adjustment range of the 14 steps can be approximately 28ps-56ps.

[0048] Figure 3a-3b Schematic diagram of a regulating unit of the first DCA module for reducing the signal duty cycle and its timing diagram. Each regulating unit may include a NOR gate 302 and a PMOS transistor 306. Figure 3bThe main design concept of this embodiment is that each adjustment unit can be configured to: the timing delay of the input to the NOR gate 302 from the low level to the high level causes the PMOS 306 to be turned on at the rising edge of the signal (that is, the driving current of the PMOS 306 is valid), so that the PMOS 306 postpones the rising edge of the signal to reduce the duty cycle of the signal; and the timing delay of the input to the NOR gate 302 from the high level to the low level causes the PMOS 306 to not be turned on at the falling edge of the signal (that is, the driving current of the PMOS 306 is invalid), so that the PMOS 306 does not change the falling edge of the signal.

[0049] The first input of the NOR gate 302 of each adjustment unit can be a high level or a low level. When the first input is a high level (for example, Figure 3a C_U shown in <0> = "H"), the high level can control the regulating unit to be in an effective state, that is, to enable the regulating unit. When the first input is a low level (for example, C_U <0> = "L"), a low level can control the regulating unit to be in an invalid state, that is, not enabling the regulating unit. It should be noted that due to the working characteristics of the NOR gate, in order to achieve the above control effect, an inverter 314 can be added to the first line. The second input line of the NOR gate 302 of each regulating unit can include a delay device 308, so that the second input of the NOR gate 302 of each regulating unit is a delayed input signal. For example, in combination with Figure 3b , the second input of the NOR gate 302 may be the delayed input signal IN_D.

[0050] In an embodiment of the present invention, as combined with Figure 3b As shown in the timing diagram of FIG, the delay amount generated by the delay device 308 on the input signal IN can be set to at least make the entire rising edge of the signal whose duty cycle is to be adjusted (which can be, for example, the input signal IN, or if the inverter 310 is used, the input signal IN after passing through the inverter 310) fall within the low level region of the delayed signal IN_D (such as Figure 3b The shape “||” on the left is shown in the box), and accordingly, the entire falling edge of the signal whose duty cycle is to be adjusted falls at least in the high level area of ​​the signal IN_D whose timing is delayed (as shown in the box). Figure 3b (as framed by the shape “||” on the right). Figure 3b Two delay devices 208 are shown, which can be buffers. However, this is only exemplary and not limiting. Based on the above delay setting requirements, other numbers and / or types of delay devices can be set.

[0051] The gate (G) of PMOS 306 can be coupled to the output of NOR gate 302. The drain (D) of PMOS 306 can be coupled to an input signal whose duty cycle is to be adjusted. The input signal whose duty cycle is to be adjusted can be, for example, signal IN, or an IN signal (similar to OUT) with a certain phase delay after passing through inverter 310. Inverter 310 can be added due to the operating characteristics of PMOS. The source (S) of PMOS 306 can be coupled to a power supply. As described above, based on the operating characteristics of PMOS, the input signal IN can pass through inverter 310 before being input to the drain of PMOS 306. In addition, when inverter 310 is added, inverter 312 can be added before the final output of output signal OUT so that the input signal IN and the output signal OUT are in phase. It should be understood that the "coupling" used in this article can include direct connection or indirect connection.

[0052] In a further embodiment, based on the working characteristics of PMOS, in order to achieve the above control effect, Figure 3a The regulation unit may include an inverter 304 between the NOR gate 302 and the PMOS transistor 306. The signal output from the inverter 304 may be as follows Figure 3b CUb <0> As shown. Figure 3b As shown by the shape “||” on the left, during the rising edge of the input signal IN and the output signal OUT (as described above, due to the effect of the inverter, the phase of OUT can be delayed compared to IN), the signal CUb input to the PMOS 306 <0> is at a low level, so PMOS 306 is driven and PMOS 306 can affect the signal OUT. Figure 3b As shown by the shape “||” on the right, during the falling edge of the input signal IN and the output signal OUT, the signal CUb input to the PMOS 306 <0> At a high level, the PMOS 306 is not driven and has no effect on the signal OUT. Due to the operating characteristics of the PMOS, the PMOS 306 will slow down the rise of the rising edge, thereby delaying the rising edge and reducing the duty cycle.

[0053] The present invention can connect multiple Figure 3a The number of adjustment units shown can be set according to actual needs. The state of each adjustment unit can be independently controlled. During use, according to the actual duty cycle adjustment needs, some, all, or none of the adjustment units can be enabled to achieve the desired duty cycle reduction.

[0054] Figure 4a-4bSchematic diagram of a regulating unit of the second DCA module for increasing the signal duty cycle and its timing diagram. Each regulating unit may include a NOR gate 402 and an NMOS transistor 406. Figure 4b The main design concept of this embodiment is that each adjustment unit can be configured to: the timing delay of the input to the NOR gate 402 from the low level to the high level causes the NMOS 406 to be turned on at the rising edge of the signal (that is, the driving current of the NMOS 406 is valid), so that the NMOS 406 advances the rising edge of the signal to increase the duty cycle of the signal; and the timing delay of the input to the NOR gate 402 from the high level to the low level causes the NMOS 406 to not be turned on at the falling edge of the signal (that is, the driving current of the NMOS 406 is invalid), so that the NMOS 406 does not change the falling edge of the signal.

[0055] The first input of the NOR gate 402 of each adjustment unit can be a high level or a low level. When the first input is a high level (for example, Figure 4a C_D shown in <0> = "H"), the high level can control the adjustment unit to be in an effective state, that is, to enable the adjustment unit. When the first input is a low level (for example, C_D <0> = "L"), a low level can control the regulating unit to be in an invalid state, that is, not enabling the regulating unit. It should be noted that due to the working characteristics of the NOR gate, in order to achieve the above control effect, an inverter 414 can be added to the first line. The second input line of the NOR gate 402 of each regulating unit can include a delay device 408, so that the second input of the NOR gate 402 of each regulating unit is a delayed input signal. For example, in combination with Figure 4b , the second input of the NOR gate 402 may be the delayed input signal IN_D.

[0056] In an embodiment of the present invention, as combined with Figure 4b As shown in the timing diagram of FIG, the delay amount generated by the delay device 408 on the input signal IN can be set to at least make the entire rising edge of the signal whose duty cycle is to be adjusted (which can be, for example, the input signal IN, or if the inverter 410 is used, the input signal IN after passing through the inverter 410) fall within the low level region of the delayed signal IN_D (such as Figure 4b The shape “||” on the left is shown in the box), and accordingly, the entire falling edge of the signal whose duty cycle is to be adjusted falls at least in the high level area of ​​the pulse signal IN_D whose timing is delayed (as shown in the box). Figure 4bSince the output of the NOR gate 402 is directly coupled to the NMOS 406, the entire rising edge of the input signal IN or the phase-delayed input signal IN (similar to the phase of OUT) falls on the output CD of the NOR gate 402. <0> The entire falling edge of the input signal IN or the phase-delayed input signal IN (similar to the phase of OUT) falls on the output (CD) of the NOR gate 402 <0> )’s low level area. Figure 4b Two delay devices 308 are shown, which can be buffers. However, this is only exemplary and not limiting. Based on the above delay amount setting requirements, other numbers and / or types of delay devices can be set.

[0057] The gate (G) of NMOS 406 can be coupled to the output of NOR gate 402. The drain (D) of NMOS 406 can be coupled to an input signal whose duty cycle is to be adjusted. The input signal whose duty cycle is to be adjusted can be, for example, signal IN, or an IN signal with a certain phase delay after passing through inverter 410 (similar to OUT). Inverter 410 can be added due to the operating characteristics of NMOS. The source (S) of NMOS 406 can be coupled to ground. As described above, based on the operating characteristics of NMOS, the input signal IN can pass through inverter 410 before being input to the drain of PMOS 406. In addition, when inverter 410 is added, inverter 412 can be added before the final output of output signal OUT so that the input signal IN and the output signal OUT are in phase. It should be understood that the "coupling" used in this article can include direct connection or indirect connection.

[0058] like Figure 4b As shown by the left shape “||”, during the rising edge of the input signal IN and the output signal OUT (as described above, due to the effect of the inverter, the phase of OUT can be delayed compared to IN), the signal CD input to the NMOS 406 <0> is at a high level, so NMOS 406 is driven, and NMOS 406 affects the signal OUT. Figure 4b As shown by the shape “||” on the right, during the falling edge of the input signal IN and the output signal OUT, the signal CD input to the NMOS 406 <0> At a low level, NMOS 406 is not driven and has no effect on signal OUT. Due to the working characteristics of NMOS, NMOS 406 will accelerate the rising edge, thereby advancing the rising edge and increasing the duty cycle.

[0059] The present invention can connect multiple Figure 4aThe number of adjustment units shown can be set according to actual needs. The state of each adjustment unit can be independently controlled. During use, according to the actual duty cycle adjustment needs, some, all, or none of the adjustment units can be enabled to achieve the desired duty cycle increase.

[0060] Figure 5 Schematic diagram of a duty cycle regulator capable of increasing and decreasing the duty cycle of a signal. For a multi-phase signal, each phase of the multi-phase signal can be independently regulated by a corresponding duty cycle regulator. For example, in the application of DDR5 four-phase DQS, the four phases can be independently regulated by four duty cycle regulators. In a preferred embodiment of the present invention, the duty cycle regulator for the first phase of the multi-phase signal (for example, ICLK in the four-phase signal) may not change the duty cycle of the first phase (such as Figure 6b As shown). The corresponding duty cycle regulators for the four-phase signal, for example, the second, third, and fourth phases, can independently adjust the duty cycles of the second, third, and fourth phases.

[0061] Figure 5 The duty cycle regulator may include the first DCA module and the second DCA module. The first DCA module and the second DCA module may be connected in parallel. Furthermore, in a preferred embodiment, the number of regulation units in the first DCA module may be the same as the number of regulation units in the second DCA module. A mixer including PMOS and NMOS transistors enables the duty cycle regulator to shift the rising edge of a signal forward or backward to increase or decrease the duty cycle.

[0062] In the application of DDR5 four-phase DQS, the first DCA module may include 7 adjustment units, and the second DCA module may include 7 adjustment units. As described above, the mode register MR43 OP[2:0] can be used to specify the step of the second phase duty cycle adjustment of the four-phase signal, and MR43 OP[3] can be used to specify the positive or negative sign of the step, and can include 14 steps from -7 to +7; the mode register MR43 OP[6:4] can be used to specify the step of the third phase duty cycle adjustment, and MR43OP[7] can be used to specify the positive or negative sign of the step, and can include 14 steps from -7 to +7; the mode register MR44OP[2:0] can be used to specify the step of the fourth phase duty cycle adjustment, and MR44 OP[3] can be used to specify the positive or negative sign of the step, and can include 14 steps from -7 to +7.

[0063] The 14 steps can be achieved by utilizing different state combinations of the 14 adjustment units in parallel. The first DCA module can be configured to execute steps +1 to +7. The second DCA module can be configured to execute steps -1 to -7. Figure 5As shown, steps +1 to +7 correspond to the activation of 1 to 7 of the 7 adjustment units in the first DCA module, and steps -1 to -7 correspond to the activation of 1 to 7 of the 7 adjustment units in the second DCA module, respectively. The states of the 14 adjustment units can be independently controlled. Therefore, the desired number of adjustment units can be activated based on actual needs to achieve the desired increase / decrease in duty cycle.

[0064] Figure 6a-6b 1 is a schematic diagram of a DLL circuit including a duty cycle regulator according to the present invention and a timing diagram of an output signal of the duty cycle regulator circuit. Figure 6a As shown, in addition to the duty cycle regulators 612-1, 612-2, 612-3, and 612-4 described above, the DLL circuit may further include some other circuits, such as one or more of the following: a phase detector 602, which may be used to detect whether the phase of the clock signal CLK is consistent with the phase of the DLL output signal (e.g., DCA_OUT); a DLL control 604, which may be used to output a control signal to control voltage regulation (e.g., increase U voltage and decrease D voltage) based on the comparison result of the phase detector; a charge pump 606, which may be used to output a control signal based on the control output of the DLL control. Signal, output voltage control signal (VCTRL); voltage controlled delay line (VCDL) 608, can be used to control voltage according to the voltage control signal; MIMIC circuit 610, can be used to simulate the circuit components between CLK and DCA output to simulate the impact of various factors on the input CLK clock signal in the DLL circuit, especially the impact of duty cycle; frequency divider 614, used to divide the four-phase signal from MIMIC into four phases, such as ICLK (0°), QCLK (90°), IBCLK (180°), and QBCLK (270°). Frequency divider 614 can be coupled to each duty cycle regulator 612-1, 612-2, 612-3, 612-4. The operating principles of duty cycle regulators 612-1, 612-2, 612-3, 612-4 are as described above and will not be repeated here.

[0065] Using the present invention Figure 6a The circuit diagram shown in FIG. 1 not only makes the output ICLK signal and CLK phase identical, but also the duty cycle of the output QCLK, BCLK and QBCLK signals can be independently adjusted according to the situation or need. Since the present invention sets the duty cycle regulator in the loop of the DLL circuit, Figure 3a and 4aAs shown, after the phase of the input signal IN is affected by, for example, an inverter (e.g., one or more of 310, 312, 410, or 412), the rising edge of ICLK can be realigned with the rising edge of the clock signal CLK in the DLL circuit after the DLL is locked (thereby, due to the fixed phase relationship between ICLK and QCLK, BCLK, and QBCLK, the phases of QCLK, BCLK, and QBCLK can be restored to the corresponding correct positions), and only the rising edges of QCLK, BCLK, and QBCLK are adjusted, as shown in FIG. Figure 6b As shown in the timing diagram, this avoids affecting the tDQSCK timing.

[0066] Figure 7 This is a diagram showing the correspondence between the mode register control bit and the duty cycle adjustment step in the DDR5 application scenario and the control signal received by each adjustment unit. One of the inputs C_D of the NOR gate of each adjustment unit is <m>or C_U <n>(exist Figure 7 In the example of , m and n can both be "1" or "0." "1" can indicate a high potential, and "0" can indicate a low potential.

[0067] Step = 0 (+0 or -0 as indicated by the dashed box) means that none of the 14 regulation units are enabled, thus applying no delay to the signal. Steps = +1 to +7 correspond to 1 to 7 PMOS regulation units being enabled, thereby reducing the duty cycle by a corresponding amount. Steps = -1 to -7 correspond to 1 to 7 NMOS regulation units being enabled, thereby increasing the duty cycle by a corresponding amount.

[0068] As described herein, for ease of understanding, this specification is mainly described with reference to DDR5 as an example. However, the present invention is not limited to application in DDR5, but can be used in any use scenario where duty cycle adjustment is required. In particular, the technology of the present application is more beneficial for situations where the rising edge needs to be adjusted while the falling edge remains unchanged. In other application scenarios, the corresponding parameters may change, for example, the step adjustment may be a number of steps other than -7 to +7 for 14 adjustment steps, and the number of phases may not be limited to four phases. Other parameters may also change and are not limited to the specific forms described herein, and are not listed here one by one.

[0069] The basic concepts of the present invention have been described above. It will be apparent to those skilled in the art that the above disclosure is merely illustrative and does not constitute a limitation of the present application. Although not explicitly stated herein, those skilled in the art may make various modifications, improvements, and amendments to the present application. Such modifications, improvements, and amendments are suggested in the present application, and such modifications, improvements, and amendments remain within the spirit and scope of the embodiments of the present application.< / n> < / m>

Claims

1. A duty cycle regulator, comprising: A first duty cycle adjustment module, comprising M parallel adjustment units, each adjustment unit comprising a NOR gate and a PMOS transistor, each adjustment unit being configured to: cause a timing delay inputted to the NOR gate from a low level to a high level to turn on the PMOS transistor at a rising edge of a signal, thereby delaying the rising edge of the signal to reduce the duty cycle of the signal; and cause a timing delay inputted to the NOR gate from a high level to a low level to prevent the PMOS transistor from being turned on at a falling edge of the signal, thereby preventing the PMOS transistor from changing the falling edge of the signal, and / or A second duty cycle adjustment module includes N parallel adjustment units, each adjustment unit includes an NOR gate and an NMOS transistor, and each adjustment unit is configured to: a timing delay from a low level to a high level input to the NOR gate causes the NMOS to be turned on at the rising edge of the signal, so that the NMOS advances the rising edge of the signal to increase the duty cycle of the signal; and a timing delay from a high level to a low level input to the NOR gate causes the NMOS to not be turned on at the falling edge of the signal, so that the NMOS does not change the falling edge of the signal.

2. The duty cycle regulator according to claim 1, wherein: The gate of the PMOS is coupled to the output of the NOR gate, the drain of the PMOS is coupled to the input signal whose duty cycle is to be adjusted, the source of the PMOS is coupled to a power supply, and / or A gate of the NMOS is coupled to the output of the NOR gate, a drain of the NMOS is coupled to an input signal whose duty cycle is to be adjusted, and a source of the NMOS is coupled to ground.

3. The duty cycle regulator according to claim 2, wherein: In the first duty cycle adjustment module, an inverter is included between the NOR gate and the PMOS.

4. The duty cycle regulator according to claim 2, wherein: The input signal passes through an inverter before being input to the drain of the NMOS or the PMOS, and the duty cycle regulator includes an inverter before the final output signal.

5. The duty cycle regulator according to claim 2, wherein: The first input line of the NOR gate of each regulating unit includes an inverter; The first input of the NOR gate of each regulating unit is a high level or a low level. When the first input is a high level, the high level controls the regulating unit to be in an effective state. When the first input is a low level, the low level controls the regulating unit to be in an ineffective state. The second input line of the NOR gate of each regulating unit includes a delay device, so that the second input of the NOR gate of each regulating unit is a delayed input signal, and wherein The state of each regulating unit can be controlled independently.

6. The duty cycle regulator according to claim 5, wherein: The delay amount generated by the delay device on the input signal is set to: at least make the entire rising edge of the signal whose duty cycle is to be adjusted fall within the low level area of ​​the delayed input signal, and correspondingly, make the entire falling edge of the signal whose duty cycle is to be adjusted fall within the high level area of ​​the delayed input signal.

7. The duty cycle regulator according to claim 1, wherein: The duty cycle regulator is arranged in a delay phase locked loop (DLL) circuit, and the change of the rising edge is performed during the DLL locking period.

8. The duty cycle regulator according to claim 7, wherein: The duty cycle regulator is arranged after the MIMIC circuit in the DLL circuit.

9. The duty cycle regulator according to claim 1, wherein: When the duty cycle regulator includes both the first duty cycle adjustment module and the second duty cycle adjustment module, the first duty cycle adjustment module and the second duty cycle adjustment module are connected in parallel.

10. The duty cycle regulator according to claim 9, wherein: M equals N.

11. The duty cycle regulator according to any one of claims 1 to 10, characterized in that: The duty cycle regulator includes a duty cycle regulator for the internal clock of the DDR5 four-phase bidirectional data control pin DQS.

12. The duty cycle regulator according to claim 11, wherein: The number of the duty cycle regulators includes four, each phase of the four-phase signal is independently regulated by a corresponding duty cycle regulator, and each duty cycle regulator includes the first duty cycle regulation module and the second duty cycle regulation module connected in parallel; a duty cycle adjuster for a first phase of the four-phase signal that does not vary the duty cycle of the first phase; The respective duty cycle adjusters for the second, third, and fourth phases of the four-phase signal independently adjust the duty cycles of the second, third, and fourth phases.

13. The duty cycle regulator according to claim 12, wherein: In each duty cycle regulator, the first duty cycle regulating module includes 7 regulating units, and the second duty cycle regulating module includes 7 regulating units; and The duty cycle regulator is configured to: Use the mode register MR43 OP[2:0] to specify the step of the second phase duty cycle adjustment, and use MR43 OP[3] to specify the positive or negative sign of the step, and the step includes 14 steps from -7 to +7; Use the mode register MR43 OP[6:4] to specify the step of the third phase duty cycle adjustment, and use MR43 OP[7] to specify the positive or negative sign of the step, and the step includes -7 to +7, a total of 14 steps; The mode register MR44 OP[2:0] is used to specify the step of the fourth phase duty cycle adjustment, and MR44 OP[3] is used to specify the positive or negative sign of the step, and the step includes 14 steps from -7 to +7.

14. The duty cycle regulator according to claim 13, wherein: The 14 steps are achieved by utilizing different state combinations of 14 parallel-connected regulation units.

15. The duty cycle regulator according to claim 14, wherein: The first duty cycle adjustment module of each duty cycle regulator is configured to perform steps +1 to +7, the second duty cycle adjustment module is configured to perform steps -1 to -7, and wherein Steps +1 to +7 correspond to 1 to 7 of the 7 adjustment units in the first duty cycle adjustment module being valid, and steps -1 to -7 correspond to 1 to 7 of the 7 adjustment units in the second duty cycle adjustment module being valid.

16. The duty cycle regulator according to claim 13, wherein: The adjustment range of each step is 2ps-4ps, and the total adjustment range of 14 steps is 28ps-56ps.

17. The duty cycle regulator according to claim 12, wherein: The duty cycle regulator is provided in a delay locked loop (DLL) circuit, which includes a frequency divider configured to divide a four-phase input signal into a first phase, a second phase, a third phase, and a fourth phase, each of which has a phase difference of π / 2 between adjacent phases.

18. A delay phase-locked loop (DLL) circuit, comprising the duty cycle regulator according to any one of claims 1 to 17.

Images