A high speed comparator suitable for digital LDOs

Abstract

The application discloses a high-speed comparator suitable for a digital LDO, which comprises a first-stage gain amplifier, a second-stage preamplifier and a third-stage latch stage, wherein the first-stage gain amplifier compares a positive end input voltage with a negative end input voltage, and outputs a voltage as an input voltage of the second-stage preamplifier; the second-stage preamplifier adopts an NMOS input pair to improve working speed and amplify an input voltage difference; the output voltage of the second-stage preamplifier is used as an input voltage of the third-stage latch stage, and in order to realize working under a sub-1V power supply voltage, the third-stage latch stage introduces two additional auxiliary paths, which can provide different pull-down currents according to different input voltages, and realize high-speed working of the comparator.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit power management technology, specifically a high-speed comparator suitable for digital LDOs. Background Technology

[0002] The comparator is a key component of a digital LDO. It performs a quantized comparison between the LDO's input reference voltage and output voltage, dynamically controlling the number of power transistors on to stabilize the LDO's output voltage. Operating speed, supply voltage, and input offset voltage are three important performance indicators of the comparator, significantly impacting the performance of the digital LDO.

[0003] Based on their structure, common comparators can be divided into three categories: single-stage comparators, two-stage comparators, and three-stage comparators. Single-stage comparators feature low quiescent current, rail-to-rail output, and fast feedback comparison, but their comparison speed is limited by the latch tail current and they employ a multi-transistor stacked structure, requiring a power supply voltage of 1V or higher. Two-stage comparators typically use a PMOS transistor latch input structure, offering high input voltage and fast comparison characteristics, and reducing the number of stacked transistors, thus allowing for a further reduction in the operating voltage. Three-stage comparators add an additional preamplifier stage at the output of the two-stage comparator, further improving the comparison speed. However, in low-power-voltage operating scenarios, such as near-threshold voltage conditions, the output gain of the first two stages of a traditional three-stage comparator decreases sharply, leading to a significant drop in the voltage accuracy input to the third-stage preamplifier circuit, resulting in an increase in the overall comparator output error, thus preventing high-speed comparison operation. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to provide a high-speed comparator suitable for digital LDOs, which addresses the shortcomings of the prior art. The comparator adopts a three-stage circuit structure consisting of a first-stage gain amplifier, a second-stage preamplifier, and a third-stage latch stage. The first two stages mainly serve as preamplifiers to improve the comparator's operating speed under low power supply voltage and low input voltage drop. The third-stage latch circuit introduces two additional auxiliary paths, which can realize rapid comparison of input voltage according to different current flow rates.

[0005] The technical solution adopted by the present invention to solve the above-mentioned technical problems is as follows: a high-speed comparator suitable for digital LDO, comprising a first-stage gain amplifier, a second-stage preamplifier, and a third-stage latch stage;

[0006] The first-stage gain amplifier includes a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, and a fifth transistor M5, wherein M1, M2, and M5 are NMOS transistors, and M3 and M4 are PMOS transistors; the source terminal of M1 is connected to the drain terminal of M5, the drain terminal of M1 is connected to the first-stage signal output terminal FN, and the gate terminal of M1 is connected to the signal input terminal VIP; the source terminal of M2 is connected to the drain terminal of M5, the drain terminal of M2 is connected to the first-stage signal output terminal FP, and the gate terminal of M2 is connected to the signal input terminal VIN; the source terminal of M3 is connected to the power supply signal VDD, the drain terminal of M3 is connected to the first-stage signal output terminal FN, and the gate terminal of M3 is connected to the clock input signal CLK; the source terminal of M4 is connected to the power supply signal VDD, the drain terminal of M4 is connected to the first-stage signal output terminal FP, and the gate terminal of M4 is connected to the clock input signal CLK; the source terminal of M5 is connected to the ground signal GND, and the gate terminal of M5 is connected to the clock input signal CLK.

[0007] The second-stage preamplifier includes a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, and a ninth transistor M9, wherein M6 and M7 are NMOS transistors, and M8 and M9 are PMOS transistors; the source terminal of M6 is connected to the ground signal GND, the drain terminal of M6 is connected to the second-stage signal output terminal RP, and the gate terminal of M6 is connected to the clock signal CLKB, which is generated based on the clock input signal CLK; the source terminal of M7 is connected to the ground signal GND, the drain terminal of M7 is connected to the second-stage signal output terminal RN, and the gate terminal of M7 is connected to the clock signal CLKB; the source terminal of M8 is connected to the power supply signal VDD, the drain terminal of M8 is connected to the second-stage signal output terminal RP, and the gate terminal of M8 is connected to the first-stage signal output terminal FN; the source terminal of M9 is connected to the power supply signal VDD, the drain terminal of M9 is connected to the second-stage signal output terminal RN, and the gate terminal of M9 is connected to the first-stage signal output terminal FP.

[0008] The third-stage latching stage includes twelfth transistor M12, thirteenth transistor M13, fourteenth transistor M14, fifteenth transistor M15, sixteenth transistor M16, seventeenth transistor M17, eighteenth transistor M18, nineteenth transistor M19, twentieth transistor M20, and twenty-first transistor M21. M12, M13, M15, and M16 are NMOS transistors, while M14, M17, M18, M19, M20, and M21 are PMOS transistors. The source terminal of M12 is connected to the ground. The signal GND is connected; the drain of M12 is connected to the source of M15; the gate of M12 is connected to the second-stage signal output terminal RN; the source of M13 is connected to the ground signal GND; the drain of M13 is connected to the source of M16; the gate of M13 is connected to the second-stage signal output terminal RP; the source of M14 is connected to the power supply signal VDD; the drain of M14 is connected to the drain of M12; the gate of M14 is connected to the clock input signal CLK; the drain of M15 is connected to the output signal OUTP; M1... M15's gate terminal is connected to the output signal OUTN; M16's drain terminal is connected to the output signal OUTN, and M16's gate terminal is connected to the output signal OUTP; M17's source terminal is connected to the power supply signal VDD, M17's drain terminal is connected to the drain terminal of M13, and M17's gate terminal is connected to the clock input signal CLK; M18's source terminal is connected to the power supply signal VDD, M18's drain terminal is connected to the output signal OUTP, and M18's gate terminal is connected to the clock input signal CLK; M19's... The source terminal of M19 is connected to the power supply signal VDD; the drain terminal of M19 is connected to the output signal OUTP; and the gate terminal of M19 is connected to the output signal OUTN. The source terminal of M20 is connected to the power supply signal VDD; the drain terminal of M20 is connected to the output signal OUTN; and the gate terminal of M20 is connected to the output signal OUTP. The source terminal of M21 is connected to the power supply signal VDD; the drain terminal of M21 is connected to the output signal OUTN; and the gate terminal of M21 is connected to the clock input signal CLK.

[0009] The third-stage latch has a first auxiliary path and a second auxiliary path. The first auxiliary path includes N parallel first paths, and the second auxiliary path includes N parallel second paths, where N is a positive integer, N = 3 to 10. Each first path includes a twenty-second transistor M22 and a twenty-third transistor M23, where M22 is an NMOS transistor and M23 is a PMOS transistor. The source of M22 is connected to the ground signal GND, the drain of M22 is connected to the drain of M23, and the gate of M22 is connected to the signal input terminal VIN. The source of M23 is connected to the drain of M22, and the drain of M23 is connected to the output signal OUTP. The gate of M23 is connected to the clock signal CLK1, which is generated based on the output signals OUTN, OUTP, and CLKB. Each second path includes a twenty-fourth transistor M24 and a twenty-fifth transistor M25, where M24 is an NMOS transistor and M25 is a PMOS transistor. The source of M24 is connected to the ground signal GND, the drain of M24 is connected to the drain of M25, and the gate of M24 is connected to the signal input terminal VIP. The source of M25 is connected to the drain of M24, the drain of M25 is connected to the output signal OUTN, and the gate of M25 is connected to the clock signal CLK1.

[0010] The first-stage gain amplifier of this invention amplifies the error between the input voltage at the signal input terminal VIP (i.e., the positive input voltage) and the input voltage at the signal input terminal VIN (i.e., the negative input voltage), and outputs it to the second-stage preamplifier. The second-stage preamplifier uses NMOS input transistors to improve the circuit's operating speed and achieve input voltage difference amplification. The third-stage latch stage adopts a positive feedback circuit structure and introduces two auxiliary paths to support normal operation under sub-1V and near-threshold voltages. The introduction of auxiliary paths also helps to improve the comparator's operating speed.

[0011] Preferably, the clock signal CLKB is generated by a clock generation circuit, which includes a tenth transistor M10 and an eleventh transistor M11, wherein M10 is an NMOS transistor and M11 is a PMOS transistor; the source terminal of M10 is connected to the ground signal GND, the source terminal of M11 is connected to the power supply signal VDD, the gate terminals of M10 and M11 are respectively connected to the clock input signal CLK, and the drain terminal of M10 is connected to the drain terminal of M11 to generate the clock signal CLKB.

[0012] Preferably, the clock signal CLK1 is generated by a shutdown circuit, which includes an XOR gate and a NOR gate. The input terminals of the XOR gate are connected to the output signals OUTN and OUTP, respectively. The output terminal of the XOR gate is connected to one input terminal of the NOR gate, and the other input terminal of the NOR gate is connected to the clock signal CLKB. The output terminal of the NOR gate generates the clock signal CLK1.

[0013] Compared with the prior art, the present invention has the following advantages:

[0014] (1) The comparator of the present invention adopts a three-stage circuit structure consisting of a first-stage gain amplifier, a second-stage preamplifier, and a third-stage latch stage. When the rising edge of the clock arrives, the first two stages of the circuit can promptly compare the slight difference between the input voltage of the signal input terminal VIP and the input voltage of the signal input terminal VIN, driving the output signals of the signal output terminals RP and RN of the second-stage preamplifier to be pulled up to the power supply voltage respectively. During the pull-up process, the output signals of RP and RN will generate a voltage value several times greater than the initial input voltage difference, which helps the third-stage latch circuit to compare quickly.

[0015] (2) The comparator of the present invention employs a third-stage latching stage, which accelerates the comparator's operation speed under sub-1V voltage by adding two additional auxiliary paths. When the voltage difference between the input voltage of the signal input terminal VIP and the input voltage of the signal input terminal VIN reaches a certain value, the current flow rates of the two auxiliary paths will differ. The output voltage of one auxiliary path reaches ground potential before the other auxiliary path. Due to the positive feedback effect, the output voltage of the other auxiliary path will be quickly set to a high level, thereby realizing the comparison of input voltages. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of a high-speed comparator structure suitable for digital LDOs according to an embodiment of the present invention;

[0017] Figure 2 This invention provides a time delay comparison between a high-speed comparator in an embodiment of the invention and a conventional two-stage comparator under a 1mV voltage difference.

[0018] Figure 3 This invention provides a time delay comparison between a high-speed comparator and a conventional two-stage comparator under a 10mV voltage difference. Detailed Implementation

[0019] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments.

[0020] An example of a high-speed comparator suitable for digital LDOs, such as Figure 1As shown, it includes a first-stage gain amplifier, a second-stage preamplifier, and a third-stage latch stage.

[0021] In this embodiment, the first-stage gain amplifier includes a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, and a fifth transistor M5, wherein M1, M2, and M5 are NMOS transistors, and M3 and M4 are PMOS transistors; the source terminal of M1 is connected to the drain terminal of M5, the drain terminal of M1 is connected to the first-stage signal output terminal FN, and the gate terminal of M1 is connected to the signal input terminal VIP; the source terminal of M2 is connected to the drain terminal of M5, the drain terminal of M2 is connected to the first-stage signal output terminal FP, and the gate terminal of M2 is connected to the signal input terminal VIN; the source terminal of M3 is connected to the power supply signal VDD, the drain terminal of M3 is connected to the first-stage signal output terminal FN, and the gate terminal of M3 is connected to the clock input signal CLK; the source terminal of M4 is connected to the power supply signal VDD, the drain terminal of M4 is connected to the first-stage signal output terminal FP, and the gate terminal of M4 is connected to the clock input signal CLK; the source terminal of M5 is connected to the ground signal GND, and the gate terminal of M5 is connected to the clock input signal CLK.

[0022] In this embodiment, the second-stage preamplifier includes a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, and a ninth transistor M9, wherein M6 and M7 are NMOS transistors, and M8 and M9 are PMOS transistors; the source terminal of M6 is connected to ground signal GND, the drain terminal of M6 is connected to the second-stage signal output terminal RP, and the gate terminal of M6 is connected to the clock signal CLKB, which is generated based on the clock input signal CLK; the source terminal of M7 is connected to ground signal GND, the drain terminal of M7 is connected to the second-stage signal output terminal RN, and the gate terminal of M7 is connected to the clock signal CLKB; the source terminal of M8 is connected to power supply signal VDD, the drain terminal of M8 is connected to the second-stage signal output terminal RP, and the gate terminal of M8 is connected to the first-stage signal output terminal FN; the source terminal of M9 is connected to power supply signal VDD, the drain terminal of M9 is connected to the second-stage signal output terminal RN, and the gate terminal of M9 is connected to the first-stage signal output terminal FP.

[0023] In this embodiment, the third-stage latch stage includes the twelfth transistor M12, the thirteenth transistor M13, the fourteenth transistor M14, the fifteenth transistor M15, the sixteenth transistor M16, the seventeenth transistor M17, the eighteenth transistor M18, the nineteenth transistor M19, the twentieth transistor M20, and the twenty-first transistor M21. M12, M13, M15, and M16 are NMOS transistors, and M14, M17, M18, M19, M20, and M21 are PMOS transistors. MOS transistors; the source of M12 is connected to ground (GND), the drain of M12 is connected to the source of M15, and the gate of M12 is connected to the second-stage signal output terminal RN; the source of M13 is connected to ground (GND), the drain of M13 is connected to the source of M16, and the gate of M13 is connected to the second-stage signal output terminal RP; the source of M14 is connected to the power supply signal VDD, the drain of M14 is connected to the drain of M12, and the gate of M14 is connected to the clock input signal CLK; M15... The drain of M15 is connected to the output signal OUTP, and the gate of M16 is connected to the output signal OUTN. The drain of M16 is connected to the output signal OUTN, and the gate of M16 is connected to the output signal OUTP. The source of M17 is connected to the power supply signal VDD, the drain of M17 is connected to the drain of M13, and the gate of M17 is connected to the clock input signal CLK. The source of M18 is connected to the power supply signal VDD, the drain of M18 is connected to the output signal OUTP, and the gate of M18 is connected to the clock input signal CLK. The source terminal of M19 is connected to the power supply signal VDD, the drain terminal of M19 is connected to the output signal OUTP, and the gate terminal of M19 is connected to the output signal OUTN; the source terminal of M20 is connected to the power supply signal VDD, the drain terminal of M20 is connected to the output signal OUTN, and the gate terminal of M20 is connected to the output signal OUTP; the source terminal of M21 is connected to the power supply signal VDD, the drain terminal of M21 is connected to the output signal OUTN, and the gate terminal of M21 is connected to the clock input signal CLK.

[0024] In this embodiment, the third-stage latch stage has a first auxiliary path and a second auxiliary path. The first auxiliary path includes N parallel first paths, and the second auxiliary path includes N parallel second paths, where N is a positive integer, N = 3 to 10, and in this embodiment N = 7. Each first path includes a twenty-second transistor M22 and a twenty-third transistor M23, where M22 is an NMOS transistor and M23 is a PMOS transistor. The source terminal of M22 is connected to ground signal GND, the drain terminal of M22 is connected to the drain terminal of M23, and the gate terminal of M22 is connected to the signal input terminal VIN. The source terminal of M23 is connected to the drain terminal of M22, and the drain terminal of M23 is connected to the output signal O. The UTP connection is established, and the gate of M23 is connected to the clock signal CLK1, which is generated based on the output signals OUTN, OUTP, and CLKB. Each second path includes the twenty-fourth transistor M24 and the twenty-fifth transistor M25, where M24 is an NMOS transistor and M25 is a PMOS transistor. The source of M24 is connected to ground GND, the drain of M24 is connected to the drain of M25, and the gate of M24 is connected to the signal input VIP. The source of M25 is connected to the drain of M24, the drain of M25 is connected to the output signal OUTN, and the gate of M25 is connected to the clock signal CLK1.

[0025] In this embodiment, the clock signal CLKB is generated by a clock generation circuit, which includes a tenth transistor M10 and an eleventh transistor M11, wherein M10 is an NMOS transistor and M11 is a PMOS transistor; the source terminal of M10 is connected to the ground signal GND, the source terminal of M11 is connected to the power supply signal VDD, the gate terminals of M10 and M11 are respectively connected to the clock input signal CLK, and the drain terminal of M10 is connected to the drain terminal of M11 to generate the clock signal CLKB; the clock signal CLK1 is generated by a shutdown circuit, which includes an XOR gate and a NOR gate. The input terminals of the XOR gate are respectively connected to the output signals OUTN and OUTP, the output terminal of the XOR gate is connected to one input terminal of the NOR gate, the other input terminal of the NOR gate is connected to the clock signal CLKB, and the output terminal of the NOR gate generates the clock signal CLK1.

[0026] The high-speed comparator of this invention is a three-stage comparator. Compared with the traditional two-stage comparator, this invention adds an additional second-stage preamplifier. When the rising edge of the clock arrives, the first two stages of the circuit can promptly compare the subtle difference between the input voltage at the signal input terminal VIP and the input voltage at the signal input terminal VIN, driving the output signals of the second-stage preamplifier's signal output terminals RP and RN to be pulled high to the power supply voltage. During the pull-up process, the output signals of RP and RN will generate a voltage value several times greater than the initial input voltage difference, which helps the third-stage latch circuit to compare quickly.

[0027] The high-speed comparator of this invention has two working paths in the working state, namely the first working path and the second working path.

[0028] The first operating path consists of the remaining parts excluding the first and second auxiliary paths. Operating phase: When the rising edge of the clock signal arrives, after the first-stage gain amplifier amplifies the error between the reference voltage and the output voltage, the outputs FP and FN of the first-stage gain amplifier drop to GND. This causes the input transistors M8 and M9 of the second-stage preamplifier to have a large gate-source voltage close to VDD. Therefore, the current on M8 and M9 is large enough to quickly pull up RP and RN. During the pull-up process, RP and RN will generate a voltage value several times greater than the initial input voltage difference, causing the current flow rates of the input transistors M12 and M13 in the third-stage latch stage to be inconsistent. This current difference causes the drain of the input transistor with the higher voltage to reach ground potential first, making the output of this circuit reach ground potential first, at which point the circuit enters the latch state. Assuming OUTN reaches ground potential before OUTP, it is equivalent to the gate terminals of M15 and M19 being connected to ground potential, causing M15 to be cut off and M19 to be turned on, and the OUTP potential to become high. The third latch stage will continue the output until the next clock cycle, waiting for the next rising edge of the clock to arrive before performing a new round of adjustments.

[0029] The second operating path mainly consists of the first and second auxiliary paths. Its main operating scheme is as follows: the current through multiple first and second paths in the first and second auxiliary paths depends on the magnitude of the input voltage of the differential pair, i.e., the input voltages of VIN and VIP. During the reset phase, the second operating path operates in the same way as a conventional comparator. During the regeneration phase, the capacitor begins to discharge through the parallel paths. The input signal is fed to all the parallel branches, i.e., N parallel first paths and N parallel second paths, each branch allowing a current of gmVIN to flow. Therefore, the total current of the load capacitor discharges through N+1 branches. For N parallel branches, the effective transconductance of the output node increases by N. 1 / 2This reduces latency. Once the output is generated, conventional comparators have no current path from VDD to ground, thus eliminating static power consumption. However, in the high-speed comparator structure of this invention, which employs a first auxiliary path and a second auxiliary path, when CLK1 is high and the output of one of the auxiliary paths is also high, this auxiliary path will have a ground path that continues until CLK1 is low. This problem is solved by providing an additional auxiliary clock CLK1. This additional auxiliary clock CLK1 is generated by the output signals OUTN, OUTP, and CLKB, and its main function is to set CLK1 low after the output voltage comparison is complete, preventing the aforementioned ground path from continuously discharging.

[0030] The third-stage latch stage of the comparator in this invention employs a method of adding first and second auxiliary paths to support normal operation under low voltage (0.6-1V). The addition of multiple first and second paths further improves the comparison speed above 1V. Under low voltage conditions, the first-stage gain amplifier and the second-stage preamplifier are essentially inactive. Relying on the subthreshold currents of the first and second auxiliary paths, the current flow rates of the first and second auxiliary paths differ due to the voltage difference between the signal input terminals VIN and VIP. The output voltage of one auxiliary path reaches ground potential before the other, and the other auxiliary path is quickly set to a high level. When the supply voltage is above 1V, the paths of the first and second auxiliary paths also generate ground currents, further accelerating the comparison speed. Simultaneously, the third-stage latch stage performs a latching function, storing the comparison result within the current clock cycle.

[0031] The present invention employs a first auxiliary path and a second auxiliary path. Since it does not require separate signal amplification, it is suitable for near-threshold operating conditions, greatly expanding the application range of the comparator of the present invention.

[0032] The comparison results of the delay of the high-speed comparator of this embodiment and the traditional two-stage comparator at 1mV and 10mV are as follows: Figure 2 and Figure 3 As shown. From Figure 2 and Figure 3 It is evident that the transient performance of the high-speed comparator of this invention is superior to that of the traditional two-stage comparator, with a significant improvement in comparison delay. It also possesses a function that the traditional two-stage comparator cannot achieve, namely, high-speed comparison can be performed even at near-threshold voltage.

Claims

1. A high speed comparator suitable for digital LDO, characterized in that, The first stage gain amplifier, the second stage preamplifier and the third stage latch stage are included. The first stage gain amplifier includes a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4 and a fifth transistor M5, wherein M1, M2 and M5 are NMOS transistors, and M3 and M4 are PMOS transistors; the source end of M1 is connected with the drain end of M5, the drain end of M1 is connected with a first stage signal output end FN, and the gate end of M1 is connected with a signal input end VIP; the source end of M2 is connected with the drain end of M5, the drain end of M2 is connected with a first stage signal output end FP, and the gate end of M2 is connected with a signal input end VIN; the source end of M3 is connected with a power signal VDD, the drain end of M3 is connected with the first stage signal output end FN, and the gate end of M3 is connected with a clock input signal CLK; the source end of M4 is connected with the power signal VDD, the drain end of M4 is connected with the first stage signal output end FP, and the gate end of M4 is connected with the clock input signal CLK; the source end of M5 is connected with a ground signal GND, and the gate end of M5 is connected with the clock input signal CLK; The second stage preamplifier includes a sixth transistor M6, a seventh transistor M7, an eighth transistor M8 and a ninth transistor M9, wherein M6 and M7 are NMOS transistors, and M8 and M9 are PMOS transistors; the source end of M6 is connected with the ground signal GND, the drain end of M6 is connected with a second stage signal output end RP, the gate end of M6 is connected with a clock signal CLKB, and the clock signal CLKB is generated based on the clock input signal CLK; the source end of M7 is connected with the ground signal GND, the drain end of M7 is connected with a second stage signal output end RN, and the gate end of M7 is connected with the clock signal CLKB; the source end of M8 is connected with the power signal VDD, the drain end of M8 is connected with the second stage signal output end RP, and the gate end of M8 is connected with the first stage signal output end FN; the source end of M9 is connected with the power signal VDD, the drain end of M9 is connected with the second stage signal output end RN, and the gate end of M9 is connected with the first stage signal output end FP; The third stage of the latch stage includes a twelfth transistor M12, a thirteenth transistor M13, a fourteenth transistor M14, a fifteenth transistor M15, a sixteenth transistor M16, a seventeenth transistor M17, an eighteenth transistor M18, a nineteenth transistor M19, a twentieth transistor M20 and a twenty-first transistor M21, wherein the M12, the M13, the M15 and the M16 are NMOS transistors, and the M14, the M17, the M18, the M19, the M20 and the M21 are PMOS transistors; the source end of the M12 is connected with the ground signal GND, the drain end of the M12 is connected with the source end of the M15, and the gate end of the M12 is connected with the second stage signal output end RN; the source end of the M13 is connected with the ground signal GND, the drain end of the M13 is connected with the source end of the M16, and the gate end of the M13 is connected with the second stage signal output end RP; the source end of the M14 is connected with the power supply signal VDD, the drain end of the M14 is connected with the drain end of the M12, and the gate end of the M14 is connected with the clock input signal CLK; the drain end of the M15 is connected with the output signal OUTP, and the gate end of the M15 is connected with the output signal OUTN; the drain end of the M16 is connected with the output signal OUTN, and the gate end of the M16 is connected with the output signal OUTP; the source end of the M17 is connected with the power supply signal VDD, the drain end of the M17 is connected with the drain end of the M13, and the gate end of the M17 is connected with the clock input signal CLK; the source end of the M18 is connected with the power supply signal VDD, the drain end of the M18 is connected with the output signal OUTP, and the gate end of the M18 is connected with the clock input signal CLK; the source end of the M19 is connected with the power supply signal VDD, the drain end of the M19 is connected with the output signal OUTP, and the gate end of the M19 is connected with the output signal OUTN; the source end of the M20 is connected with the power supply signal VDD, the drain end of the M20 is connected with the output signal OUTN, and the gate end of the M20 is connected with the output signal OUTP; the source end of the M21 is connected with the power supply signal VDD, the drain end of the M21 is connected with the output signal OUTN, and the gate end of the M21 is connected with the clock input signal CLK; The third latch stage has a first auxiliary path and a second auxiliary path, the first auxiliary path includes N first paths in parallel, and the second auxiliary path includes N second paths in parallel, where N is a positive integer, N=3-10; each first path includes a twenty-second transistor M22 and a twenty-third transistor M23, where M22 is an NMOS transistor, and M23 is a PMOS transistor; the source end of M22 is connected with the ground signal GND, the drain end of M22 is connected with the drain end of M23, and the gate end of M22 is connected with the signal input end VIN; the source end of M23 is connected with the drain end of M22, the drain end of M23 is connected with the output signal OUTP, and the gate end of M23 is connected with a clock signal CLK1; each second path includes a twenty-fourth transistor M24 and a twenty-fifth transistor M25, where M24 is an NMOS transistor, and M25 is a PMOS transistor; the source end of M24 is connected with the ground signal GND, the drain end of M24 is connected with the drain end of M25, and the gate end of M24 is connected with the signal input end VIP; the source end of M25 is connected with the drain end of M24, the drain end of M25 is connected with the output signal OUTN, and the gate end of M25 is connected with the clock signal CLK1.

2. The high speed comparator suitable for digital LDO according to claim 1, wherein, The clock signal CLK1 is generated by a turn-off circuit, and the turn-off circuit includes an XOR gate and a NOR gate; the input ends of the XOR gate are connected with the output signal OUTN and the output signal OUTP respectively, the output end of the XOR gate is connected with one input end of the NOR gate, the other input end of the NOR gate is connected with the clock signal CLKB, and the output end of the NOR gate generates the clock signal CLK1.

3. The high speed comparator suitable for digital LDO according to claim 1, wherein, ​

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