Wideband Frequency Synthesizer and Method for Zero-IF Wireless Local Area Network Radio Transceiver

Abstract

A frequency synthesizer and a method thereof. The frequency synthesizer includes: a clock multiplier unit for receiving a first clock and outputting a second clock according to a multiple; a 1:3 frequency divider circuit for receiving the second clock and outputting a third clock; a first 1:2 frequency divider circuit for receiving the second clock and outputting a fourth clock; a second 1:2 frequency divider circuit for receiving the fourth clock and outputting a fifth clock; a first multiplexer for receiving the third clock and the fourth clock and outputting a seventh clock according to a first selection signal; a second multiplexer for receiving the third clock and the fifth clock and outputting an eighth clock according to a second selection signal; and a mixer for receiving the seventh clock and the eighth clock and outputting an output clock.

Description

Technical Field

[0001] This disclosure relates to frequency synthesizers, and more particularly to frequency synthesizers and methods having a tunable voltage-controlled oscillator (VCO). Background Art

[0002] A radio frequency synthesizer for a wireless local area network (WLAN) radio transceiver that transmits and receives radio signals covers a range of approximately 4.8 GHz to 7.2 GHz. In a zero intermediate frequency (zero-IF) radio transceiver, a frequency synthesizer that can generate a clock having the same frequency as the radio signal is required. Therefore, a zero-IF WLAN radio transceiver requires a frequency synthesizer that can generate a clock having a frequency range of approximately 4.8 GHz to 7.2 GHz. Frequency synthesizers are typically implemented with a clock multiplier unit (CMU) that includes a phase lock loop (PLL). The key component of the phase lock loop is the voltage-controlled oscillator, which outputs a clock whose frequency is adjustable and controlled in a closed-loop state, so that the frequency of the clock can be precisely determined. For a voltage-controlled oscillator, the wider its adjustable range, the more difficult the design.

[0003] For example, U.S. Patent No. 10,404,316 discloses a zero-IF WLAN radio transceiver that utilizes a frequency synthesizer that requires a voltage-controlled oscillator with an adjustable range from 7.68 GHz to 9.60 GHz.

[0004] Therefore, there is a need for a frequency synthesizer that reduces the requirement for the adjustable range of the voltage-controlled oscillator but can still meet the frequency range required by a zero-IF WLAN radio transceiver. Summary of the Invention

[0005] An embodiment of the present invention provides a frequency synthesizer, comprising: a clock multiplier unit for receiving a first clock and outputting a second clock according to a multiple; a 1 / 3 frequency divider circuit for receiving the second clock and outputting a third clock; a first 1 / 2 frequency divider circuit for receiving the second clock and outputting a fourth clock; a second 1 / 2 frequency divider circuit for receiving the fourth clock and outputting a fifth clock; a first multiplexer for receiving the third clock and the fourth clock and outputting a seventh clock according to a first selection signal; a second multiplexer for receiving the third clock and the fifth clock and outputting an eighth clock according to a second selection signal; and a mixer for receiving the seventh clock and the eighth clock and outputting an output clock.

[0006] Another embodiment of the present invention provides a frequency synthesis method, comprising: receiving a first clock; using a clock multiplier unit to multiply the first clock by a multiple to obtain a second clock; using a 1 / 3 frequency divider circuit to divide the second clock into a third clock; using a first 1 / 2 frequency divider circuit to divide the second clock into a fourth clock; using a second 1 / 2 frequency divider circuit to divide the fourth clock into a fifth clock; using a first multiplexer to select between the third clock and the fourth clock according to a first selection signal to output a seventh clock; using a second multiplexer to select from multiple clocks including the third clock and the fifth clock according to a second selection signal to output an eighth clock; and generating an output clock by mixing the seventh clock and the eighth clock using a mixer. Description of the Drawings

[0007] Figure 1 A functional block diagram showing a frequency synthesizer according to an embodiment of the present disclosure;

[0008] Figure 2 A schematic diagram showing a 1 / 2 frequency divider circuit;

[0009] Figure 3 A schematic diagram showing a 1 / 3 frequency divider circuit; and

[0010] Figure 4 A flowchart showing a frequency synthesis method according to an embodiment of the present disclosure.

[0011] Symbol Description

[0012] 100: Frequency synthesizer

[0013] 110: Crystal oscillator (“XO”)

[0014] 120: Clock multiplier unit (“CMU”)

[0015] 130: 1 / 3 frequency divider circuit (“1 / 3”)

[0016] 140, 150, 160: One-to-two frequency divider circuit (“1 / 2”)

[0017] 170: Two-to-one multiplexer (“2:1 mux”)

[0018] 180: Three-to-one multiplexer (“3:1 mux”)

[0019] 190: Mixer (“mixer”)

[0020] 200: One-to-two frequency divider circuit

[0021] 210: Data flip-flop

[0022] 300: One-to-three frequency divider circuit

[0023] 310, 320, 330: Data flip-flop

[0024] 340, 350: NAND gate

[0025] 400: Flowchart

[0026] 410, 420, 430, 440, 450, 470, 480, 490: Steps Detailed implementation manners

[0027] This disclosure relates to a frequency synthesizer. Although the specification describes several exemplary embodiments of implementing the present invention in this disclosure, it should be understood that the present invention can be implemented in various ways and is not limited to the specific examples described below or any specific manner of implementing the features of these examples. In other cases, well-known details are not shown or described in order to focus on discussing various aspects of this disclosure.

[0028] Those skilled in the art of this technical field understand the terms and basic concepts related to microelectronics used in this disclosure, such as “voltage”, “signal”, “clock”, “frequency”, “phase-locked loop”, “data flip flop”, “edge trigger”, “NAND Gate”, “mixer”, “logic signal”, “ternary signal”, “quadrature clock”, “multiplexer” and “clock multiplier unit (CMU)”. Such terms are used in the field of microelectronics, and the related concepts are obvious to those skilled in this technical field, so they will not be described in detail here.

[0029] Those skilled in the art can read a schematic diagram of a circuit containing components such as data flip - flops and NAND gates, and do not require a detailed description of how one component is connected to another in the schematic diagram. Those skilled in the art also understand units such as giga - Hertz (GHz), and do not require further explanation.

[0030] A circuit is a collection of transistors, capacitors, resistors, and / or other electronic devices interconnected in some way to achieve a certain function.

[0031] A so - called signal refers to a voltage with a variable level, whose level carries a certain information and changes over time. The level of a signal at a certain moment represents the state of the signal at that moment.

[0032] A logic signal is a voltage signal with two states: a low - level state and a high - level state. The low - level state is also called the "0" state, and the high - level state is also called the "1" state. Regarding the logic signal Q, when people say "Q is at a high level" or "Q is at a low level", it means "Q is in the high - level state" or "Q is in the low - level state". Similarly, when people say "Q is 1" or "Q is 0", it means "Q is in the state of 1" or "Q is in the state of 0".

[0033] When a logic signal switches from a low level to a high level, a rising edge appears. When a logic signal switches from a high level to a low level, a falling edge appears.

[0034] If the first logic signal and the second logic signal are always in opposite states, the first logic signal is said to be the inverse or inverse logic of the second logic signal. That is, when the first logic signal is 1, the second logic signal is 0; when the first logic signal is 0, the second logic signal is 1. When the first logic signal is the inverse logic of the second logic signal, it means that the first logic signal is complementary to the second logic signal.

[0035] A three - state signal is a composite signal with three states that can be represented by two logic signals.

[0036] A clock is a logic signal that periodically switches back and forth between a low level and a high level. When the clock switches from a low level to a high level, and then from a high level to a low level, one cycle is completed. The frequency of the clock represents the number of cycles the clock completes in one second.

[0037] A data flip-flop (DFF) receives an input signal on a data pin labeled "D", and outputs an output signal on an output pin labeled "Q" and a complementary output signal on a complementary output pin labeled "QB" according to a trigger signal on a trigger pin marked with a wedge symbol. The input signal, output signal, complementary output signal, and trigger signal are all logic signals. For a positive (negative) edge-triggered data flip-flop, at the rising (falling) edge of the trigger signal, it loads the state of the input signal into the output signal and loads the opposite state of the input signal into the complementary output signal. The default setting of the data flip-flop is positive edge-triggered. When the data flip-flop is negative edge-triggered, a small circle is placed on the trigger pin to indicate the logical inversion of the trigger signal.

[0038] A multiplexer receives a number of inputs and selects one of them to produce an output according to a selection signal. The selection signal has a number of states, each corresponding to one of the inputs. A two-to-one multiplexer receives two inputs and produces an output according to a selection signal. The selection signal is a logic signal and has two states, each corresponding to one of the two inputs. A three-to-one multiplexer receives three inputs and produces an output according to a selection signal. The selection signal is a ternary signal and has three states, each corresponding to one of the three inputs.

[0039] Figure 1Functional block diagram of a frequency synthesizer 100 showing an embodiment of the present disclosure. The frequency synthesizer 100 includes a clock multiplier unit (denoted as "CMU") 120, a 1 / 3 frequency divider circuit (denoted as "1 / 3") 130, a first 1 / 2 frequency divider circuit (denoted as "1 / 2") 140, a second 1 / 2 frequency divider circuit (denoted as "1 / 2") 150, a third 1 / 2 frequency divider circuit (denoted as "1 / 2") 160, a 2:1 multiplexer (denoted as "2:1 mux") 170, a 3:1 multiplexer (denoted as "3:1 mux") 180, and a mixer (denoted as "mixer") 190. The clock multiplier unit 120 is used to receive a first clock x1 and output a second clock x2 according to a multiplication factor N. For example (but not limited thereto), the first clock x1 is generated by a crystal oscillator (denoted as "XO") 110. The 1 / 3 frequency divider circuit 130 is used to receive the second clock x2 and output a third clock x3. The first 1 / 2 frequency divider circuit 140 is used to receive the second clock x2 and output a fourth clock x4. The second 1 / 2 frequency divider circuit 150 is used to receive the fourth clock x4 and output a fifth clock x5. The third 1 / 2 frequency divider circuit 160 is used to receive the fifth clock x5 and output a sixth clock x6. The 2:1 multiplexer 170 is used to receive the third clock x3 and the fourth clock x4, and output a seventh clock x7 according to a first selection signal S1. The 3:1 multiplexer 180 is used to receive the third clock x3, the fifth clock x5, and the sixth clock x6, and output an eighth clock x8 according to a second selection signal S2. The mixer 190 is used to receive the seventh clock x7 and the eighth clock x8, and output a ninth clock x9. The ninth clock x9 is the output of the frequency synthesizer 100. In some embodiments (by way of example and not limitation), the purpose of the frequency synthesizer 100 is to make the ninth clock x9 adjustable (covering a frequency range from 4.80 GHz to 7.2 GHz) without the clock multiplier unit 120 having a wide adjustable frequency range.

[0040] A 1 / 2 frequency divider circuit (such as the 1 / 2 frequency divider circuits 140, 150, and 160) receives an input clock and outputs an output clock such that the frequency of the output clock is equal to half of the frequency of the input clock. Figure 2A schematic diagram showing an example of a 1:2 frequency divider circuit. The 1:2 frequency divider circuit 200 can be used to implement the 1:2 frequency divider circuits 140, 150, and 160. The 1:2 frequency divider circuit 200 includes a data flip-flop 210, which has a data pin (labeled "D"), an output pin (labeled "Q"), a complementary output pin (labeled "QB"), and a trigger pin (marked with a wedge symbol). The data flip-flop 210 is configured in a negative feedback manner to output an output clock according to the trigger of the input clock. The symbols, functions, principles, and circuit implementation methods of the 1:2 frequency divider circuit 200 and data flip-flops (such as the data flip-flop 210) are well known to those skilled in the art, so they will not be described in detail here.

[0041] A 1:3 frequency divider circuit (such as the 1:3 frequency divider circuit 130) receives an input clock and outputs an output clock such that the frequency of the output clock is equal to one-third of the frequency of the input clock. Figure 3 A schematic diagram showing an example of a 1:3 frequency divider circuit. The 1:3 frequency divider circuit 300 can be used to implement the 1:3 frequency divider circuit 130. The 1:3 frequency divider circuit 300 includes three data flip-flops 310, 320, and 330, and NAND gates 340 and 350. The data flip-flop 310, the data flip-flop 320, and the NAND gate 340 implement the function of dividing by three, which is well known in the prior art, so it will not be described in detail here. The data flip-flop 330 and the NAND gate 350 are used to make the output clock have a 50% duty cycle (not necessary but helpful). These are well known in the prior art, so they will not be described in detail here. It should be noted that the data flip-flop 330 is negative-edge triggered (as indicated by the small circle on the trigger pin, indicating logical inversion), while the data flip-flops 310 and 320 are positive-edge triggered.

[0042] Let the frequencies of the clocks x1, x2, x3, x4, x5, x6, x7, x8, and x9 be f1, f2, f3, f4, f5, f6, f7, f8, and f9 respectively. x1 is output by the crystal oscillator 110, and its frequency f1 has high accuracy and stability. Crystal oscillators are well known in the prior art, so they will not be described in detail here. The clock multiplier unit 120 is used to make the frequency of x2 equal to the frequency of x1 multiplied by the multiple N, that is

[0043] f2 = N·f1 (1)

[0044] In one embodiment, the multiple N is a number with an integer part and a fractional part. In one embodiment, the clock multiplier unit 120 is a fractional-N phase-locked loop (fractional-N PLL), which includes a voltage-controlled oscillator for generating the second clock x2. The second clock x2 is controlled in a closed-loop manner to track the phase of the first clock x1. Fractional-N phase-locked loops are well known in the prior art and will not be described in detail here. Examples of fractional-N phase-locked loops can be found in U.S. Patent No. 7,498,856.

[0045] A 1:3 frequency divider circuit 130 is used to make the frequency of x3 equal to one-third of the frequency of x2, i.e.,

[0046] f3 = f2 / 3 (2)

[0047] A first 1:2 frequency divider circuit 140 is used to make the frequency of x4 equal to half of the frequency of x2, i.e.,

[0048] f4 = f2 / 2 (3)

[0049] A second 1:2 frequency divider circuit 150 is used to make the frequency of x5 equal to half of the frequency of x4, i.e.,

[0050] f5 = f4 / 2 (4)

[0051] A third 1:2 frequency divider circuit 160 is used to make the frequency of x6 equal to half of the frequency of x5, i.e.,

[0052] f6 = f5 / 2 (5)

[0053] A 2-to-1 multiplexer 170 performs a clock selection function; the first selection signal S1 is a logic signal (possible states are 0 or 1). When S1 is 0, x3 is selected; when S1 is 1, x4 is selected. That is:

[0054]

[0055] 2-to-1 multiplexers are well known in the prior art and will not be described in detail here. There are many implementation methods known in the prior art, and those skilled in the art can choose by themselves.

[0056] A 3-to-1 multiplexer 180 performs a clock selection function; the second selection signal S2 is a ternary signal (possible states are 0, 1, or 2). When S2 is 0, x3 is selected; when S2 is 1, x5 is selected; when S2 is 2, x6 is selected. That is:

[0057]

[0058] Three-to-one multiplexers are well known in the prior art and will not be described in detail here. There are many implementation methods known in the prior art, and those skilled in the art of this technology can choose by themselves.

[0059] The mixer 190 performs frequency mixing of x7 and x8 such that the frequency of x9 is equal to the sum of the frequencies of x7 and x8, that is:

[0060] f9 = f7 + f8 (8)

[0061] Based on equations (2), (3), (4), (5), (6), (7), and (8), the relationship between f2 and f9 can be established according to the states of S1 and S2 as shown in the following table:

[0062]

[0063] Therefore, the range of f9 is very wide: it can be as low as 11f2 / 24 and as high as 5f2 / 6.

[0064] Mixers are well known in the prior art and will not be described in detail here. There are many implementation manners known in the prior art, and those skilled in the art of this technology can choose by themselves to implement the mixer 190. In one embodiment, the mixer 190 includes a resonant tank, and the resonant tank is tuned to the desired frequency x9 to suppress unwanted mixing products. This concept and implementation manners are well known in the prior art and will not be described in detail here. In one embodiment, the mixer 190 is a single-sideband (SSB) mixer, and x3, x4, x5, x6, x7, and x8 are all quadrature clocks. "Single-sideband mixer" and "quadrature clock" are well known to those skilled in the art of this technology and will not be described in detail here. An implementation manner of a single-sideband mixer can be found in U.S. Patent 10,250,189, which is also an example of using a resonant tank to suppress unwanted mixing products. In one embodiment, the quadrature clock generator disclosed in U.S. Patent 10,613,575 is used to implement the one-to-two frequency dividers 140, 150, and 160; in this case, x4, x5, and x6 are quadrature clocks. In one embodiment, the quadrature clock generator disclosed in U.S. Patent 10,469,061 is integrated into the one-to-three frequency divider 130 such that x3 can be a quadrature clock.

[0065] In one embodiment (by way of example and not limitation): The frequency synthesizer 100 is used in a zero-IF wireless local area network radio transceiver, in which a clock with a frequency range of 4.80 GHz to 7.20 GHz is required; f1 is 40 MHz; the multiple N is between 192 and 216; f2 is between 7.680 GHz and 8.640 GHz; f9 is between 4.80 GHz and 7.20 GHz; and the states of S1 and S2 are listed in the following table:

[0066] <![CDATA[f9(GHz)]]> <![CDATA[f2(GHz)]]> <![CDATA[S1]]> <![CDATA[f7(GHz)]]> <![CDATA[S2]]> <![CDATA[f8(GHz)]]> 4.80～5.12 7.680～8.192 1 3.840～4.096 2 0.960～1.024 5.12～5.76 7.680～8.640 0 2.560～2.880 0 2.560～2.880 5.76～6.48 7.680～8.640 1 3.840～4.320 1 1.920～2.160 6.48～7.20 7.776～8.640 1 3.888～4.320 0 2.592～2.880

[0067] That is to say, by appropriately setting the states of S1 and S2, f9 can cover the range from 4.80 GHz to 7.20 GHz, while the range of f2 is from 7.680 GHz to 8.640 GHz. This means that when the clock multiplier unit 120 is implemented by a fractional-N phase-locked loop including a voltage-controlled oscillator, the required adjustable range of the voltage-controlled oscillator is from 7.680 GHz to 8.640 GHz. In this way, compared with the disclosure of U.S. Patent 10,404,316, the present invention greatly reduces the requirement for the adjustable range of the voltage-controlled oscillator.

[0068] Note that some radio transceivers may not require the frequency range between 4.80 GHz and 5.12 GHz (of f9). In this case, the sixth clock x6 and the state of S2 = 2 are not required, so the frequency synthesizer 100 can be simplified by removing the third 1:2 frequency divider circuit 160, and since the sixth clock x6 can be removed from the original options, the three-to-one multiplexer 180 can be simplified to a two-to-one multiplexer, and the second selection signal S2 becomes a logic signal. In other words, the third 1:2 frequency divider circuit 160 can be optionally included depending on whether the frequency range between 4.80 GHz and 5.12 GHz is required.

[0069] As Figure 4As shown in the flowchart 400, a frequency synthesis method includes the following steps: (step 410) receiving a first clock; (step 420) using a clock multiplier unit to multiply the first clock by a multiple to obtain a second clock; (step 430) using a 1:3 frequency divider circuit to divide the second clock to obtain a third clock; (step 440) using a first 1:2 frequency divider circuit to divide the second clock to obtain a fourth clock; (step 450) using a second 1:2 frequency divider circuit to divide the fourth clock to obtain a fifth clock; (step 470) outputting a seventh clock by selecting between the third clock and the fourth clock according to a first selection signal using a first multiplexer; (step 480) outputting an eighth clock by selecting from multiple clocks (including the third clock and the fifth clock) according to a second selection signal using a second multiplexer; (step 490) generating an output clock by mixing the seventh clock and the eighth clock using a mixer.

[0070] Those skilled in the art will readily observe that various modifications and changes can be made to the apparatus and method while maintaining the teachings of the present disclosure. Therefore, the above disclosure should not be construed as being limited only by the boundaries of the claims.

Claims

1. A frequency synthesizer comprising: a clock multiplier unit, configured to receive a first clock and output a second clock according to a multiplier; a 1:3 frequency division circuit, configured to receive the second clock and output a third clock; a first one-to-two frequency dividing circuit, configured to receive the second clock and output a fourth clock; a second one-to-two frequency dividing circuit, configured to receive the fourth clock and output a fifth clock; a first multiplexer, configured to receive the third clock and the fourth clock, and output a seventh clock according to a first selection signal; a second multiplexer, configured to receive the third clock and the fifth clock, and output an eighth clock according to a second selection signal; as well as A mixer is used for receiving the seventh clock and the eighth clock and outputting an output clock.

2. The frequency synthesizer of claim 1 , wherein the multiple includes an integer part and a fractional part, the clock multiplier unit includes a fractional-N phase-locked loop (PLL), the fractional-N PLL including a voltage-controlled oscillator (VCO) for generating the second clock, and the second clock is controlled in a closed-loop manner to track a phase of the first clock.

3. The frequency synthesizer of claim 1, wherein the first selection signal is a logic signal, and the first multiplexer is a two-to-one multiplexer.

4. The frequency synthesizer of claim 1, wherein the second selection signal is a logic signal, and the second multiplexer is a two-to-one multiplexer.

5. The frequency synthesizer of claim 1, wherein the mixer comprises a resonant circuit tuned to a specified frequency of the output clock.

6. The frequency synthesizer of claim 1, wherein the mixer is a single sideband mixer. 7 . The frequency synthesizer as claimed in claim 6 , wherein the third clock, the fourth clock, the fifth clock, the seventh clock, and the eighth clock are all four-phase clocks.

8. The frequency synthesizer as claimed in claim 1, further comprising a third one-to-two frequency divider circuit for receiving the fifth clock and outputting a sixth clock.

9. The frequency synthesizer of claim 8, wherein the second selection signal is a tri-state signal, the second multiplexer is a three-to-one multiplexer, and the eighth clock is selected from the third clock, the fifth clock, and the sixth clock.

10. A frequency synthesis method, comprising: receiving a first clock; multiplying the first clock into a second clock using a clock multiplier unit according to a multiple; Divide the second clock into a third clock using a 1:3 frequency division circuit; Using a first one-to-two frequency dividing circuit to divide the second clock into a fourth clock; Using a second one-to-two frequency dividing circuit to divide the fourth clock into a fifth clock; Using a first multiplexer to select between the third clock and the fourth clock according to a first selection signal to output a seventh clock; using a second multiplexer to select a plurality of clocks including the third clock and the fifth clock according to a second selection signal to output an eighth clock; as well as An output clock is generated by mixing the seventh clock and the eighth clock using a mixer.

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