A CRC parallel computation method

Abstract

The application relates to a CRC parallel computing method and belongs to the field of data processing. The application fills 0 in non-packet bytes of a message starting word and an ending word; 256-bit input data are divided into 8 lanes, each lane containing 32 bits; recursion of a state register is carried out by using an LFSR circuit, 8 state registers are obtained, the state registers are subjected to XOR operation to obtain a combined state register, the value of the combined state register is subjected to state rollback, and the state register after rollback is the final CRC check value. The application reduces the complexity of CRC state register associated logic by splitting a state transition matrix, and improves circuit timing characteristics; the application eliminates the influence of redundant 0 at the tail of a message on the state register in large-bit-width parallel time through state rollback logic.

Description

TECHNICAL FIELD

[0001] The present application belongs to the field of data processing, and particularly relates to a CRC parallel computation method. BACKGROUND

[0002] CRC (cyclic redundancy check) is a commonly used data error detection and correction code. Its basic encoding principle is as follows.

[0003] Suppose that the data to be encoded is W=[w0, w1, w2, w3...wk-1], with a total of k bits. The CRC generating polynomial is G=[g0, g1, g2...gr-1], with a total of r bits.

[0004] The bit sequence in this paper follows the Ethernet order, that is, w0 is transmitted first, and in the subsequent derivation and calculation, it corresponds to the highest priority. Therefore, in the GF(2) domain, W=w(0)x k-1 +w(1)x k-2 +w(2)x k-3 +...+ w(k-1)x 0 After merging, W can be represented as

[0005] Similarly, the generating polynomial G can be represented in the GF(2) domain as In this paper, the bit sequence weight of the information sequence and the generating polynomial is opposite.

[0006] The CRC check in the GF(2) domain can be represented by the following formula:

[0007] R(x)=M(x)x r mod G(x) Formula 1

[0008] The check code R(x) is the result of taking the modulus of G(x) in the GF(2) domain after adding r zeros to the information M(x), and the final transmitted information is S(x)=M(x)x r +R(x). Error discovery can be achieved at the receiving end by calculating whether S(x) mod G(x) is all 0. In addition, if the original information length k is a fixed value, error correction can also be achieved by checking S(x) mod G(x). The specific error correction capability is related to the generating polynomial k length, etc.

[0009] As can be seen above, CRC computation is essentially a modulus (division) in the GF(2) domain. At the circuit level, division can be equivalent to LFSR, and its circuit structure is as follows: Figure 1 :

[0010] The above circuit can realize serial CRC calculation, and after the data W is moved into the LFSR bit by bit, the data in R[0, 1, 2..r-1] is the final check code R(x) coefficient at this time.

[0011] There are various implementation schemes of CRC to adapt to different application scenarios.

[0012] 1. Serial method

[0013] The serial method directly uses the CRC definition, obtains the input data bit by bit, and calculates the GF(2) domain remainder according to the bit value and the current remainder value until all data are involved in the calculation. The serial method is easy to understand, and the circuit is simple, and is used more in low-speed occasions. However, the bit-by-bit calculation mode is low in efficiency, and cannot meet the high-speed calculation occasion.

[0014] 2. Table lookup method

[0015] The table lookup method can process multiple input bits at a time by using pre-computed table entries, but the table entry size is the power size of the number of bits processed at a time, for example, a 256-size table entry can process 8-bit data at a time, and a 56636-size table entry can process 16-bit data at a time. With the improvement of processing performance, the table entry size will increase exponentially. Usually, this method uses a 256-size table entry, that is, 8-bit data is processed at a time. This method is also not suitable for occasions with very high calculation speed requirements.

[0016] 3. Direct parallel method

[0017] In the design based on FPGA or ASIC, the table entry storage in the calculation can be replaced by circuit logic calculation to realize larger-scale parallelism. However, the increase of logic complexity caused by the increase of parallel scale greatly limits the upper limit of the circuit clock frequency. Usually, more than 64-bit parallel calculation in FPGA will face a great timing challenge. SUMMARY

[0018] (1) Technical problem to be solved

[0019] The technical problem to be solved by the present application is how to provide a CRC parallel calculation method to solve the problems that the serial method of CRC cannot meet the high-speed calculation occasion, the table lookup method is not suitable for occasions with very high calculation speed requirements, and the direct parallel method faces a great timing challenge in parallel calculation.

[0020] (2) Technical scheme

[0021] In order to solve the above technical problems, the present application provides a CRC parallel calculation method, which comprises the following steps:

[0022] Input multiple words, each of which is 256-bit data, divide the 256-bit input data into 8 lanes, each of which contains 32 bits, marked as

[0023] D l0 [31..0] = W[31..0]

[0024] D l1 [31..0] = W[63..32]

[0025] D l2 [31..0] = W[95..64]

[0026] D l3 [31..0] = W[127..96]

[0027] D l4 [31..0] = W[159..128]

[0028] D l5 [31..0] = W[191..160]

[0029] D l6 [31..0] = W[223..192]

[0030] D l7 [31..0] = W[255..224]

[0031] The recursive formula of the state register of each lane is:

[0032]

[0033] Wherein, k is the lane number range 0, …, 7, is an r x r state transition matrix, is an r x 1 generating polynomial coefficient matrix, is an r x 1 register state matrix, r is the order of the CRC, n represents the nth, D lk [i] is the data of the kth lane;

[0034]

[0035]

[0036]

[0037] Wherein, E (r-1) is an r-1 order unit matrix, g is a polynomial coefficient;

[0038] After the last word computation is completed, 8 state registers are obtained, and the state registers are XORed to obtain a merged state register; the value of the merged state register is the CRC value corresponding to the input data.

[0039] Further, the maximum number of associations of each bit of each lane state register is not more than 64.

[0040] Further, the maximum number of associations is 42 when the polynomial is CRC32.

[0041] Further, z represents the z-th power of M, and for circuit operation, it represents a state transition matrix of shifting z bits.

[0042] Further, the XOR operation of the state register corresponds to GF2 field addition.

[0043] Further, the input data is an Ethernet network message.

[0044] Further, before the 256-bit input data is divided into 8 lanes, it also includes: filling 0 in the non-message bytes of the start word and the end word of the message, and recording the number p of 0 filled in the end word.

[0045] Further, after the state registers are XORed to obtain the merged state register, it also includes: the value of the merged state register is the CRC value corresponding to the data with the tail 0 filled, the state rollback is performed according to the number p of 0 filled in the end word through formula 7, and the state register after the rollback is the final CRC check value.

[0046] wherein,

[0047]

[0048] is an r x r matrix.

[0049] Further, the state rollback is calculated by

[0050] Further, the state rollback circuit is only related to the state register, and the maximum number of associations is 32.

[0051] ​The application provides a CRC parallel calculation method, the application reduces the complexity of CRC state register associated logic by splitting the state transition matrix, and improves the circuit timing characteristics; the application eliminates the influence of redundant 0 at the tail of the message on the state register through state rollback logic. Through verification of the author on the xilinx Kintex7325t-2 chip, when the bit width of the data stream is 256 bits, the clock frequency can reach 250Mhz, and the data throughput reaches 64Gbps; when the xilinxvu13p-2 chip clock frequency reaches 400Mhz, the data throughput reaches 100Gbps. BRIEF DESCRIPTION OF DRAWINGS

[0052] Figure 1 is a schematic diagram of an LFSR circuit;

[0053] Figure 2 is a schematic diagram of a network message stream interface data of the application;

[0054] Figure 3 is a schematic diagram of 256bit input data processing of the application;

[0055] Figure 4 is a schematic diagram of original data being divided into 8 data of the application;

[0056] Figure 5 is a schematic diagram of the overall processing flowchart of the application. DETAILED DESCRIPTION

[0057] In order to make the purpose, content and advantages of the application more clear, the specific embodiments of the application are further described in detail below in combination with the drawings and examples.

[0058] The application splits the traditional parallel CRC scheme based on the associativity of modular operation, so as to reduce the logic complexity and improve the circuit timing.

[0059] The principle of the application is as follows:

[0060] The application scheme depends on the matrix representation of parallel CRC calculation, which is briefly listed as follows:

[0061] State recursion

[0062] Analysis Figure 1 The LFSR circuit can be known,

[0063] R is regarded as the circuit state, then the state at the next time only depends on the current state of the circuit and the current input data, and the analysis circuit can be known

[0064]

[0065] Each variable in the formula is a matrix, and the specific form is as follows:

[0066] is an rx1 matrix

[0067] is an rxr matrix

[0068] W[n] is a scalar, representing the nth input bit

[0069] is an rx1 matrix.

[0070] Multi-stage recursion

[0071] Through

[0072] After recursion t, the following can be obtained:

[0073]

[0074] The above formula can further write the input data W as a matrix as follows

[0075]

[0076] Wherein is an rxr matrix, is an rxt matrix, is a tx1 vector

[0077] State rollback

[0078] In formula 2, the value in the LFSR register is only passed to the next stage through When the input W[n] is 0

[0079] Matrix is a full rank matrix, and there is an inverse matrix So that

[0080] Through calculation

[0081]

[0082] is an rxr matrix. Through The state rollback of the CRC can be calculated.

[0083] Based on the above mathematical basis, the following implementation scheme is provided.

[0084] This paper mainly aims at the network message stream interface for real-time CRC calculation. In high-speed network interface, the interface data bit width can reach hundreds of bits, and the clock rate is hundreds of Mhz. This paper takes 256-bit data interface as an example for analysis, and the analysis and calculation of other bit width interfaces are similar. The network message stream interface data is as follows Figure 2 :

[0085] The specific implementation steps are as follows:

[0086] Step S1: input message padding

[0087] 1 word is 256 bits, since the network message length of Ethernet and other networks is an integer number of byte data, but the number of bytes is uncertain, so the start position and end position in the 256-bit word exist 256 / 8=32 possibilities, in order to facilitate calculation, we fill 0 in the non-message bytes of the start word and the end word, and record the number of 0 filled in the end word p. The target of filling 0 is 256-bit alignment. According to the principle of CRC algorithm, the 0 filled before the start byte does not affect the calculation result; the 0 filled after the end byte will push the CRC register to continue to rotate, thereby affecting the final calculation value, but we can use the state rollback matrix mentioned above to rollback the CRC register value, and eliminate the influence of subsequent 0 filling. For example Figure 2 .

[0088] Step S2: message splitting and sub-state iteration calculation

[0089] Since the CRC operation is essentially a modulo operation in the GF(2) field, according to the additive law, the data participating in the CRC operation can be additively split, and the state registers obtained by calculating the CRC of each split data are summed to obtain the CRC value of the original data.

[0090] Through reasonable splitting, the number of associated data of the state register in the beat-by-beat recursion can be reduced, thereby reducing the logic complexity and improving the circuit timing.

[0091] Input multiple words, each word is 256-bit data, the present application divides the 256-bit input data into 8 lanes, each lane contains 32 bits, as follows Figure 3 :

[0092] The input data is segmented according to the lane, so the original data is segmented into 8 data as follows Figure 4 :

[0093] After splitting, 8 lanes are obtained, each lane has 32-bit data marked as

[0094] D l0[31..0] = W[31..0]

[0095] D l1 [31..0] = W[63..32]

[0096] D l2 [31..0] = W[95..64]

[0097] D l3 [31..0] = W[127..96]

[0098] D l4 [31..0] = W[159..128]

[0099] D l5 [31..0] = W[191..160]

[0100] D l6 [31..0] = W[223..192]

[0101] D l7 [31..0] = W[255..224]

[0102] The above data is substituted into Equation 5 to obtain the recursive formula of each lane status register

[0103]

[0104] k is the lane number ranging from 0..7, is an r x r state transition matrix, is an r x 1 generating polynomial coefficient matrix, is an r x 1 register state matrix, r is the order of the CRC, n represents the nth shot, D lk [i] is the data of the kth lane; represents the zth power of M, for circuit operation, it represents the state transition matrix shifted by z bits.

[0105]

[0106]

[0107]

[0108] wherein E(r-1) is an r-1 order unit matrix, g is a polynomial coefficient;

[0109] As can be seen from the above formula, the maximum number of associations for each bit in each lane status register does not exceed 64 (number of status registers + lane width). Calculations show that the maximum number of associations is 42 when the polynomial is 802.3CRC32, which is comparable to the maximum number of associations of 34 when directly calculating CRC in parallel with 32 bits, and is a significant reduction compared to 157 when directly calculating with 256 bits of data.

[0110] Table 1. Number of 802.3 CRC32 associations computed in parallel with different bit widths.

[0111]

[0112]

[0113] Step S3: Sub-state merging and state rollback

[0114] After the last word is calculated, the algorithm obtains 8 status registers. After performing an XOR operation (GF2 field addition) on the status registers, a merged status register is obtained. The value of the merged status register is the CRC value of the corresponding input data.

[0115] In the case where zeros are padded after the end byte, the value of the merged status register is the CRC value corresponding to the data padded with zeros at the end. The status needs to be rolled back according to the number of zeros p p added to the end word using Formula 7. The rolled-back status register is the final CRC check value.

[0116] in,

[0117]

[0118] It is an r×r matrix; through Calculate the CRC status rollback.

[0119] The state rollback circuit is only related to the state register, and its maximum number of associations is 32. Its circuit complexity is comparable to that of calculating the state register, and it will not be a critical path in terms of timing.

[0120] The overall processing flow of this invention is as follows: Figure 5 :

[0121] This invention reduces the complexity of the CRC status register association logic by splitting the state transition matrix, thereby improving the circuit timing characteristics. Furthermore, this invention eliminates the impact of trailing redundant zeros on the status register during large-bit-width parallel processing through state rollback logic. Verification by the authors on the Xilinx Kintex7325t-2 chip showed that a 256-bit data stream clock frequency of 250MHz and a data throughput of 64Gbps were achieved; on the Xilinx VU13P-2 chip, a clock frequency of 400MHz and a data throughput of 100Gbps were achieved.

[0122] The above description is only a preferred embodiment of the present invention. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the technical principles of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A CRC parallel computation method, characterized by, The method comprises: Inputting a plurality of words, each word being 256-bit data, dividing the 256-bit input data into 8 lanes, each lane containing 32 bits, and marking the 8 lanes as D l0 [31..0] = W[31..0] D l1 [31..0] = W[63..32] D l2 [31..0] = W[95..64] D l3 [31..0] = W[127..96] D l4 [31..0] = W[159..128] D l5 [31..0] = W[191..160] D l6 [31..0] = W[223..192] D l7 [31..0] = W[255..224] The recursive formula of the state register of each lane is: where k is a lane number ranging from 0,..., 7, is an r x r state transition matrix, is an r x 1 generator polynomial coefficient matrix, is an r x 1 register state matrix, r is the order of the CRC, n denotes the nth beat, D lk [i] is the data of the kth lane; Wherein, E(r-1) is r-1 order unit matrix, g is polynomial coefficient; Indicates the z power of M, for circuit operation, indicates the state transition matrix of shifting z bits. After the calculation of the last word is completed, 8 state registers are obtained, the state registers are subjected to an XOR operation, and a merged state register is obtained; the value of the merged state register is the CRC value corresponding to the input data.

2. The CRC parallel computation method of claim 1, wherein, The maximum association number of each bit of each lane state register is not more than 64.

3. The CRC parallel computation method of claim 1, wherein, When the polynomial is CRC32, the maximum association number is 42.

4. The CRC parallel computation method of claim 1, wherein, The XOR operation of the state register corresponds to GF2 field addition.

5. The CRC parallel computation method of any one of claims 1-4, wherein, The input data is an Ethernet network message.

6. The CRC parallel computation method of claim 5, wherein, Before the 256-bit input data is divided into 8 lanes, it also includes: filling 0 in the non-message bytes of the start word and the end word of the message, and recording the number p of 0 filled in the end word.

7. The CRC parallel computation method of claim 6, wherein, After the state register is subjected to an XOR operation to obtain the merged state register, it also includes: the value of the merged state register is the CRC value corresponding to the data with the tail part filled with 0, the state is rolled back according to the number p of 0 filled in the end word through formula 7, and the rolled-back state register is the final CRC check value; Wherein, is an r x r matrix.

8. The CRC parallel computation method of claim 7, wherein, By Compute CRC state rollbacks.

9. The CRC parallel computation method of claim 7, wherein, The state rollback circuit is only related to the state register, and the maximum association number thereof is 32.

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