Silicon carbide semiconductor device and method for manufacturing the same

Abstract

The present disclosure aims to provide a silicon carbide semiconductor device with excellent productivity and which suppresses degradation of characteristics when a large current flows through a body diode. A structure comprising a SiC substrate (10), a buffer layer (11), and a drift layer (12) is divided into an active region (13) through which current flows when a voltage is applied to a SiC-MOSFET (101) and a withstand voltage holding region (14) located on the outer periphery of the active region (13) when viewed from above. The active region (13) is divided into a first active region (15) in the center and a second active region (16) between the first active region (15) and the withstand voltage holding region (14) when viewed from above. The lifetime of minority carriers in the second active region (16) and the withstand voltage holding region (14) is shorter than the lifetime of minority carriers in the first active region (15).

Description

Technical Field

[0001] The present disclosure relates to a silicon carbide semiconductor device. Background Art

[0002] It is known that when a forward current, or bipolar current, continues to flow through a pn diode made of silicon carbide (SiC), stacking faults form in the crystal, causing a shift in forward voltage and causing a reliability issue. This is believed to be caused by the recombination energy of minority carriers injected through the pn diode and majority carriers, which propagate stacking faults as surface defects, starting from basal plane dislocations and other structures in the silicon carbide substrate. These stacking faults obstruct the flow of current, resulting in a decrease in current flow and an increase in forward voltage, which in turn reduces the reliability of the semiconductor device.

[0003] This increase in forward voltage also occurs in vertical MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) using silicon carbide. Vertical MOSFETs have a parasitic pn diode (body diode) between the source and drain. When forward current flows through this body diode, the same reliability degradation occurs in vertical MOSFETs as with pn diodes. Using the SiC MOSFET's body diode as a return diode can sometimes degrade MOSFET characteristics.

[0004] As a method for solving the reliability problem caused by the forward current flowing into the parasitic pn diode as described above, there are the following three methods. The first method is a method of converting the basal plane dislocation transferred from the SiC substrate to the epitaxial growth layer into a through-edge dislocation to prevent the expansion of the stacking fault (for example, refer to non-patent document 1). The second method is a method of preventing the occurrence of stacking faults from the basal plane dislocation existing in the SiC substrate by forming a buffer layer with a high impurity concentration on the SiC substrate and promoting the recombination of holes and electrons in the buffer layer (for example, refer to non-patent document 2). The third method is a method of introducing a recombination center into the region of the parasitic pn diode, reducing the injected holes, and preventing the recombination of holes and electrons near the basal plane dislocation existing in the SiC substrate (for example, refer to patent document 1).

[0005] Prior art literature

[0006] Patent Literature

[0007] Patent Document 1: International Publication No. 2015 / 189929

[0008] Non-patent literature

[0009] Non-patent document 1: "Influence of growth conditions on basal plane dislocation in 4H-SiC epitaxial layer", Journal of Crystal Growth 271 (2004) 1-7

[0010] Non-patent document 2: "Short minority carrier lifetimes in highly nitrogen-doped 4H-SiC epilayers for suppression of the stacking fault formation in PiNdiodes", JOURNAL OF APPLIED PHYSICS Vol.120, pp115101, 2016 Summary of the Invention

[0011] The techniques disclosed in Non-Patent Documents 1 and 2 achieve a certain effect in suppressing the degradation of SiC MOSFET characteristics. However, this requires a thick buffer layer to apply a large current to the body diode, leading to increased production costs. Furthermore, buffer layers containing high impurity concentrations increase manufacturing variations, leading to reduced productivity.

[0012] The technology disclosed in Patent Document 1 has a problem in that a recombination center is formed in the pn junction portion, so that the characteristics of the body diode are significantly degraded and a large current cannot flow through the body diode.

[0013] The present disclosure has been made to solve the above-mentioned problems, and an object of the present disclosure is to provide a silicon carbide semiconductor device that has excellent productivity and suppresses degradation of characteristics when a large current flows through a body diode.

[0014] The first silicon carbide semiconductor device disclosed herein comprises: a silicon carbide substrate of a first conductivity type; a buffer layer of a first conductivity type formed on the silicon carbide substrate; a drift layer of a first conductivity type formed on the buffer layer; and a well region of a second conductivity type formed on the surface layer of the drift layer, wherein the structure including the silicon carbide substrate, the buffer layer and the drift layer is divided into an active region through which current flows when voltage is applied to the silicon carbide semiconductor device and a voltage-resistant maintenance region located on the outer peripheral side of the active region when viewed from above, and the active region is divided into a first active region in the center and a second active region between the first active region and the voltage-resistant maintenance region when viewed from above, and the lifetime of minority carriers in the second active region and the voltage-resistant maintenance region is shorter than the lifetime of minority carriers in the first active region.

[0015] A second silicon carbide semiconductor device disclosed herein includes: a silicon carbide substrate of a first conductivity type; a buffer layer of the first conductivity type formed on the silicon carbide substrate; a drift layer of the first conductivity type formed on the buffer layer; and a well region of a second conductivity type formed in a surface layer of the drift layer. The structure including the silicon carbide substrate, the buffer layer, and the drift layer is divided, in a plan view, into an active region through which current flows when a voltage is applied to the silicon carbide semiconductor device, and a withstand voltage maintenance region located further outward from the active region. The active region is divided, in a plan view, into a first active region in the center and a second active region between the first active region and the withstand voltage maintenance region. At least the second active region and the withstand voltage maintenance region of the first, second, and withstand voltage maintenance regions contain an inactive element. The device further includes an impurity region of the first conductivity type formed in a surface layer of a well region in the active region. The ion concentration of the inactive element in the second active region and the withstand voltage maintenance region is higher than the ion concentration of the inactive element in the first active region.

[0016] In the silicon carbide semiconductor device disclosed herein, the minority carrier lifetimes in the second active region and the withstand voltage maintenance region are shorter than those in the first active region. Therefore, when a large current flows through the body diode, hole current concentration at the boundary between the second active region and the withstand voltage maintenance region is suppressed. Furthermore, since the buffer layer does not need to be thickened to allow high current to flow through the body diode, productivity is improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 This is a top view of the SiC-MOSFET according to the first embodiment.

[0018] Figure 2 It is along Figure 1 1 is a cross-sectional view of the SiC-MOSFET according to the first embodiment, taken along line aa′.

[0019] Figure 3 It is along Figure 1 1 is a cross-sectional view taken along line aa′ showing the manufacturing process of the SiC-MOSFET according to the first embodiment.

[0020] Figure 4 It is along Figure 1 The cross-sectional view taken along line aa′ of FIG. 1 shows a manufacturing process of the SiC-MOSFET according to the second embodiment.

[0021] Figure 5 This is a diagram showing simulation results of hole current density distribution when the width of the second active region is set to 100 μm in the SiC-MOSFET of the first embodiment.

[0022] Figure 6This is a diagram showing the simulation result of the hole current density distribution when the width of the second active region is 0 μm in the SiC-MOSFET of Embodiment 1.

[0023] Figure 7 This is a diagram showing the ratio of the hole current density near the boundary between the active region and the breakdown voltage holding region to the hole current density at the center of the active region when the width of the second active region and the lifetime of minority carriers in the second active region are changed.

[0024] (Explanation of reference numerals)

[0025] 1: SiC epitaxial substrate; 2: gate pad; 3: source pad; 10: SiC substrate; 11: buffer layer; 12: drift layer; 13: active region; 14: breakdown voltage holding region; 15: first active region; 16: second active region; 21: source region; 31: well region; 32: well contact region; 33: JTE region; 41: gate insulating film; 42: gate electrode; 43: interlayer insulating film; 51: field insulating film; 61: contact hole; 71: ohmic electrode; 81, 82: implantation mask. Detailed implementation manners

[0026] <A. Embodiment 1>

[0027] <A-1. Structure>

[0028] Figure 1 This is a top view of the SiC-MOSFET 101 as a silicon carbide semiconductor device of Embodiment 1. Figure 2 This is along Figure 1 Cross-sectional view of the SiC-MOSFET 101 taken along the a-a' line. In this specification, a MOSFET based on a silicon carbide (SiC) substrate is referred to as a SiC-MOSFET.

[0029] As Figure 1 shown, the SiC-MOSFET 101 includes a SiC epitaxial substrate 1, a gate pad 2, and a source pad 3. The gate pad 2 is formed on the SiC epitaxial substrate 1. A gate voltage is applied from an external control circuit to the central portion of the gate pad 2. The source pad 3 is formed on the SiC epitaxial substrate 1 at a distance from the gate pad 2.

[0030] As Figure 2 shown, the SiC epitaxial substrate 1 is configured to include a SiC substrate 10 of the first conductivity type, a buffer layer 11 of the first conductivity type, and a drift layer 12 of the first conductivity type. On one surface of the SiC substrate 10 in the thickness direction, the buffer layer 11 and the drift layer 12 are sequentially formed by epitaxial growth.

[0031] The buffer layer 11 has the effect of allowing holes injected from the device surface to recombine and reducing the density of holes reaching the SiC substrate 10. The buffer layer 11 may also include a function of converting basal plane dislocations present in the SiC substrate 10 into edge dislocations. In addition, the buffer layer 11 may also be a stacked structure of multiple layers rather than a single layer. With respect to the buffer layer 11, the higher the impurity concentration, the higher the ability to suppress the expansion of stacking faults in response to the current. Therefore, the impurity concentration and film thickness of the buffer layer 11 are set according to the current density of the device. For example, the impurity concentration of the buffer layer 11 is preferably 1×10 18 cm -3 to 1×10 19 cm -3 .

[0032] The drift layer 12 is formed on one side of the buffer layer 11 in the thickness direction. The impurity concentration of the drift layer 12 is lower than that of the SiC substrate 10 and the buffer layer 11, and can be 5×10 16 cm -3 the following.

[0033] When viewed from above, the SiC-MOSFET 101 is divided into a central active region 13 and a voltage-resistant region 14 on the outer periphery of the active region 13. Furthermore, the active region 13 is divided into a central first active region 15 and a second active region 16 between the first active region 15 and the voltage-resistant region 14. In other words, the second active region 16 is the region of the active region 13 on the voltage-resistant region 14 side. The width of the second active region 16, i.e., Figure 2 The length in the horizontal direction of the paper is at least 10 μm. Furthermore, the minority carrier lifetime in the second active region 16 is shorter than the minority carrier lifetime in the first active region 15. The minority carrier lifetimes in the first active region 15, the second active region 16, and the withstand voltage maintaining region 14 are represented by τ1, τ2, and τ3, respectively.

[0034] The structure of the active region 13 will be described. Multiple well regions 31 of the second conductivity type are formed spaced apart from one another on the surface of the drift layer 12 in the active region 13. A well contact region 32 of the second conductivity type, having a relatively high impurity concentration, is formed in the center of the surface of each well region 31. The well contact region 32 serves to reduce contact resistance with the metal electrode. On the surface of each well region 31, a source region 21, which is an impurity region of the first conductivity type, is formed surrounding the well contact region 32.

[0035] A gate insulating film 41 is formed across the source regions 21 within two adjacent well regions 31. A gate electrode 42 and an interlayer insulating film 43 are formed on the gate insulating film 41. An ohmic electrode 71 is formed on the well contact region 32. The source pad 3 and the well contact region 32 are connected through the ohmic electrode 71. Further, in Figure 2 a planar gate electrode 42 is shown, but the gate electrode 42 may also be a trench type. That is, the gate electrode 42 faces the well region 31 across the gate insulating film 41.

[0036] In the active region 13, a pn junction is formed by the well region 31 and the source region 21. The active region 13 is defined as the region where current flows when a voltage is applied to the SiC-MOSFET 101.

[0037] Next, the structure of the breakdown voltage holding region 14 will be described. In the breakdown voltage holding region 14, a well region 31 and a well contact region 32 are also formed in the same manner as in the active region 13. Further, a JTE region 33 of the second conductivity type is formed in the outer peripheral portion of the well region 31 in the breakdown voltage holding region 14. The JTE region 33 is used to maintain the breakdown voltage of the semiconductor device, and an example thereof is an FLR (Field Limiting Ring) structure formed in a ring shape along the outer periphery of the semiconductor device. The innermost JTE region 33 when looking down at the SiC-MOSFET 101 is connected to the outermost well region 31 when looking down.

[0038] A field insulating film 51 is formed on the well region 31 in the breakdown voltage holding region 14, and the gate electrode 42 is formed on the field insulating film 51. In addition, the interlayer insulating film 43 is formed so as to cover the gate electrode 42. However, an opening is provided in the interlayer insulating film 43 where the gate electrode 42 is exposed, and through this opening, the gate electrode 42 is electrically connected to the gate pad 2 on the interlayer insulating film 43.

[0039] In the breakdown voltage holding region 14, a pn junction is formed by the well region 31 and the drift layer 12. The breakdown voltage holding region 14 is the region that maintains the breakdown voltage of the semiconductor device. The JTE region 33 is formed along the periphery of the active region 13 when looking down at the SiC-MOSFET 101.

[0040] In the SiC-MOSFET 101, the lifetimes τ2 and τ3 of the minority carriers in the second active region 16 and the breakdown voltage holding region 14 are shorter than the lifetime τ1 of the minority carriers in the first active region 15.

[0041] <A-2. Manufacturing Method>

[0042] Next, the manufacturing method of the SiC-MOSFET 101 will be described. Figure 31 is a cross-sectional view showing a manufacturing process of SiC-MOSFET 101. In the following description, the first conductivity type is n-type and the second conductivity type is p-type, but the conductivity types may be opposite.

[0043] First, prepare an n-type and low-resistance SiC substrate 10. The SiC substrate 10 is a (0001) plane with an off-angle in the first principal surface, and has a 4H polytype. Then, an n-type buffer layer 11 is epitaxially grown on the SiC substrate 10 by chemical vapor deposition (CVD). The n-type impurity concentration of the buffer layer 11 is 1×10 18 cm -3 Above and 1×10 19 cm -3 Hereinafter, the thickness is, for example, 5 μm.

[0044] Next, a drift layer 12 composed of n-type SiC is epitaxially grown on the buffer layer 11. The n-type impurity concentration of the drift layer 12 is 1×10 14 cm -3 Above and 5×10 16 cm -3 The thickness of the drift layer 12 is 5 μm or more and 100 μm or less, for example, 10 μm.

[0045] After that, an implantation mask is formed on a portion of the surface of the drift layer 12 using a photoresist or the like, and p-type impurity Al (aluminum) is ion implanted. At this time, the depth of the Al ion implantation is not less than 0.3 μm and not more than 3 μm, which is not greater than the thickness of the drift layer 12. The impurity concentration of the Al ion implanted is 1×10 17 cm -3 Above and 1×10 19 cm -3 The impurity concentration is higher than that of the drift layer 12. After that, the implantation mask is removed. The region into which the Al ions are implanted in this step becomes the well region 31.

[0046] Next, an implantation mask is formed using a photoresist or the like in a portion of the surface of the drift layer 12 in the withstand voltage holding region 14, and ion implantation of the p-type impurity Al is performed. At this time, the depth of the Al ion implantation is set to a depth not less than 0.3 μm and not more than 3 μm, which is not greater than the thickness of the drift layer 12. The impurity concentration of the implanted Al is 1×10 16 cm -3 Above and 1×10 18 cm -3The following range is higher than the impurity concentration of the drift layer 12 and lower than the impurity concentration of the well region 31. The implantation mask is then removed. The region where Al is ion-implanted in this step becomes the JTE region 33. Similarly, Al is ion-implanted into a portion of the well region 31 at a higher impurity concentration than the well region 31, forming the well contact region 32.

[0047] Then, an implantation mask is formed using a photoresist or the like so as to open a portion of the inner region of the well region 31 in the active region 13, and N (nitrogen) is ion implanted as an n-type impurity. The depth of the N ion implantation is shallower than the thickness of the well region 31. The impurity concentration of the implanted N is 1×10 18 cm -3 Above and 1×10 21 cm -3 Thereafter, the p-type impurity concentration exceeds that of the well region 31. In this step, the region exhibiting n-type among the regions into which N is implanted becomes the source region 21.

[0048] Next, a lifetime adjustment process is performed to make the lifetimes τ2 and τ3 of the minority carriers in the second active region 16 and the withstand voltage maintaining region 14 shorter than the lifetime τ1 of the minority carriers in the first active region 15. Specifically, Figure 3 As shown, an implantation mask 81 is formed on the surface of the drift layer 12 in the first active region 15 by using a photoresist or an oxide film, and ions of an inactive element are irradiated to introduce recombination centers into the second active region 16 and the withstand voltage holding region 14. Figure 3 In the embodiment, the injection mask 81 is formed only in the first active region 15, but it can also be formed in the withstand voltage maintenance region 14 in addition to the first active region 15. That is, the injection mask 81 only needs to be formed in the first active region 15. The inactive element irradiated in this process is, for example, He or Ar. The injection energy is preferably greater than 10 keV and less than 10 MeV. In the region injected with ions in this process, crystal defects are formed due to the irradiated ions. The formed crystal defects act as recombination centers for holes and electrons, so in the region injected with ions, the probability of recombination of holes and electrons becomes higher than in the region not injected with ions, and the carrier lifetime becomes shorter. As a result, the lifetimes τ2 and τ3 of the minority carriers in the second active region 16 and the withstand voltage maintenance region 14 are shorter than the lifetime τ1 of the minority carriers in the first active region 15.

[0049] Next, annealing is performed in a heat treatment apparatus in an inert gas atmosphere such as argon (Ar) at a temperature of 1300°C to 1900°C for 30 seconds to 1 hour. This annealing electrically activates the implanted N and Al ions, while simultaneously restoring the SiC crystals that were excessively damaged by He ion irradiation.

[0050] Thereafter, a field insulating film 51 made of silicon oxide having a film thickness of 0.3 μm to 2 μm is formed on the well region 31 of the withstand voltage holding region 14 using CVD or photolithography technology.

[0051] Next, a silicon oxide film of a desired thickness is formed as the gate insulating film 41 by thermally oxidizing the silicon carbide surface not covered by the field insulating film 51. A conductive polysilicon film is then formed on the gate insulating film 41 and the field insulating film 51 by a reduced-pressure CVD method and patterned to form the gate electrode 42. Next, an interlayer insulating film 43 composed of silicon oxide is formed by a reduced-pressure CVD method. Then, a contact hole 61 is formed that penetrates the interlayer insulating film 43 and the gate insulating film 41 and reaches the well contact region 32 and the well region 31.

[0052] Next, after forming a metal film mainly composed of Ni by sputtering or the like, heat treatment is performed at a temperature of 600°C to 1100°C to react the metal film mainly composed of Ni with the silicon carbide layer in the contact hole 61, thereby forming a silicide between the silicon carbide layer and the metal film. The remaining metal film other than the silicide obtained by the reaction is then removed by wet etching. Thus, the remaining silicide becomes the ohmic electrode 71. Next, a metal film mainly composed of Ni is formed on the back side (second main surface) of the SiC substrate 10 and heat treated, thereby forming a back ohmic electrode (not shown) on the back side of the SiC substrate 10.

[0053] Afterwards, a wiring metal such as Al is formed on the surface of the substrate processed to this point by sputtering or vapor deposition, and then processed into a predetermined shape using photolithography technology to form a source pad 3 in contact with the ohmic electrode 71 and a gate pad 2 in contact with the gate electrode 42. Thus, SiC-MOSFET 101 is obtained.

[0054] Thus, in the manufacturing method of SiC-MOSFET101, an n-type buffer layer 11 is formed on an n-type SiC substrate 10, an n-type drift layer 12 is formed on the buffer layer 11, and a plurality of p-type well regions 31 separated from each other are formed on the surface of the drift layer 12. The structure including the SiC substrate 10, the buffer layer 11 and the drift layer 12 is divided into an active region 13 and a voltage-resistant maintenance region 14 located on the outer side of the active region 13 when viewed from above. The active region 13 is divided into a first active region 15 in the central portion and a second active region 16 between the first active region 15 and the voltage-resistant maintenance region 14 when viewed from above. A source region 21 serving as an n-type impurity region is formed on the surface of the well region 31 in the active region 13, and inactive elements are ion-implanted into the second active region 16 and the voltage-resistant maintenance region 14 to introduce recombination centers.

[0055] In the above description, by means of a single ion implantation process, non-active elements are simultaneously irradiated onto the second active region 16 and the breakdown voltage holding region 14, so that the lifetimes τ2 and τ3 of minority carriers in the second active region 16 and the breakdown voltage holding region 14 become the same value. However, the ion implantation process of non-active elements can also be divided into two times, and non-active elements are irradiated onto the breakdown voltage holding region 14 and the second active region 16 at different timings.

[0056] Specifically, an implantation mask is formed on the surface of the drift layer 12 in the first active region 15 and the breakdown voltage holding region 14, and the first ion irradiation of non-active elements is performed. The implantation energy is preferably 10 keV or more and 10 MeV or less. In the second active region 16 into which ions are implanted in this process, crystal defects are formed due to the irradiated ions.

[0057] After that, the implantation mask is removed from the surface of the drift layer 12 in the first active region 15 and the breakdown voltage holding region 14. Then, an implantation mask is formed on the surface of the drift layer 12 in the first active region 15 and the second active region 16, and the second ion irradiation for introducing recombination centers is performed. The ions irradiated here are the same as those irradiated in the first time, but the irradiation amount is larger in the second time. As a result, more ions are irradiated onto the breakdown voltage holding region 14 than the second active region 16, and a large number of crystal defects are formed. Therefore, the lifetime τ3 of minority carriers in the breakdown voltage holding region 14 is shorter than the lifetime τ2 of minority carriers in the second active region 16. That is, the lifetimes of minority carriers become τ3 < τ2 < τ1.

[0058] <A-3. Effect>

[0059] The lifetimes of minority carriers in the breakdown voltage holding region 14, the first active region 15, and the second active region 16 can be measured by the microwave photoconductivity decay method (Microwave Photo Conductivity Decay, hereinafter referred to as the μ-PCD method). The μ-PCD method is a method for non-contact and non-destructively measuring the lifetime of carriers based on the time change of the reflectivity of microwaves. By pulse-irradiating a laser onto the SiC epitaxial substrate 1, excess carriers (majority carriers and minority carriers) are generated. The excess carriers recombine and disappear after a lifetime determined by physical characteristics such as the defect density or impurity concentration of the SiC epitaxial substrate 1. The time is measured by the change in the reflectivity of microwaves. Here, the lifetime of minority carriers is the time when the excess carriers become 1 / e when the generated excess carriers are set to 1.

[0060] In addition to this, the lifetimes of minority carriers can also be measured by methods such as photoluminescence.

[0061] The inventors found that when 500A / cm 2 At such a high current, a region where the hole current density is at least twice that of the center of the active region 13 occurs at the boundary between the active region 13 and the withstand voltage maintaining region 14 , and stacking faults occur preferentially in this boundary region.

[0062] According to SiC-MOSFET 101, by making the minority carrier lifetimes τ2 and τ3 in second active region 16 and withstand voltage maintaining region 14 shorter than the minority carrier lifetime τ1 in first active region 15, the body diode characteristics are not significantly degraded even when a large current is applied, and hole current concentration at the boundary between active region 13 and withstand voltage maintaining region 14 can be suppressed. Consequently, stacking faults originating from SiC substrate 10 at the boundary between active region 13 and withstand voltage maintaining region 14 can be suppressed. Furthermore, the buffer layer 11, which suppresses the occurrence of stacking faults, can be made thinner.

[0063] Figure 5 The following table shows the simulation results of the hole current density distribution when the active region 13 of the SiC-MOSFET 101 is replaced with a PN diode and the width of the second active region 16 is set to 100 μm. It is confirmed that the hole current density distribution results show the same trend when the active region 13 is a MOSFET and when it is a PN diode. In this simulation, the applied current is set to 1000 A / cm 2 , so that the lifetimes τ2 and τ3 of minority carriers in the second active region 16 and the withstand voltage holding region 14 become τ2=τ3, and change according to 2.2μs, 218ns, 72.7ns, 21.8ns, and 2.18ns. In addition, τ1 is 2.2μs. The vertical axis represents the ratio of the hole current density at the boundary between the active region 13 and the withstand voltage holding region 14 to the hole current density at the center of the active region 13. On the horizontal axis, with the boundary between the active region 13 and the withstand voltage holding region 14 as the origin, the chip periphery direction ( Figure 2 The horizontal axis (in the right direction of the paper) is positive and represents the distance from the boundary. The range of -200 μm to -100 μm on the horizontal axis corresponds to the first active region 15, and the range of -100 μm to 0 μm on the horizontal axis corresponds to the second active region 16. The hole current density is the value at the outermost surface of the SiC substrate 10.

[0064] exist Figure 5The figure shows that the shorter the minority carrier lifetimes τ2 and τ3 in the second active region 16 and the withstand voltage maintaining region 14, the more the hole current concentration occurring at the boundary between the active region 13 and the withstand voltage maintaining region 14 is eliminated. On the other hand, it is also clear that when the minority carrier lifetimes τ2 and τ3 in the second active region 16 and the withstand voltage maintaining region 14 are excessively reduced, hole current concentration occurs at the boundary between the first active region 15 and the second active region 16. Based on the above, the minority carrier lifetimes τ2 and τ3 in the second active region 16 and the withstand voltage maintaining region 14 are preferably 1 ns to 500 ns, and more preferably 10 ns to 100 ns, in order to eliminate hole current concentration. Generally, the lifetime τ1 of the minority carriers in the first active region 15 is greater than 1μs and less than 10μs, so the lifetimes τ2 and τ3 of the minority carriers in the second active region 16 and the voltage-resistant maintenance region 14 are preferably greater than 1 / 1000 and less than 1 / 10 of the lifetime τ1 of the minority carriers in the first active region 15.

[0065] Figure 6 Shown with Figure 5 Similarly, the hole current density distribution simulation results are obtained when the active region 13 of the SiC-MOSFET 101 is replaced with a PN diode and the width of the second active region 16 is set to 0 μm. In other words, the second active region 16 is not provided and only the withstand voltage maintaining region 14 is set as a low life region. It is confirmed that the hole current density distribution results show the same trend when the active region 13 is a MOSFET and when it is a PN diode. Other simulation conditions are the same as Figure 5 Same. From Figure 6 It is understood that even if the minority carrier lifetime τ3 in the second active region 16 is shortened, the effect of eliminating the concentration of hole current occurring at the boundary between the active region 13 and the withstand voltage maintaining region 14 is small.

[0066] Figure 7 The figure shows the ratio of the hole current density near the boundary between the active region 13 and the withstand voltage maintaining region 14 to the hole current density at the center of the active region 13 when the width of the second active region 16 and the lifetime of the minority carriers in the second active region 16 are changed. Figure 7 It can be seen that when the width of the second active region 16 is greater than or equal to 10 μm and the minority carrier lifetime τ2 in the second active region 16 is greater than or equal to 10 nsec and less than or equal to 100 nsec, the hole current density near the boundary between the active region 13 and the withstand voltage maintaining region 14 reaches a minimum value. This shows that there are optimal values for the width of the second active region 16 and the minority carrier lifetime τ2 in the second active region 16.

[0067] From the above results, it can be seen that by setting the second active region 16 with a short minority carrier lifetime, the concentration of hole current occurring at the boundary between the active region 13 and the voltage withstand holding region 14 can be eliminated.

[0068] The SiC-MOSFET 101 of Embodiment 1 includes a SiC substrate 10 of the first conductivity type, a buffer layer 11 of the first conductivity type formed on the SiC substrate 10, a drift layer 12 of the first conductivity type formed on the buffer layer 11, and a well region 31 of the second conductivity type formed on the surface layer of the drift layer 12. When the structure including the SiC substrate 10, the buffer layer 11, and the drift layer 12 is viewed from above, it is divided into an active region 13 through which current flows when a voltage is applied to the SiC-MOSFET 101, and a voltage withstand holding region 14 on the outer peripheral side of the active region 13. When viewed from above, the active region 13 is divided into a first active region 15 at the central portion and a second active region 16 between the first active region 15 and the voltage withstand holding region 14. At least the second active region 16 and the voltage withstand holding region 14 in the first active region 15, the second active region 16, and the voltage withstand holding region 14 contain inactive elements. The SiC-MOSFET 101 further includes a source region 21 which is an impurity region of the first conductivity type formed on the surface layer of the well region 31 formed in the active region 13. The ion concentration of the inactive elements in the second active region 16 and the voltage withstand holding region 14 is higher than the ion concentration of the inactive elements in the first active region 15. Thus, by the inactive elements, recombination centers are introduced into the second active region 16 and the voltage withstand holding region 14, so that the minority carrier lifetimes τ2 and τ3 are reduced and are shorter than the minority carrier lifetime τ1 in the first active region 15. Therefore, the concentration of hole current at the boundary between the active region 13 and the voltage withstand holding region 14 when a large current flows through the body diode is suppressed. In addition, since there is no need to form the buffer layer 11 thick, the productivity of the SiC-MOSFET 101 is also excellent.

[0069] <B. Embodiment 2>

[0070] <B-1. Structure>

[0071] The structure of the SiC-MOSFET 102 as a silicon carbide semiconductor device of Embodiment 2 is as Figure 1 and Figure 2As shown, it is the same as the SiC-MOSFET 101 of Embodiment 1. In the SiC-MOSFET 101, by implanting inactive element ions into the second active region 16, the lifetime τ2 of minority carriers in the second active region 16 is reduced, achieving τ1 > τ2. In addition to the characteristics of the above SiC-MOSFET 101, the SiC-MOSFET 102 also extends the lifetime τ1 of minority carriers in the first active region 15, and in addition to the effects of the SiC-MOSFET 101, it also has the effect of improving the element resistance of the body diode.

[0072] <B-2. Manufacturing Method>

[0073] The manufacturing method of the SiC-MOSFET 102 will be described. The manufacturing method of the SiC-MOSFET 102 is the same as that of the SiC-MOSFET 101 until the formation of the source region 21.

[0074] After the formation of the source region 21, as Figure 4 shown, on the surfaces of the second active region 16 and the drift layer 12 in the breakdown voltage holding region 14, an implantation mask 82 is formed by a photoresist or an oxide film, etc., and carbon atoms are implanted ionically. In Figure 4 , the implantation mask 82 is formed in the second active region 16 and the breakdown voltage holding region 14, but it may not be formed in the breakdown voltage holding region 14. Here, the implantation surface density of the ionic implantation of carbon atoms is preferably 1×10 13 cm -2 or more and 1×10 16 cm -2 or less. In addition, the implantation energy is preferably 10 keV or more and 10 MeV or less. Through this process, carbon atoms are implanted ionically into the first active region 15 and introduced between the lattices in the SiC epitaxial crystal.

[0075] Next, by irradiating the second active region 16 and the breakdown voltage holding region 14 with He ions or Ar ions, recombination centers are introduced. This process is the same as the process shown in Embodiment 1 Figure 3 . Through this process, the lifetimes τ2 and τ3 of minority carriers in the second active region 16 and the breakdown voltage holding region 14 are reduced and are shorter than the lifetime τ1 of minority carriers in the first active region 15.

[0076] In addition, in the above description, recombination centers are introduced after the implantation of carbon atoms, but the order of the two processes can also be reversed.

[0077] Next, through a heat treatment device, annealing is performed at a temperature of 1300 °C or higher and 1900 °C or lower for 30 seconds or longer and 1 hour or shorter in an inert gas atmosphere such as argon (Ar) gas. Through this annealing, the implanted N and Al are electrically activated, and at the same time, the SiC crystal excessively damaged by He ion irradiation is restored. Furthermore, the inter-lattice carbon atoms react with the carbon vacancies, which are a type of point defect, present in the drift layer 12. As a result, the point defects in the first active region 15 implanted with inter-lattice carbon atoms are reduced, and the traps of minority carriers caused by the point defects are reduced, so that the minority carrier lifetime τ1 in the first active region 15 increases.

[0078] Thereafter, similarly to the first embodiment, by forming the field insulating film 51, the gate insulating film 41, the gate electrode 42, the interlayer insulating film 43, the ohmic electrode 71, the source pad 3, and the gate pad 2, the SiC-MOSFET 102 is completed.

[0079] <B-3. Effects>

[0080] In the SiC-MOSFET 102 of the second embodiment, the carbon concentration in the first active region 15 is higher than the carbon concentration in the second active region 16 and the breakdown voltage holding region 14. Therefore, in the first active region 15, the minority carrier lifetime τ1 becomes longer, and the effect of conductivity modulation in the drift layer 12 is improved. Therefore, in addition to the effects of the first embodiment, an effect that the element resistance of the body diode becomes smaller is also obtained.

[0081] In addition, the minority carrier lifetime τ2 in the second active region 16 may not be longer than the minority carrier lifetime τ3 in the breakdown voltage holding region 14.

[0082] The technologies disclosed in the respective embodiments of this specification can be freely combined, appropriately deformed, or omitted within the range where their effects are achieved.

Claims

1. A silicon carbide semiconductor device comprising: a silicon carbide substrate of a first conductivity type; a buffer layer of a first conductivity type formed on the silicon carbide substrate; a drift layer of the first conductivity type formed on the buffer layer; A well region of the second conductivity type is formed in a surface layer of the drift layer; A source region as an impurity region of the first conductivity type is formed in a surface layer of the well region; as well as a source pad electrically connected to the source region, The structure including the silicon carbide substrate, the buffer layer, and the drift layer is divided into an active region through which current flows when voltage is applied to the silicon carbide semiconductor device and a withstand voltage maintenance region located on the outer peripheral side of the active region when viewed from above. The active region is divided into a first active region in the center and a second active region between the first active region and the withstand voltage maintaining region in a plan view. The first active region and the second active region are covered by the source pad. The lifetime of minority carriers in the second active region and the withstand voltage maintaining region is shorter than the lifetime of minority carriers in the first active region.

2. The silicon carbide semiconductor device according to claim 1, wherein A portion of the withstand voltage maintaining region is covered by the source pad.

3. The silicon carbide semiconductor device according to claim 1 or 2, wherein: The minority carrier lifetime in the second active region and the withstand voltage maintaining region is not less than 1 ns and not more than 500 ns.

4. The silicon carbide semiconductor device according to claim 1 or 2, wherein The lifetime of minority carriers in the second active region and the withstand voltage maintaining region is 1 / 1000 or more and 1 / 10 or less of the lifetime of minority carriers in the first active region.

5. The silicon carbide semiconductor device according to claim 1 or 2, wherein The width of the second active region is greater than or equal to 10 μm.

6. The silicon carbide semiconductor device according to claim 1 or 2, wherein: The impurity concentration of the buffer layer is 1×10 18 cm -3 Above and 1×10 19 cm -3 the following.

7. The silicon carbide semiconductor device according to claim 1 or 2, wherein: The impurity concentration of the drift layer is 5×10 16 cm -3 the following.

8. The silicon carbide semiconductor device according to claim 1 or 2, wherein The carbon concentration in the first active region is higher than the carbon concentrations in the second active region and the withstand voltage maintaining region.

9. A silicon carbide semiconductor device comprising: a silicon carbide substrate of a first conductivity type; a buffer layer of a first conductivity type formed on the silicon carbide substrate; a drift layer of the first conductivity type formed on the buffer layer; A well region of the second conductivity type is formed in a surface layer of the drift layer; A source region as an impurity region of the first conductivity type is formed in a surface layer of the well region; as well as a source pad electrically connected to the source region, The structure including the silicon carbide substrate, the buffer layer, and the drift layer is divided into an active region through which current flows when voltage is applied to the silicon carbide semiconductor device and a withstand voltage maintenance region located on the outer peripheral side of the active region when viewed from above. The active region is divided into a first active region in the center and a second active region between the first active region and the withstand voltage maintaining region in a plan view. The first active region and the second active region are covered by the source pad. At least the second active region and the withstand voltage maintaining region among the first active region, the second active region, and the withstand voltage maintaining region contain an inactive element. The ion concentration of the inactive element in the second active region and the withstand voltage maintaining region is higher than the ion concentration of the inactive element in the first active region.

10. A method for manufacturing a silicon carbide semiconductor device, forming a first conductivity type buffer layer on a first conductivity type silicon carbide substrate; forming a first conductive type drift layer on the buffer layer; A plurality of well regions of the second conductivity type are formed on the surface layer of the drift layer and are spaced apart from each other. A source region as an impurity region of the first conductivity type is formed on the surface layer of the well region. forming a source pad electrically connected to the source region, The structure including the silicon carbide substrate, the buffer layer, and the drift layer is divided into an active region through which current flows when voltage is applied to the silicon carbide semiconductor device and a withstand voltage maintenance region located on the outer periphery of the active region when viewed from above. The active region is divided into a first active region in the center and a second active region between the first active region and the withstand voltage maintaining region in a plan view. The first active region and the second active region are covered by the source pad. In the second active region and the withstand voltage maintaining region, an inactive element is ion-implanted to introduce recombination centers.

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