A 16-channel neural recorder

Abstract

This invention provides a 16-channel neural recorder, comprising: a chip integrating an analog front-end and a polarized transmitter, and a software-defined receiver as a transponder. The chip further includes a data buffer, a channel encoder, a DMA that transmits data to the data buffer, and the channel encoder for packetizing and channel coding according to register file configuration parameters. A modulator receives the output of the channel encoder, modulates it, and inputs it to a frequency shaping filter. The output of the frequency shaping filter is then fed to the polarized transmitter. The receiver is based on an FPGA and includes a pairwise connected RF front-end, an FPGA, and an ARM processor. Experimental results show that the input reference noise of the AFE is 2.87 μVrms, and the energy efficiency of the transmitter is 2.8 nJ / bit. The chip consumes a total power of 5.47 mW under maximum load. In vivo experiments on rats demonstrate good system usability.

Description

Technical Field

[0001] This invention relates to the field of neural recording technology, and specifically to a 16-channel neural recorder. Background Technology

[0002] Neural interface implants enable invasive acquisition and monitoring of brain activity. This is an effective treatment approach in biomedical research aimed at understanding neural circuits and providing treatments for neurological diseases in clinical practice. The functions of neural interface implants include: 1) amplification and digitization of analog neural signals, 2) selective local feature extraction of raw acquired signals, and 3) data transmission to external devices.

[0003] Wireless neural interface solutions have been published in the literature using COTS (Commercial Off-the-Shelf) chips. However, their bulky size and high power consumption are not friendly to invasive scenarios. Furthermore, wireless solutions in the 2.4 GHz band are easily interfered with by other devices such as Bluetooth or Wi-Fi. SoC solutions integrating analog front-ends and RF circuitry have been developed for neural interfaces to enable system miniaturization and reduce power consumption. Some have proposed designs integrated with a 433 MHz OOK transmitter, while others have proposed UWB solutions. The high data rate transmitter integration in these projects places high demands on the experimental environment due to its sensitivity, limiting the operating wavelength to approximately 1 meter. The Medical Institution Area Network (MBAN) band operates at frequencies of 2.36–2.4 GHz with less interference. It is suitable for stable neural recording in larger experimental spaces. Summary of the Invention

[0004] The objective of this invention is achieved through the following technical solutions.

[0005] This invention proposes a single-chip solution for wireless neural signal recorders and a complete chip-based system design. The chip integrates a 16-channel analog front-end (AFE) with a variable sampling rate for neural signal recording and a transmitter in the 2.36-2.4 GHz band. To reduce chip resources and power consumption, a constant envelope polarity transmitter is designed. The modulation scheme employs a general form of continuous phase modulation, supporting two different modulation orders and four different speed modes. In the receiver design, demodulation algorithms including frequency offset calibration, frame synchronization, and symbol demodulation are proposed and implemented in FPGA-based software-defined radio (SDR). Bench tests and in-system tests were conducted on the system.

[0006] According to a first aspect of the invention, a 16-channel neural recorder is provided, comprising: a chip integrating an analog front-end and a polarity transmitter, and a software-defined receiver as a transponder.

[0007] Furthermore, the analog front end is a 16-channel analog front end used to acquire neural signals, with a configurable sampling rate of 1kS / s to 24kS / s.

[0008] Furthermore, the differential input signal of the analog front end is converted into current, and the output current is fed into two 29-stage ring oscillators to convert it into the phase domain. The output frequency of the ring oscillators reflects the coarse resolution of the original signal, while the phase provides fine resolution.

[0009] Furthermore, the analog front end further includes:

[0010] A phase decoder is used to quantize the final output of the analog front end.

[0011] Furthermore, the chip further includes a readout module, a DMA, and an SRAM. The readout module is used to organize data from the analog front end and to store the data in the SRAM under the control of the DMA.

[0012] Furthermore, the chip further includes a data buffer and a channel encoder. The DMA transmits data to the data buffer, and the channel encoder is used for packing and channel encoding according to the register file configuration parameters.

[0013] Furthermore, the chip further includes a modulator and a frequency shaping filter. The modulator receives the output of the channel encoder, modulates it, and inputs it into the frequency shaping filter. The output of the frequency shaping filter is sent to the polarity transmitter.

[0014] Furthermore, the receiver is based on an FPGA and includes a radio frequency front-end, an FPGA, and an ARM processor connected in pairs; the FPGA includes a demodulator, and the ARM processor includes a buffer and a radio frequency controller.

[0015] Furthermore, the software-defined receiver employs the following algorithms: carrier frequency offset calibration, frame synchronization, and symbol demodulation.

[0016] Furthermore, the ARM processor receives demodulated symbols from the FPGA via the AXI4 stream port, the symbols are buffered and sent to an external computer via an Ethernet connection, and the neural signals are decoded and displayed on the computer.

[0017] This invention proposes a 16-channel neural recorder with the following advantages: an input reference noise of 2.87 μVrms for the AFE and a transmitter energy efficiency of 2.8 nJ / bit. The chip consumes a total power of 5.47 mW under maximum load. Neural signals can be correctly decoded at least at -95 dBm RSSI (Received Signal Strength Indicator), and the operating distance is 8 meters. In vivo experiments on rats have demonstrated good system usability. Attached Figure Description

[0018] Various other advantages and benefits will become apparent to those skilled in the art upon reading the following detailed description of preferred embodiments. The accompanying drawings are for illustrative purposes only and are not intended to limit the invention. Furthermore, the same reference numerals denote the same parts throughout the drawings. In the drawings:

[0019] Appendix Figure 1 A schematic diagram of the architecture of a 16-channel neural recorder according to the present invention is shown.

[0020] Appendix Figure 2 A schematic diagram of a typical frame structure for digital baseband is shown.

[0021] Appendix Figure 3 A schematic diagram is shown showing the selection of the raised cosine of the spectrum as the frequency shaping function.

[0022] Appendix Figure 4 A block diagram of the receiver algorithm of the present invention is shown.

[0023] Appendix Figure 5 A schematic diagram illustrating the concept of demodulation using the sine and cosine values ​​of the phase difference is shown.

[0024] Appendix Figure 6 A schematic diagram of the chip structure of the present invention is shown.

[0025] Appendix Figure 7 A schematic diagram of resource usage in an FPGA architecture is shown.

[0026] Appendix Figure 8 A schematic diagram comparing the present invention with the prior art is shown. Detailed Implementation

[0027] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0028] This invention proposes a miniature neural interface system. A monolithic neural recording SoC, fabricated using a 40nm CMOS process, has an area of ​​3mm × 3mm. It integrates a 16-channel analog front-end (AFE) and a low-power constant envelope polarity transmitter. The modulation scheme employs a general form of continuous phase modulation. Receiver algorithms, including frequency offset calibration, frame synchronization, and symbol demodulation, are proposed and implemented on a software-defined radio platform. Simulation results show a bit error rate of 10% at a high data rate of 971.4kbps. -4 The required signal-to-noise ratio is 19dB. A graphical user interface and real-time display for channel decoding were designed.

[0029] I. A 16-channel neural recorder

[0030] like Figure 1 The diagram shown illustrates the architecture of a 16-channel neural recorder according to the present invention. It includes a chip integrating an analog front-end and a polarity transmitter, as well as a software-defined receiver acting as a transponder.

[0031] The wireless recorder chip consists of a 16-channel analog front-end (AFE) for acquiring neural signals. The AFE has a configurable sampling rate from 1 kS / s to 24 kS / s to accommodate different types of signals of interest. The AFE structure is as follows... Figure 1 As shown, the differential input signal is converted into current. The output current is fed into two 29-stage ring oscillators (ROs) to convert it to the phase domain. The output frequency fi of the ring oscillators reflects the coarse resolution of the original signal, while the phase φi provides additional fine resolution. A phase decoder is used to quantize the final output of the AFE. A readout module is used to organize the data from the AFE and store the data in SRAM under DMA control. The DMA transfers the data to a data buffer for packing and channel coding according to register file configuration parameters. The outputs of the modulator and frequency shaping filter are fed into a polarity transmitter. Demodulation is performed using an FPGA-based receiver. A graphical user interface was designed for real-time display of channel decoding and results.

[0032] II. Digital baseband of the transmitter

[0033] A. Data Packaging and Channel Coding

[0034] The transmitter operates in frames, allowing for better synchronization between the receiver and higher-layer protocols. The raw data needs to be organized into frames according to... Figure 2The image shows a typical frame structure for a data packet. A preamble is sent first for synchronization, followed by a PHY header containing modulation information such as the data rate, radio channel selection, and the byte length L of the frame body. The frame body includes samples. The first part is the available channel information bits. In this field, if the Mth bit is 1, it indicates that the Mth channel is enabled, and the number of channels in the frame equals the number of 1s in this field. The samples for each channel are grouped together, and the sample number N can be calculated from L and M.

[0035] Furthermore, to avoid errors caused by undesirable factors such as noise, interference, and / or fading, a BCH encoder is used for forward error correction, and cyclic redundancy check (CRC) is used for error detection. For added flexibility, the encapsulation behavior and parameters in channel coding can be configured.

[0036] B. Modulation scheme: CPM

[0037] The recording SoC of this invention operates at a frequency below 2.4 GHz, with a 1 MHz interval between each frequency band and a symbol rate of 600 kHz. A polarized transmitter is used. Furthermore, to reduce design and area resources, and to meet the linearity requirements of the radio front-end power amplifier, the amplitude modulation (AM) path is discarded. This allows the transmitter to have a constant envelope; these modulation methods are suitable for and widely used in low-power communication systems such as Bluetooth Low Energy (BLE) and Global System for Mobile Communications (GSM).

[0038] To facilitate baseband testing and use, this invention selects a general form of constant envelope modulation scheme, namely continuous phase modulation (CPM). In CPM, the only modulation position of a symbol is the signal phase, or alternatively, the signal frequency. Therefore, the baseband signal of CPM at time t is only a function of the phase Φ(t, h, a), as shown below:

[0039]

[0040] In the formula, Es and T are constants, representing the average energy and symbol duration of the symbol respectively. a = {ai} is the information symbol with values ​​{±1, ±3, …±(M-1)}, given a modulation order (M). h is the modulation index, and Φ(t, h, a) is the phase function modulation information a, as shown below:

[0041]

[0042] Where q(t) and g(t) are phase and frequency shaping pulse functions, q(t) has a constraint: when t≤0, q(t)≡0, and when t≥LT, q(t)≡1 / 2, where L is the length of q(t).

[0043] In CPM, L, h, M, and the shape of the shaping function are key parameters for its spectral and modulation performance. To maximize the transmitter's data rate to support different types of signal acquisition scenarios, M can be set to 2 or 4, and h can be set to 1 / 2 and 1 / 4 respectively, thus achieving a variable data rate from 121.4 kbps to 971.4 kbps. This better supports different sampling rates and environments. Under these settings, the phase transition is ±π / 2 or ±π / 4-3π / 4 within one symbol period. Demodulation is more difficult with M=4, and the solution will be introduced in Section 3. For L and the shape of the shaping function, to provide flexibility in optimization, L can be limited to ≤2 in the recording chip of this invention. In testing and experiments, as... Figure 3 As shown, the raised cosine of the spectrum is chosen as the frequency shaping function, and L is set to 2. The arrows indicate the decision points during demodulation, and the shaded areas represent the phase contribution of the additional symbols.

[0044] III. Software-defined receiver

[0045] A. Algorithm

[0046] To pair with the transmitter, this invention proposes a series of receiver algorithms, including carrier frequency offset calibration, frame synchronization, and symbol demodulation. These algorithms convert the I / Q samples from the RF front end into corresponding symbols. Figure 4 A block diagram of the proposed algorithm is shown, which will be discussed below.

[0047] 1) Demodulation: As described in Section 2, the phase of each symbol in a CPM modulated signal changes depending on the symbol itself and the modulation index. If the differential phase between each symbol period is calculated, this value can be used in the demodulation process. However, directly converting each I / Q sample to phase would be extremely costly. In practice, this can be achieved by using... Figure 4 The "symbol phase difference" shown is achieved through delayed multiplication. If the phases of the two additional symbol times are φ2 and φ1, the result will be:

[0048]

[0049] This shows that the sine and cosine of the differential phase can be easily calculated.

[0050] like Figure 5 As shown, the two signs when M=2 can be determined using the sine value, while the four signs when M=4 can be determined by combining the sine and cosine values.

[0051] Even in this example, where the shaping function length is set to 2, meaning the differential phase depends on the current sign and two additional signs, if we make the decision in the middle of a sign, such as Figure 3As shown, the effect will be eliminated. Calculations show that the maximum deviation of the sine and cosine values ​​caused by this overlap is only 0.26%, which is very small and negligible. To verify the proposed demodulation algorithm, the bit error rate-signal-noise ratio curves were simulated for M=2 and M=4 without BCH coding. The bit error rate is 10. -4 The signal-to-noise ratios are 11.9 dB and 18.6 dB, respectively.

[0052] 2) Frame Synchronization: A preamble field is used for frame synchronization. Similar to the demodulation algorithm, the correlation of the sine values ​​can be easily calculated using delay lines and adders. The peak of the correlation result signifies the start of a frame. To utilize the energy of the entire symbol, a symbol-length moving average has been performed. Another moving average module is used to calculate the average amplitude to dynamically set the threshold, as the signal amplitude from the RF front end varies over time.

[0053] 3) Carrier Frequency Offset Calibration: Carrier frequency offset between the transmitter and receiver will cause continuous phase drift in the received I / Q samples. This invention proposes a simple and effective method to calibrate this offset. If phase drift exists during the empty carrier period, the phase of the delay multiplication is not zero. As a result, as... Figure 4 As shown, the carrier frequency offset can be calibrated by eliminating this value during a short period of time on the empty carrier before each frame.

[0054] B. Implementation and System Integration

[0055] An FPGA-based SDR was chosen for its flexible scalability. It comprises an RF board with a configurable RF front-end (AD9361) for capturing radio signals into I / Q samples, and an FPGA board with a Zynq SoC (xc7z020) for performing computations. A computer controls the workflow and provides real-time monitoring.

[0056] Structure as Figure 1 As shown, the ARM processor receives demodulated symbols from the FPGA via the AXI4 stream port. The symbols are buffered and transmitted to the computer via an Ethernet connection. The neural signals are then decoded and displayed on the computer.

[0057] IV. Experimental Results

[0058] The wireless neural signal recording SoC proposed in this invention includes a digital baseband and is fabricated using a 40nm CMOS process. The chip is as follows... Figure 6 As shown. The entire SoC occupies a 3mm x 3mm silicon area, including the front-end, RF circuitry, programmable core, and digital baseband. The digital baseband itself occupies 0.172mm. 2 The simulation consumed 98.2 μW. For example... Figure 6As shown, a microcircuit board integrating the proposed wireless SoC and electrode connectors was designed. The recording board can be fixed to the skull of a test animal. The connectors are used to connect different types of electrodes implanted in regions of interest in the brain. The board measures 15mm × 20mm. Test results show that the AFE has an input reference noise of 2.87μVrms, a bandwidth of 250Hz-2kHz, a total chip power consumption of 5.47mW, a total transmitter power consumption of 2.75mW, and an energy efficiency of 2.8NJ / bit at an output power of -5dBm and a sampling rate of 24kS / s.

[0059] This invention models and simulates the proposed receiver algorithm and implements it using Simulink software and its support for Zynq hardware. The FPGA architecture incurs several fixed resource costs in order to interface with the RF front-end and other parts of the circuit board. Figure 7 The resource utilization of the RX design itself is shown, along with the complete implementation including other interface circuits. It can be seen that the proposed receiver design uses only about 10% of the FPGA. Experimental results demonstrate that the software-defined receiver of this invention can correctly decode neural signals in high data rate mode at low RSSI (Received Signal Strength Indicator, -95dBm), with a working distance of at least 8m, making it suitable for large experimental spaces.

[0060] This invention was tested in vivo in rats. A 16-channel electrode chip connected to a microplate was inserted into the right STN region of the rat (AP-3.8mm, ML-2.5mm, DV-8.2mm). Recording parameters were set to 1 kS / s per channel. The acquired signals for channels #1, 5, 6, 10, 15, and 16 are shown below. Figure 6 As shown. Figure 8 A comparison table is provided.

[0061] V. Conclusion

[0062] This paper proposes a miniature neural interface system comprising a wireless neural recording SoC fabricated using a 40nm CMOS process and an SDR-based receiver. The SoC integrates a 16-channel analog-to-electrical (AFE) and a low-power polarized transmitter. A series of receiver algorithms are proposed and implemented. Experimental results show that the AFE has an input reference noise of 2.87 μVrms and the transmitter has an energy efficiency of 2.8 nJ / bit. The chip consumes a total power of 5.47 mW under maximum workload. The transmitted signal can be correctly decoded at least -95 dBm RSSI, with a working distance of 8 m. In vivo experiments on rats demonstrate the good usability of the proposed system.

[0063] The above description is merely a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A 16-channel neural recorder, characterized in that, include: A chip that integrates an analog front-end and a polarity transmitter, as well as a software-defined receiver that acts as a transponder; The differential input signal of the analog front end is converted into current, and the output current is fed into two 29-stage ring oscillators to be converted into the phase domain. The output frequency of the ring oscillators reflects the coarse resolution of the original signal, while the phase provides fine resolution. The chip further includes a readout module, DMA, and SRAM. The readout module is used to organize data from the analog front end and to store the data in the SRAM under the control of the DMA. The chip further includes a data buffer and a channel encoder. The DMA transmits data to the data buffer, and the channel encoder is used to pack and channel encode data according to the register file configuration parameters. The chip further includes a modulator and a frequency shaping filter. The modulator receives the output of the channel encoder, modulates it, and inputs it into the frequency shaping filter. The output of the frequency shaping filter is sent to the polarity transmitter.

2. The 16-channel neural recorder according to claim 1, characterized in that, The analog front end is a 16-channel analog front end used to acquire neural signals, with a configurable sampling rate of 1kS / s to 24kS / s.

3. A 16-channel neural recorder according to claim 1, characterized in that, The simulation front end further includes: A phase decoder is used to quantize the final output of the analog front end.

4. A 16-channel neural recorder according to any one of claims 1-3, characterized in that, The receiver is based on an FPGA and includes a radio frequency front-end, an FPGA, and an ARM processor connected in pairs; the FPGA includes a demodulator, and the ARM processor includes a buffer and a radio frequency controller.

5. A 16-channel neural recorder according to claim 4, characterized in that, The software-defined receiver employs the following algorithms: carrier frequency offset calibration, frame synchronization, and symbol demodulation.

6. A 16-channel neural recorder according to claim 4, characterized in that, The ARM processor receives demodulated symbols from the FPGA via the AXI4 stream port. The symbols are buffered and sent to an external computer via an Ethernet connection. The neural signals are decoded and displayed on the computer.

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