fusible link programming unit, programming circuit, control circuit and array

Abstract

The application discloses a fuse programming unit, a programming circuit, a control circuit and an array, comprising two efuse units and a mode control tube; the first efuse unit comprises a first fuse one end forming a first line end of the fuse programming unit and a second end connected with a drain end of a first MOS; the first MOS has a source end connected with the ground and a gate end forming a first word line of the fuse programming unit; the second efuse unit comprises a second fuse first end forming a second line end of the fuse programming unit and a second end connected with a drain end of a second MOS; the second MOS has a source end connected with the ground and a gate end forming a second word line of the fuse programming unit; the mode control tube has a source end connected with the line end of the second efuse unit, a drain end connected with the source end of the first MOS and a gate end forming a correction end of the fuse programming unit. The application improves the use flexibility of the fuse programming unit array and realizes the redundancy correction function of each storage bit.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of integrated circuits, in particular to a fuse programming unit, a fuse programming circuit, a control circuit of the fuse programming unit and an array of fuse programming units. BACKGROUND

[0002] The eFuse is based on the principle of electron migration (EM) and realizes the programming function by fusing the fuse. The essence is that the internal read module of the eFuse converts the resistance value of the fuse into the corresponding logic value. The specific principle is that the comparison circuit compares the resistance of the fuse before and after fusing and generates different levels. However, the eFuse unit may have unexpected phenomena such as the fuse not being fused and the resistance being too small after programming, resulting in the read module outputting an incorrect logic value.

[0003] A conventional eFuse unit is composed of 1 fuse link and 1 NMOS control selection tube, as shown in Figure 1 .

[0004] An array composed of conventional eFuse units is shown in Figure 2 . The array is composed of a bit line BL and a word line WL. Each column of bit lines in the array is connected to an SA module through 1 NMOS read selection tube Nsa, and the control signal at the gate end of the read selection tube Nsa is RD. Each word line in the array is connected to the control selection tube gate end of the eFuse unit in the same row, and each column of bit lines is connected to the fuse end of the eFuse unit in the same column. Each column of bit lines in the array is connected to the programming power supply VDDQ through 1 PMOS power supply selection tube Mpn, and the gate end of the tube is controlled by a BLC signal.

[0005] When the conventional eFuse unit array is programmed, RD=0 closes the path of all bit lines BL in the array to the SA module. The BLC signal of 1 bit line in the array is 0, which opens the path of VDDQ to the bit line BL, so that the voltage of the bit line BL is VDDQ; the BLC signals of other bit lines are VDDQ, which closes the path of VDDQ to the bit line BL. 1 word line WL in the array is selected, the voltage of the word line is VDDQ, which opens the NMOS selection tube of all eFuse units in the row; other word lines WL in the array are not selected, the voltage is 0, which closes the NMOS selection tube of all eFuse units in the row. Between the bit line BL with a voltage of VDDQ and the word line WL with a voltage of VDDQ, a VDDQ-to-ground path is formed on the eFuse unit, a programming current flows through the fuse link, and the fuse is programmed by fusing the fuse. The other eFuse units do not form a path between VDDQ and ground, and remain in a non-programmed state.

[0006] If the efuse unit programming output is to be corrected, the conventional method is to add redundant correction bits outside the normal storage bits. By programming these redundant correction bits, the address information where the correction bit is located and the correct value are recorded in the redundant area. If the input address is the address where the error occurs during the read operation, the system will ignore the error value stored at the address and read the preset correct value from the redundant area, which is equivalent to correcting the error value. This correction method uses indirect correction, that is, in order to correct one error bit, it needs to spend several bits of area to store the address and correct value information of the error bit, so it occupies a large redundant area and the correction amount is very limited, the related circuit and layout design are complex, and the reliability is low. SUMMARY

[0007] In the summary section, a series of simplified concepts are introduced, which are simplifications of the prior art in the field. These will be described in further detail in the detailed description section. The summary section of the present application does not mean to attempt to limit the key features and essential technical features of the claimed technical solution, nor does it attempt to determine the protection scope of the claimed technical solution.

[0008] The first technical problem to be solved by the present application is to provide a novel fuse programming unit.

[0009] And a fuse programming circuit, a control circuit of the fuse programming unit and a fuse programming unit array.

[0010] To solve the above technical problems, the fuse programming unit provided by the present application comprises two efuse units and a mode control tube Nsw.

[0011] The first efuse unit comprises:

[0012] A first fuse link1, one end of which constitutes a first connection end of the fuse programming unit, the first connection end being used for connecting a first bit line BL1, and the other end being connected to the drain end of a first MOS N1;

[0013] The first MOS N1 has a source end connected to the ground and a gate end constituting a second connection end of the fuse programming unit, the second connection end being used for connecting a first word line WLo;

[0014] The second efuse unit comprises:

[0015] A second fuse link2, one end of which constitutes a third connection end of the fuse programming unit, the third connection end being used for connecting a second bit line BL2, and the other end being connected to the drain end of a second MOS N2;

[0016] The second MOSN2 has its source end connected to ground, and its gate end forms the fourth connection terminal of the fuse programming unit. The fourth connection terminal is used to connect the second word line WLe.

[0017] The mode control transistor Nsw has its source terminal connected to the line terminal BL2 of the second efuse unit, its drain terminal connected to the source terminal of the first MOSN1, and its gate terminal forming the fifth connection terminal of the fuse programming unit. This fifth connection terminal is used to connect the correction signal REWL.

[0018] Optionally, the fuse programming unit, the first MOSN1, the second MOSN2 and the mode control transistor Nsw are NMOS.

[0019] The fuse programming unit provided by this invention consists of two efuse units and one NMOS transistor, forming a 5-port device (BL1, BL2, REWL, WLo, WLe), as shown below. Figure 3 As shown. The first efuse unit consists of fuse link1 and control transistor N1, while the second efuse unit consists of fuse link2 and control transistor N2. One end of fuse link1 forms the BL1 port of the unit, and the other end of fuse link1 is connected to the drain of control transistor N1 and then to the drain of NMOS transistor Nsw (used for mode control). One end of fuse link2 forms the BL2 port of the unit, and the other end of fuse link2 is connected to the drain of control transistor N2, with the source of N2 grounded. The source of mode control transistor Nsw is connected to the BL2 port of the unit, and its gate forms the REWL port of the unit. The gate of control transistor N1 forms the WLo port of the unit, and the gate of control transistor N2 forms the WLe port of the unit.

[0020] To solve the above-mentioned technical problems, the present invention provides a fuse programming circuit for the fuse programming unit, further comprising:

[0021] The first power control transistor Mp1 has its drain connected to the first bit line BL1, its gate connected to the first programming control signal BLC1, and its source connected to the programming power supply VDDQ.

[0022] The first read control transistor Mn1 has its drain connected to the first bit line BL1, its gate connected to the first read control signal RDR, and its source connected to the first SA module SA1.

[0023] The second power control transistor Mp2 has its drain connected to the second bit line BL2, its gate connected to the second programming control signal BLC2, and its source connected to the programming power supply VDDQ.

[0024] The second read control transistor Mn2 has its drain connected to the second bit line BL2, its gate connected to the second read control signal RD, and its source connected to the second SA module SA2.

[0025] Optionally, in the aforementioned fuse programming circuit, the first power control transistor Mp1 and the second power control transistor Mp2 are PMOS, and the first read control transistor Mn1 and the second read control transistor Mn2 are NMOS.

[0026] The present invention provides a fuse programming circuit, such as... Figure 4 As shown, by Figure 3 The basic unit shown has port BL1 connected to the drain of power control transistor Mp1 and the drain of read control transistor Mn1. The source of Mp1 is connected to the programming power supply VDDQ, and the source of Mn1 is grounded. The gate of Mp1 is connected to the programming control signal BL1C, and the gate of Mn1 is connected to the read control signal RDR. The basic unit has port BL2 connected to the drain of power control transistor Mp2 and the drain of read control transistor Mn2. The source of Mp2 is connected to the programming power supply VDDQ, and the source of Mn2 is grounded. The gate of Mp2 is connected to the programming control signal BL2C, and the gate of Mn2 is connected to the read control signal RD. The REWL, WLo, and WLe ports of the basic unit are connected to their respective control signals.

[0027] To solve the above-mentioned technical problems, the present invention provides a control circuit for the programming circuit of the fuse, comprising:

[0028] Two AND gates and one inverter;

[0029] The first AND gate, whose first input terminal is connected to the second input terminal of the second AND gate, serves as the first input terminal of the control circuit and is connected to the word control signal WL. Its second input terminal is connected to the inverter input terminal and serves as the second input terminal of the control circuit and is connected to the correction control signal RE. Its output terminal serves as the first output terminal of the control circuit.

[0030] The second AND gate has its first input terminal connected to the output terminal of the inverter, and its output terminal serves as the second output terminal of the control circuit.

[0031] The third output terminal of this control circuit is connected to the word control signal WL.

[0032] Optionally, the control circuit of the fuse programming circuit enters the correction mode when the correction control signal RE is 1, the first AND gate outputs a word control signal, and the second AND gate outputs a signal of 0.

[0033] When the correction control signal RE is 0, the system enters normal mode, the first AND gate output signal is 0, and the second AND gate output signal is the word control signal WL.

[0034] The input signal for the second word line WLe of the fuse programming unit is always the word control signal WL.

[0035] The control circuit of the unit of the present invention is as follows: Figure 5As shown, it is composed of 2 AND gates and 1 inverter, and the input signals are WL (word control) and RE (correction control). The signal RE controls the switching between correction mode and normal mode, when RE=1, the correction mode is entered, REWL output is WL, WLo output is 0; when RE=0, the normal mode is entered, REWL output is 0, WLo output is WL, and WLe is always WL.

[0036] To solve the above technical problems, the application provides a fuse programming unit array, which is composed of n rows of fuse programming circuits and n control circuits, each row including at least two fuse programming circuits, and each row including one control circuit, and n≥1.

[0037] Optionally, the fuse programming unit array has a first read operation mode (normal operation mode), which includes: when the nth programming control signal BLCn is 1, all the power supply control tubes MPn between the programming power supply VDDQ and the bit lines BL1-BLn are disconnected.

[0038] The first to nth correction signals REWL1-REWLn are 0, all the efuse units on the odd-numbered column bit lines and the efuse units on the even-numbered column bit lines in the array are disconnected, and the efuse units on the odd-numbered and even-numbered columns are all effective.

[0039] The first word line WLon signal of the nth efuse unit is 1, the second word line WLen signal of the nth efuse unit is 1, the first read control signal RDR is 1, the second read control signal RD is 1, and the first to nth SA modules SA1-SAn read the efuse unit information on all the columns in the row.

[0040] Optionally, the fuse programming unit array has a second read operation mode (redundancy operation mode), which includes: when the nth programming control signal BLCn is 1, all the power supply control tubes MPn between the programming power supply VDDQ and the bit lines BL1-BLn are disconnected.

[0041] The nth correction signal REWLn is 1, and the efuse units on the odd-numbered column bit lines and the efuse units on the even-numbered column bit lines in the row where the nth correction signal REWLn is located are short-circuited.

[0042] The second read control signal RD is 0, all the even-numbered column SA modules are disconnected to the ground, the second word line WLen signal of the row where the nth correction signal REWLn is located is 1, the second word line WLen signal is 0, the control tube located in the even-numbered column in the row where the nth correction signal REWLn is located is turned on, and other control tubes are turned off.

[0043] The first read control signal RDR is 1, the current of the odd column SA module flows through the fuse of the odd column efuse unit in the row where the nth correction signal REWLn is located and the mode control tube Nsw, the even column efuse unit in the row where the nth correction signal REWLn is located is connected to the ground, and the SA module converts the sum of the resistance values of the fuses of the two efuse units into a logic value.

[0044] That is, the odd column efuse unit in each row is used as a storage bit, and the adjacent even column efuse unit is used as the redundancy of the storage bit.

[0045] The fuse programming unit array provided by the application comprises a cell array and a control circuit (Control) as shown in the figure. Figure 6 The cell array is composed of odd / even bit lines BLn and odd / even bit word lines WLon / WLen, mode control lines REWLn, efuse basic units, and PMOS power control tubes Mpn and NMOS read function control tubes Mnn; the control circuit is composed of an AND gate and an inverter, the input control signals are mode control RE and word control WLn, and the output signals are REWLn and WLen, WLon. The cell control signals on each row are WLo1-n and WLe1-n, and REWL1-n. The cells on each column are connected to the same bit line BLn-1 and BLn. The bit line is connected to VDDQ through the power control tube Mp controlled by BLC and connected to the SAn module through the read control tube Mn controlled by RDR and RD.

[0046] The fuse programming unit array of the application comprises two read operation modes: a normal mode and a redundancy mode.

[0047] The read operation schematic diagram in the normal mode is shown in the figure. Figure 8a BLnC=1, all the power control tubes between VDDQ and the bit line BLn are disconnected; REWL1-n=0, the efuse units on all the odd column bit lines in the array are disconnected with the even column bit lines, and the efuse units on the odd / even columns are all valid. WLne=1, WLno=1, RDR=1, RD=1, and SA1-n reads the efuse unit information on all the columns in the row.

[0048] The read operation schematic diagram in the redundancy mode is shown in the figure. Figure 8bAs shown, BLnC=1, all power control tubes between VDDQ and BLn are turned off; REWLn=1, the efuse cells on the odd column bit line and the even column bit line in the row where REWLn is located in the array are shorted; RD=0, all even column SA paths to ground are turned off; WLne=1 / WLno=0 of the row where REWLn is located, the control tubes located in the even column on the row are turned on, and the other control tubes are turned off; RDR=1, the current of the odd column SA flows through the resistance of the odd column efuse cell on the row where REWLn is located, the gating Nsw tube, and the even column efuse cell to the ground, and the SA converts the sum of the fuse resistance values of the two cells into a logic value, that is, the odd column efuse cell in each row is used as a storage bit, and the adjacent even column efuse cell is used as the redundancy of the storage bit, that is, before programming, the two cells are both 0, and the SA output is also 0; after programming, the two cells are both 1, and the SA output is 1; if one of them fails to be 0, but the sum of the two outputs of the SA is still 1, therefore, the application can realize the function that two cells are redundant to each other.

[0049] The fuse programming unit, the programming circuit, the control circuit and the array provided by the application improve the use flexibility of the efuse cell array by modifying the circuit and adding mode control on the basis of the traditional array, and realize that each storage bit has a redundancy correction function, and the circuit and the control mode of the efuse cell array are improved, so that not only the read and write operation of all storage bits can be realized, but also half of the capacity in the storage physical area can be used for storage, and the other half of the capacity can be used as a redundancy correction backup.

[0050] Taking an efuse with a capacity of 8192 bits and a 32-bit output bit width as an example, in the conventional redundancy correction mode, 16 bit capacities are needed to store the address and correction value information of one bit, therefore, for the capacity of 8192 bits, to realize that all storage bits can be corrected, the actual effective capacity of the efuse is only 482 bits, and the remaining capacity is used as a redundancy correction storage area, that is, 482 (actual) + 482x16 (redundancy) = 8194 bits (the total capacity closest to 8192 bits). For the same capacity 8K efuse adopting the array scheme of the application, to realize the redundancy correction capability of all storage capacities, the actual storage space can reach 4096 bits, which is much higher than 482 bits designed by using the conventional redundancy scheme. BRIEF DESCRIPTION OF DRAWINGS

[0051] The drawings accompanying the present invention are intended to illustrate the general manner of construction and / or use of the methods, structures and / or materials used in accordance with the particular example embodiments of the present invention, and to supplement the description of the specification. However, the drawings of the present invention are schematic drawings that are not drawn to scale and can not accurately reflect the precise structural or performance characteristics of any given embodiment, and the drawings of the present invention should not be interpreted as limiting or restricting the scope of the values or attributes encompassed by the example embodiments according to the present invention. The present invention is further described in detail below in conjunction with the specific embodiments and the accompanying drawings:

[0052] Figure 1 is a schematic diagram of a conventional efuse cell.

[0053] Figure 2 is a schematic diagram of a conventional efuse cell array.

[0054] Figure 3 is a schematic diagram of a fuse-fuse programming cell according to the present invention.

[0055] Figure 4 is a schematic diagram of a fuse-fuse programming circuit according to the present invention.

[0056] Figure 5 is a schematic diagram of a control circuit according to the present invention.

[0057] Figure 6 is a schematic diagram of a fuse-fuse programming cell array according to the present invention.

[0058] Figure 7a is a schematic diagram of the programmed state of the efuse cells on the odd column of a fuse-fuse programming cell array according to the present invention during a programming operation.

[0059] Figure 7b is a schematic diagram of the programmed state of the efuse cells on the even column of a fuse-fuse programming cell array according to the present invention during a programming operation.

[0060] Figure 8a is a schematic diagram of a read operation in a conventional mode for a fuse-fuse programming cell array according to the present invention.

[0061] Figure 8b is a schematic diagram of a read operation in a redundant mode for a fuse-fuse programming cell array according to the present invention. DETAILED DESCRIPTION

[0062] The present application is further explained in the following detailed description with reference to the accompanying drawings, wherein: Other advantages and features of the present application will be apparent from the following description of the embodiments, and from the claims. The present application can be embodied in various specific forms without departing from the spirit of the disclosure, which is to be considered limited only by the scope of the appended claims. The above and other examples of the present application are described in the following detailed description with reference to the accompanying drawings, in which: It should be noted that the following examples and features of the examples can be combined with each other, if not contradictory. The exemplary embodiments of the present application can be implemented in various different forms and should not be construed as being limited to the specific examples set forth herein. It should be understood that the examples are provided so that the disclosure is complete and full and to enable the present exemplary embodiments to be carried out in practice. It should be understood that when an element is referred to as being "connected" or "coupled" to another element, the element can be directly connected or coupled to the other element, or intervening elements can be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements present. Like reference numerals refer to like elements throughout the drawings.

[0063] First embodiment;

[0064] Reference Figure 3 As shown in the figure, the present application provides a fuse programming unit, characterized in that, comprising: two efuse units and a mode control tube Nsw;

[0065] The first efuse unit comprises:

[0066] The first fuse link1, one end of which constitutes the first connection end of the fuse programming unit, the first connection end being used for connecting the first bit line BL1, the second end of which is connected to the drain end of the first MOS N1;

[0067] The first MOS N1, the source end of which is connected to the ground, the gate end of which constitutes the second connection end of the fuse programming unit, the second connection end being used for connecting the first word line WLo;

[0068] The second efuse unit comprises:

[0069] The second fuse link2, the first end of which constitutes the third connection end of the fuse programming unit, the third connection end being used for connecting the second bit line BL2, the second end of which is connected to the drain end of the second MOS N2;

[0070] The second MOS N2, the source end of which is connected to the ground, the gate end of which constitutes the fourth connection end of the fuse programming unit, the fourth connection end being used for connecting the second word line WLe;

[0071] a mode control tube Nsw, a source end of which is connected with a line end BL2 of the second efuse unit, a drain end of which is connected with a source end of the first MOS N1, and a gate end of which constitutes a fifth connection end of the fuse link programming unit, the fifth connection end being used for connecting a correction signal REWL;

[0072] The first MOS N1, the second MOS N2 and the mode control tube Nsw are NMOS.

[0073] In addition, it should also be understood that although the terms "first", "second" and the like can be used herein to describe various elements, parameters, components, regions, layers and / or sections, these elements, parameters, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, parameter, component, region, layer or section from another element, parameter, component, region, layer or section. Therefore, the first element, parameter, component, region, layer or section discussed below can also be called the second element, parameter, component, region, layer or section without departing from the teachings of the exemplary embodiments according to the present application.

[0074] A second embodiment;

[0075] Reference Figure 4 As shown, the present application provides a fuse link programming circuit having the fuse link programming unit of the first embodiment, and further comprising:

[0076] a first power control tube Mp1, a drain end of which is connected with the first bit line BL1, a gate end of which is connected with the first programming control signal BLC1, and a source end of which is connected with the programming power supply VDDQ;

[0077] a first read control tube Mn1, a drain end of which is connected with the first bit line BL1, a gate end of which is connected with the first read control signal RDR, and a source end of which is connected with the first SA module SA1;

[0078] a second power control tube Mp2, a drain end of which is connected with the second bit line BL2, a gate end of which is connected with the second programming control signal BLC2, and a source end of which is connected with the programming power supply VDDQ;

[0079] a second read control tube Mn2, a drain end of which is connected with the second bit line BL2, a gate end of which is connected with the second read control signal RD, and a source end of which is connected with the second SA module SA2;

[0080] The first power control tube Mp1 and the second power control tube Mp2 are PMOS, and the first read control tube Mn1 and the second read control tube Mn2 are NMOS.

[0081] A third embodiment;

[0082] Reference Figure 5As shown, the application provides a control circuit for the fuse programming circuit, comprising:

[0083] two AND gates and an inverter;

[0084] a first AND gate, whose first input end and second input end of the second AND gate are connected as the first input end of the control circuit to connect the word control signal WL, whose second input end and input end of the inverter are connected as the second input end of the control circuit to connect the correction control signal RE, and whose output end is as the first output end of the control circuit;

[0085] a second AND gate, whose first input end is connected to the output end of the inverter, and whose output end is as the second output end of the control circuit;

[0086] the third output end of the control circuit is connected to the word control signal WL;

[0087] when the correction control signal RE is 1, the correction mode is entered, the first AND gate outputs the word control signal, and the second AND gate outputs the signal 0;

[0088] when the correction control signal RE is 0, the normal mode is entered, the first AND gate outputs the signal 0, and the second AND gate outputs the word control signal WL;

[0089] the input signal of the second word line WLe of the fuse programming unit is always the word control signal WL.

[0090] the fourth embodiment;

[0091] Reference Figure 6 As shown, the application provides a fuse programming unit array, which is composed of n rows of the fuse programming circuit of the second embodiment and n control circuits of the third embodiment, each row including at least two fuse programming circuits, and each row including one control circuit, n≥1;

[0092] Exemplarily, the fuse programming circuit of the n rows is described, each row having n fuse programming units, which should not be understood as limiting the number of fuse programming units in each row.

[0093] the first end of the n-th fuse programming unit in the n-th row is connected to the n-th first bit line BL1n, the second connection end is connected to the n-th first word line WLon, the third connection end is connected to the n-th second bit line BL2n, the fourth connection end is connected to the n-th second word line WLen, and the fifth connection end is connected to the n-th correction signal REWLn;

[0094] the n-th first power control tube Mp1n, whose drain end is connected to the n-th first bit line BL1n, whose gate end is connected to the n-th programming control signal BLC1n, and whose source end is connected to the programming power supply VDDQ;

[0095] an nth second power control transistor Mp2n, whose drain is connected to an nth second bit line BL2n, whose gate is connected to an nth program control signal BLC2n, and whose source is connected to a program power supply VDDQ;

[0096] an nth first read control transistor Mn1n, whose drain is connected to an nth first bit line BL1n, whose gate is connected to a first read control signal RDR, and whose source is connected to an nth first SA module SA1n;

[0097] an nth second read control transistor Mn2n, whose drain is connected to an nth second bit line BL2n, whose gate is connected to a second read control signal RD, and whose source is connected to an nth second SA module SA2n.

[0098] an nth mode control transistor Nswn, whose source is connected to an nth second bit line BL2n, and whose gate is connected to an nth correction signal REWLn;

[0099] an nth first AND gate, whose first input is connected to an nth word control signal WLn, and whose second input is connected to an nth correction control signal REn, and whose output outputs an nth correction signal REWLn as a first output of the control circuit;

[0100] an nth second AND gate, whose first input is connected to an output of an nth inverter, and whose output outputs an nth first word line signal WL0n as a second output of the control circuit;

[0101] a third output of the control circuit is connected to the nth word control signal WLn, and receives an nth second word line signal WLen.

[0102] Reference Figure 8a As shown, in the first read operation mode, BLnC=1, all power control transistors between VDDQ and bit lines BLn are disconnected; REWL1-n=0, all odd column bit lines in the array are disconnected from even column bit lines, and efuse cells on odd / even columns are all active; WLne=1, WLno=1, RDR=1, RD=1, and SA1-n read efuse cell information on all columns in the row.

[0103] Reference Figure 8bAs shown, the second read operation mode of operation includes: BLnC=1, all power control tubes between VDDQ and BLn are turned off; REWL n =1, the efuse cells on the odd column bit line and the even column bit line of the row where REWL n is located in the array are shorted; RD=0, all even column SA paths to ground are turned off; WLne=1 / WLno=0 of the row where REWL n is located, the control tubes located in the even column on the row are turned on, and the other control tubes are turned off; RDR=1, the current of the odd column SA flows through the resistance of the odd column efuse cell on the row where REWL n is located, the gating Nsw tube, and the even column efuse cell to the ground, and the SA converts the sum of the fuse resistance values of the two cells into a logic value, that is, the odd column efuse cell of each row is used as a storage bit, and the adjacent even column efuse cell is used as the redundancy of the storage bit, that is, before programming, the two cells are both 0, and the SA output is also 0; after programming, the two cells are 1, and the SA output is 1; if one of them fails to be 0, but the sum of the two outputs of the SA is still 1, therefore, the application can realize the function of mutual redundancy of the two cells.

[0104] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0105] The application has been described in detail by the specific embodiments and examples, but these do not constitute limitations on the application. Those skilled in the art can also make many modifications and improvements without departing from the principles of the application, and these should also be considered as the protection scope of the application.

Claims

1. A fuse programming unit, characterized in that... It includes: two efuse units and one mode control tube (Nsw); The first efuse unit includes: The first fuse (link1) has one end forming the first connection terminal of the fuse programming unit, which is used to connect the first bit line (BL1), and its second end is connected to the drain terminal of the first MOS (N1). The first MOS (N1) has its source terminal connected to ground and its gate terminal forming the second connection terminal of the fuse programming unit. The second connection terminal is used to connect the first word line (WLo). The second efuse unit includes: The second fuse (link2) has its first end forming the third connection terminal of the fuse programming unit. The third connection terminal is used to connect to the second bit line (BL2), and its second end is connected to the drain terminal of the second MOS (N2). The second MOS (N2) has its source terminal connected to ground and its gate terminal forming the fourth connection terminal of the fuse programming unit. This fourth connection terminal is used to connect the second word line (WLe). The mode control transistor (Nsw) has its source terminal connected to the second bit line (BL2), its drain terminal connected to the source terminal of the first MOS (N1), and its gate terminal forming the fifth connection terminal of the fuse programming unit. This fifth connection terminal is used to connect the correction signal (REWL).

2. The fuse programming unit as described in claim 1, characterized in that: The first MOS (N1), the second MOS (N2), and the mode control transistor (Nsw) are NMOS transistors.

3. A fuse programming circuit having the fuse programming unit as described in claim 1, characterized in that, Also includes: The first power control transistor (Mp1) has its drain terminal connected to the first bit line (BL1), its gate terminal connected to the first programming control signal (BLC1), and its source terminal connected to the programming power supply (VDDQ). The first read control transistor (Mn1) has its drain connected to the first bit line (BL1), its gate connected to the first read control signal (RDR), and its source connected to the first SA module (SA1). The second power control transistor (Mp2) has its drain connected to the second bit line (BL2), its gate connected to the second programming control signal (BLC2), and its source connected to the programming power supply (VDDQ). The second read control transistor (Mn2) has its drain connected to the second bit line (BL2), its gate connected to the second read control signal (RD), and its source connected to the second SA module (SA2).

4. The fuse programming circuit as described in claim 3, characterized in that: The first power control transistor (Mp1) and the second power control transistor (Mp2) are PMOS, and the first read control transistor (Mn1) and the second read control transistor (Mn2) are NMOS.

5. A control circuit for the programmable circuit of the fuse as described in claim 3, characterized in that, include: Two AND gates and one inverter; The first AND gate has its first input terminal connected to the second input terminal of the second AND gate as the first input terminal of the control circuit, which is connected to the word control signal (WL). Its second input terminal is connected to the inverter input terminal as the second input terminal of the control circuit, which is connected to the correction control signal (RE). Its output terminal is the first output terminal of the control circuit. The second AND gate has its first input terminal connected to the output terminal of the inverter, and its output terminal serves as the second output terminal of the control circuit. The third output terminal of this control circuit is connected to the word control signal (WL).

6. The control circuit of the fuse programming circuit as described in claim 5, characterized in that: When the correction control signal (RE) is 1, the correction mode is entered, the first AND gate outputs the word control signal, and the second AND gate outputs the signal 0; When the correction control signal (RE) is 0, the system enters normal mode, the first AND gate output signal is 0, and the second AND gate output signal is the word control signal (WL). The input signal of the second word line (WLe) of the fuse programming unit is always the word control signal (WL).

7. A fuse programming unit array, characterized in that: It consists of n rows of the fuse programming circuits described in claim 3 and n control circuits described in claim 5, with each row including at least two of the fuse programming circuits and each row including one of the control circuits, where n ≥ 1.

8. The fuse programming unit array as described in claim 7, characterized in that: The first read operation mode includes: when the Xth programming control signal pair is 1, X≥2, disconnect the power control transistor (MPn) between all programming power supplies (VDDQ) and bit lines (BL1~BLn); When the first correction signal to the nth correction signal (REWL1 to REWLn) is 0, the efuse cells on all odd-numbered columns and even-numbered columns in the array are disconnected, and the efuse cells on both odd and even columns are valid. The first word line (WLon) signal of the nth efuse unit pair is 1, the second word line (WLen) signal of the nth efuse unit pair is 1, the first read control signal (RDR) is 1, the second read control signal (RD) is 1, and the first SA module to the second XSA module read the efuse unit information of all columns in this row.

9. The fuse programming unit array as described in claim 7, characterized in that: The second read operation mode includes: when the Xth programming control signal is 1, disconnecting the power control transistor (MPn) between all programming power supplies (VDDQ) and bit lines (BL1~BLn); When the nth correction signal (REWLn) is 1, the efuse cells on the odd-numbered column lines and the efuse cells on the even-numbered column lines of the row containing the nth correction signal (REWLn) in the array are short-circuited. When the second read control signal (RD) is 0, the grounding path of all even-numbered SA modules is turned off. When the second word line (WLen) signal of the row containing the nth correction signal (REWLn) is 1, and the second word line (WLen) signal is 0, the control tube located in the even-numbered column of the row containing the nth correction signal (REWLn) is turned on, and other control tubes are turned off. When the first read control signal (RDR) is 1, the current of the odd-numbered SA module flows through the fuse and mode control transistor (Nsw) of the odd-numbered efuse cell in the row where the nth correction signal (REWLn) is located, and the even-numbered efuse cell in the row where the nth correction signal (REWLn) is located is connected to ground. The SA module converts the sum of the fuse resistance values ​​of the two efuse cells into a logic value. That is, the odd-numbered columns of efuse cells in each row are used as storage bits, and the adjacent even-numbered columns of efuse cells are used as redundancy for that storage bit.

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