Intermediate Substrate and Its Manufacturing Method

Abstract

An interposer substrate and a manufacturing method thereof, including disposing conductive pillars and supports on opposite sides of a coreless layer circuit structure, and covering the conductive pillars and the supports with an insulating layer, so that the rigidity of the interposer substrate meets the requirements through the configuration of the supports and the insulating layer, thereby effectively resisting warping and achieving the application of fine-pitch circuits.

Description

Technical Field

[0001] The present invention relates to a carrier board for semiconductor packaging, and more particularly to an interposer substrate capable of improving reliability and a manufacturing method thereof. Background Art

[0002] With the development of industrial applications, in recent years, the functions required by IC electronic components such as those used in network communication servers, high-speed computing, and AI artificial intelligence have become increasingly diversified, and the performance has become increasingly high. Therefore, it is necessary to integrate and package multiple heterogeneous chips and develop towards large package sizes with high stacking layers, high density, high I / O numbers, and high pin counts.

[0003] Currently, the package sizes of high-end semiconductor component packages are getting larger and larger. For example, the size of the CoWoS (Chip on Wafer on Substrate) type is as large as 54×54 mm 2 , or even 100×100 mm 2 or more, which is much larger than the traditional package size (less than 31×31 mm 2 ). Moreover, the pitches, such as the bump pitch and BGA pitch for flip-chip on the carrier board, are continuously miniaturized, making the package substrates used for flip-chip packaging and the printed circuit boards (PCBs) used for system assembly develop towards fine line pitches, high stacking layers, and high density. For example, the high-density multi-junction (I / O) of the bump pitch for flip-chip in a large-size package structure often has tens of thousands or even more. When the bump pitch for flip-chip is reduced from 150 micrometers (μm) to 130 μm, or even 100 μm, the number of wiring layers of the carrier board will increase, such as from the traditional 8 layers (or 10 layers) to 12 layers, 14 layers, 16 layers, or 22 layers.

[0004] Figure 1 FIG. 21 is a schematic cross-sectional view of an existing large-size package CoWoS type electronic package 1. As Figure 1 shown, on the flip-chip side of a flip-chip package substrate 1a of the electronic package 1, a silicon interposer (Through Silicon interposer, abbreviated as TSI) 1b is provided, and at least one semiconductor chip 12 and / or at least one chipset 12' are disposed on the silicon interposer 1b. One side of the silicon interposer 1b has a plurality of conductive bumps 13 as connection points for flip-chip packaging. The flip-chip package substrate 1a uses the solder pads 101 on its flip-chip side to be bonded to the conductive bumps 13 of the silicon interposer 1b through a plurality of pre-solder bodies 102 to form flip-chip joints 13'.

[0005] In subsequent assembly, the electronic package 1 is placed on a circuit board 1' by means of a plurality of solder balls 14 with the bottom side (i.e., the ball-planting side) of the flip-chip package substrate 1a thereof.

[0006] Currently, the structure of the flip-chip package substrate 1a in the industry can be divided into a substrate with a core layer and a coreless substrate. In the core layer type substrate, a plurality of conductive vias are formed by mechanical drilling and electroplating copper in the core layer to electrically conduct the build-up lines on the upper and lower sides. Therefore, the pitch of its vias is relatively large, so its core layer is not conducive to making fine-pitch and fine-line wiring. On the other hand, the coreless substrate uses a thin dielectric layer for build-up and electrically conducts between layers entirely by laser (Laser) conductive blind vias or conductive pillars, which is easy to make fine-pitch and fine-line wiring. Compared with the core layer type substrate, it has better fine-pitch ability and high-density packaging applications. However, the structure of the coreless substrate is thin, resulting in poor rigidity, so it cannot resist warping. Therefore, the coreless substrate is not suitable for large-size electronic packages 1.

[0007] Therefore, due to the better structural strength and rigidity of the core layer type substrate and its ability to resist warping, the industry currently selects the core layer type substrate as the flip-chip package substrate 1a of the large-size electronic package 1. In the early production of the core layer type substrate, a substrate composed of glass fiber and epoxy resin, such as BT (Bismaleimide Triazine) or FR5, etc., is used as the core layer 10, and then the conductive via 100 process is carried out thereon, such as mechanical drilling, laser drilling or double-cone blind holes and other hole-forming steps, and then a conductive layer is electroplated in the holes or a filler 100' is filled, and then double-sided build-up is carried out to complete.

[0008] However, the existing flip-chip package substrate 1a with a core layer 10 applied to high-integration / large layout size will have obvious disadvantages. For example, the core layer 10 uses a substrate composed of glass fiber and epoxy resin. Since the coefficient of thermal expansion (CTE) of the materials between the layers of the flip-chip package substrate 1a is inconsistent with that of the silicon interposer 1b, the semiconductor chip 12, the chipset 12', and the encapsulation material 1c (which is used to encapsulate the silicon interposer 1b, the semiconductor chip 12, and the chipset 12'), warping is likely to occur during encapsulation, resulting in poor connection between it and the silicon interposer 1b, or during soldering, poor connection will occur between it and the circuit board 1'. More seriously, due to stress, delamination between the semiconductor chip 12 and / or the chipset 12' and the carrier board or its own cracking may easily occur during reliability verification, or delamination between the carrier board layers may cause electrical failure of the semiconductor chip 12 and / or the chipset 12'.

[0009] Furthermore, when applying an early core-type substrate to the flip-chip package substrate 1a with a large panel size, its rigidity is still insufficient, and the support stress is insufficient, resulting in poor flatness. Therefore, when it is assembled onto the circuit board 1', it is likely to affect the product quality and the stability of reliability due to stress.

[0010] Therefore, the current industry practice is to thicken the thickness h of the core layer 10. For example, the thickness h is increased from the original 0.8 millimeters (mm) to 1.2 mm (or more than 1.6 mm) to increase the rigidity strength of the flip-chip package substrate 1a and thus improve the warping problem. However, this results in the following more disadvantages:

[0011] First, the pitch of each of the conductive vias 100 cannot be reduced. Specifically, the result of thickening the core layer 10 causes the end face sizes of the plurality of conductive vias 100 to become larger under traditional technology. For example, when the thickness h is 0.8 mm, the via hole diameter w and the via pitch are typically 150 micrometers (μm) and more than 300 μm. If the thickness h is 1.2 mm, the diameter w is increased to more than 200 micrometers (i.e., the diameter w becomes larger), and thus the pitch of the plurality of conductive vias 100 must become larger. As a result, the number of conductive vias 100 per unit area becomes smaller, which is not conducive to fabricating high-density fine-pitch wiring. Therefore, when applied to the need for more contacts (I / O), the size of the flip-chip package substrate 1a must be increased, making it more difficult to control the board warping and greatly increasing the cost.

[0012] Second, the processing cost and difficulty of the conductive vias 100 are higher as the core layer thickens. Specifically, the result of thickening the core layer 10 causes the plurality of conductive vias 100 to become deeper, thus increasing the difficulty of electroplating in the deeper conductive vias 100 and the difficulty of smoothly filling the filler 100' into the deeper conductive vias 100, and at the same time increasing the processing cost.

[0013] On the other hand, with the development of the high stacking layers and high density of existing large-size electronic packages 1, the manufacturing processes of the flip-chip package substrate 1a and the circuit board 1' have become increasingly complex, and the requirement for precision has become higher. As a result, the processing difficulty of the circuit board 1' has also become higher. Therefore, in the processing process of the large-size packaged circuit board 1', problems such as low processing yield and increased cost will be faced. Moreover, such a large-panel-size packaged system assembly structure will have serious warpage problems, thus affecting the quality and reliability of the end product.

[0014] For example, for the circuit board 1', when the pitch t of the solder balls 14 on the package substrate 1a is reduced from 1.0 mm to 0.8 - 0.7 mm, or even 0.6 - 0.4 mm, the number of wiring layers of the circuit board 1' needs to be significantly increased (such as from 16 layers to 22 layers, or even more than 30 layers) to meet the requirements of multiple contacts. At the same time, the line width / line pitch (L / S) of the wiring on the circuit board 1' also needs to be reduced accordingly (such as being refined from the current mass-produced L / S of 75 / 75 μm for rigid PCB boards to 25 / 25 μm). Therefore, based on the general layout size of the circuit board 1' being quite large (such as a rectangular layout with side lengths of 10 inches to 30 inches), if the number of wiring layers of the circuit board 1' increases to 22 layers (or even more than 30 layers), originally, only fine lines and high-density wiring need to be locally set in the component area A of the large-sized electronic package 1 to meet the requirements. However, in the production of the circuit board 1', in fact, the entire surface of the circuit board 1' is processed with fine lines instead of only processing the fine lines in a local area. Therefore, in the case of processing fine lines on the entire board surface on the one hand and increasing the number of layers on the other hand, it will cause difficulties in processing the traditional circuit board 1', and the yield rate is extremely low, resulting in a significant increase in cost.

[0015] In addition, as in the prior art of the TWI308385 patent, its substrate adopts a thin core layer (such as reference numeral 230) technology, plus a reinforcement board (such as reference numeral 240), to achieve the production of high-density wiring and solve the problem of warping and deformation of the circuit lines. However, it has obvious disadvantages, as described below:

[0016] First, since it still has a core layer, via holes need to be made, resulting in limited wiring density of the substrate.

[0017] Second, the reinforcement board is formed on a single side of the overall structure, so there is an asymmetry problem, and thus it cannot be applied to large-sized packages.

[0018] Third, although the reinforcement board can be thickened to achieve the purpose of anti-warpage, it also causes the conductive path (such as reference numeral 252) to become longer, thus increasing the difficulty of its processing operation (such as reference numeral 252), and the pitch is not easily miniaturized. More seriously, reliability problems will occur. For example, a long and deep conductive channel (such as reference numeral 250) will cause a large amount of solder to be required when connecting external electronic components such as chips, and reliability problems such as voids and poor adhesion are likely to occur.

[0019] Fourth, the reinforcement board is first coated with an insulating material, so in the state of high-density pores (such as at reference numeral 246), it is easy to have uneven or poor coating, thus causing concerns about short circuits in electrical connections.

[0020] Therefore, how to overcome the various problems of the above prior art has actually become a difficult problem that the industry urgently needs to overcome. Summary of the Invention

[0021] In view of the above-mentioned deficiencies of the prior art, the present invention provides an interposer substrate and a manufacturing method thereof, which can effectively resist warping and achieve the application of fine-pitch circuits.

[0022] The interposer substrate of the present invention includes: a coreless layer circuit structure having opposite first and second surfaces, and both the first surface and the second surface include exposed circuit layers; a first insulating layer disposed on the first surface of the coreless layer circuit structure; a plurality of first conductive posts having opposite first and second end faces and embedded in the first insulating layer, wherein the first end face is bonded and electrically connected to the circuit layer on the first surface of the coreless layer circuit structure, and the second end face is exposed from the first insulating layer; a first support member which is a plate body provided with a plurality of mesh openings, having opposite first and second sides and embedded in the first insulating layer, wherein the first side faces the first surface of the coreless layer circuit structure, and the second side is exposed from the first insulating layer, and the plurality of first conductive posts are located in at least one mesh opening of the first support member; a second insulating layer disposed on the second surface of the coreless layer circuit structure; a plurality of second conductive posts having opposite first and second end faces and embedded in the second insulating layer, wherein the first end face is bonded and electrically connected to the circuit layer on the second surface of the coreless layer circuit structure, and the second end face is exposed from the second insulating layer; a second support member which is a plate body provided with a plurality of mesh openings, having opposite first and second sides and embedded in the second insulating layer, and the first side is disposed on the second surface of the coreless layer circuit structure, and the plurality of second conductive posts are located in at least one mesh opening of the second support member; and a second insulating layer disposed on the second surface of the coreless layer circuit structure to cover the plurality of second conductive posts and the second support member, and the second end faces of the plurality of second conductive posts are exposed from the second insulating layer.

[0023] In the above-mentioned interposer substrate, the first conductive post and / or the second conductive post includes a plurality of stacked columnar bodies.

[0024] In the above-mentioned interposer substrate, there is an interval of the first insulating layer between the first side of the first support member and the circuit layer on the first surface of the coreless layer circuit structure, or the first side of the first support member is directly bonded to the circuit layer on the first surface of the coreless layer circuit structure.

[0025] In the above-mentioned interposer substrate, there is an interval of an adhesive material between the first side of the second support member and the circuit layer on the first surface of the coreless layer circuit structure, or the first side of the second support member is directly bonded to the circuit layer on the second surface of the coreless layer circuit structure.

[0026] In the foregoing interposer substrate, the second side of the first support member is exposed from the first insulating layer, and / or the second side of the second support member is exposed from the second insulating layer. Further, a heat sink may be further disposed on the surface where the first support member or the second support member is exposed.

[0027] In the foregoing interposer substrate, the first support member and / or the second support member includes a plurality of laminate bodies that are stacked and each provided with a plurality of mesh openings.

[0028] In the foregoing interposer substrate, the plurality of first conductive posts are respectively located in the respective mesh openings of the first support member, and / or the plurality of second conductive posts are respectively located in the respective mesh openings of the second support member.

[0029] In the foregoing interposer substrate, the plurality of first conductive posts and the first support member are made of copper or a copper alloy.

[0030] In the foregoing interposer substrate, the plurality of second conductive posts and the second support member are made of copper, a copper alloy, stainless steel, or a ferro-nickel alloy.

[0031] In the foregoing interposer substrate, the first support member and / or the second support member are made of a metal material, an organic resin material, a plastic steel material, or a ceramic insulating material.

[0032] In the foregoing interposer substrate, the side of the second end surface of the plurality of first conductive posts serves as a die placement side for bonding a chip or an interposer in a flip-chip manner, and the side of the second end surface of the plurality of second conductive posts serves as a circuit board side for bonding a circuit board.

[0033] The present invention further provides a method for manufacturing an interposer substrate, comprising: providing a carrier; forming a plurality of first conductive posts on the carrier by patterned electroplating and forming a plate-shaped first support member including a plurality of mesh openings, such that the plurality of first conductive posts are located in at least one of the mesh openings of the first support member; forming a first insulating layer on the carrier to cover the plurality of first conductive posts and the first support member, and performing a planarization process on the first insulating layer to expose one end surface of the plurality of first conductive posts on the surface of the first insulating layer; forming a coreless layer circuit structure having a plurality of circuit layers on the first insulating layer, the plurality of first conductive posts and the first support member by an additive process (semi-additive process SAP), such that at least one of the circuit layers of the coreless layer circuit structure is bonded to one end surface of the plurality of first conductive posts; forming a plurality of second conductive posts on the coreless layer circuit structure by patterned electroplating and forming a plate-shaped second support member including a plurality of mesh openings, such that the plurality of second conductive posts are located in at least one of the mesh openings of the second support member, and one end surface of the plurality of second conductive posts is bonded to one of the circuit layers on the surface of the coreless layer circuit structure; forming a second insulating layer on the coreless layer circuit structure to cover the plurality of second conductive posts and the second support member, and performing a planarization process on the second insulating layer to expose the other end surface of the plurality of second conductive posts on the surface of the second insulating layer; and removing the carrier to expose the other end surface of the plurality of first conductive posts on the first insulating layer.

[0034] The present invention further provides a method for manufacturing an interposer substrate, including: providing a carrier, the carrier being a plate body and being made of copper, copper alloy, stainless steel, or iron-nickel alloy; forming a coreless layer circuit structure with multiple circuit layers on the carrier by an additive process (semi-additive technology SAP), and bonding one of the circuit layers on the surface of the coreless layer circuit structure to the carrier; forming multiple first conductive posts and a plate-shaped first support member including multiple mesh-shaped openings on the coreless layer circuit structure by patterned electroplating, so that the multiple first conductive posts are located in at least one of the mesh-shaped openings of the first support member, and one end surface of the multiple first conductive posts is bonded to one of the circuit layers on the surface of the coreless layer circuit structure; forming a first insulating layer on the coreless layer circuit structure to cover the multiple first conductive posts and the first support member, and performing a planarization process on the first insulating layer to expose the other end surfaces of the multiple first conductive posts on the surface of the first insulating layer; etching the carrier by a patterned etching process to form multiple second conductive posts and a second support member, wherein the second support member is formed as a plate body including multiple mesh-shaped openings, and the multiple second conductive posts are located in at least one of the mesh-shaped openings of the second support member, and one of the circuit layers on the surface of the coreless layer circuit structure bonds one end surface of the multiple second conductive posts; and forming a second insulating layer on the coreless layer circuit structure to cover the multiple second conductive posts and the second support member, and performing a planarization process on the second insulating layer to expose the other end surfaces of the multiple second conductive posts on the surface of the first insulating layer.

[0035] In the foregoing manufacturing method, one side of the first support member is exposed outside the first insulating layer, and / or one side of the second support member is exposed outside the second insulating layer. Further, a heat dissipating member is formed on the exposed surface of the first support member or the second support member.

[0036] In the foregoing manufacturing method, the multiple first conductive posts and the first support member are simultaneously formed on the carrier or the circuit layer of the coreless layer circuit structure by patterned electroplating, and the first conductive posts are formed as single-layer columns or multiple stacked column bodies, and / or the first support member is formed as a single-layer plate body or multiple stacked plate bodies.

[0037] In the foregoing manufacturing method, first, the plurality of first conductive posts are formed on the carrier or the circuit layer of the coreless layer circuit structure by patterned electroplating, and then the first support member is bonded to the carrier or the circuit layer of the coreless layer circuit structure by an insulating adhesive bonding method; alternatively, first, the first support member is bonded to the carrier or the circuit layer of the coreless layer circuit structure by an insulating adhesive bonding method, and then the plurality of first conductive posts are formed on the carrier or the circuit layer of the coreless layer circuit structure by patterned electroplating; and, the first conductive posts are formed as single-layer columns or a plurality of stacked column bodies, and / or the first support member is formed as a single-layer plate body with a plurality of mesh openings or a plurality of stacked plate bodies.

[0038] In the foregoing manufacturing method, if the first conductive posts and the second conductive posts are directly formed by electroplating, better reliability than that of the laser blind vias in the conventional (such as the TWI308385 patent) can be obtained.

[0039] In the first embodiment of the foregoing manufacturing method, the plurality of second conductive posts and the second support member are simultaneously formed on the circuit layer of the coreless layer circuit structure by patterned electroplating, and the second conductive posts are formed as single-layer columns or a plurality of stacked column bodies, and / or the second support member is formed as a single-layer plate body or a plurality of stacked plate bodies.

[0040] In the first embodiment of the foregoing manufacturing method, first, the plurality of second conductive posts are formed on the circuit layer of the coreless layer circuit structure by patterned electroplating, and then the second support member is bonded to the circuit layer of the coreless layer circuit structure by an adhesive bonding method; alternatively, first, the second support member is bonded to the circuit layer of the coreless layer circuit structure by an adhesive bonding method, and then the plurality of second conductive posts are formed on the circuit layer of the coreless layer circuit structure by patterned electroplating; and, the second conductive posts are formed as single-layer columns or a plurality of stacked column bodies, and / or the second support member is formed as a single-layer plate body or a plurality of stacked plate bodies.

[0041] In the foregoing manufacturing method, the plurality of first conductive posts are respectively located in the respective mesh openings of the first support member, and / or the plurality of second conductive posts are respectively located in the respective mesh openings of the second support member.

[0042] As can be seen from the above, in the interposer substrate and its manufacturing method of the present invention, the fine-pitch (such as 60 to 100 microns, far better than the 300 microns of the through-hole pitch of the existing core layer) and fine-line wiring for interlayer conduction are easily fabricated by the coreless layer circuit structure to meet the requirements of high I / O numbers and high wiring density for large-size packaging.

[0043] Furthermore, in the present invention, the core layer of the core layer substrate in the prior art is split into support members and disposed on one or both sides of the core layer-free circuit structure, so as to form a better sandwich structure. Through the configuration of the first support member and the second support member with the first insulating layer and the second insulating layer, and by utilizing the characteristics of good rigidity and appropriate thickening of the support members, the rigidity of the interposer substrate meets the requirements, thus effectively resisting warping. Therefore, when the interposer substrate is used for chip component packaging operations, the quality, reliability and yield can be improved, overcoming the difficulties of the prior art.

[0044] In addition, by using the core layer-free circuit structure, there is no need to perform the conductive via process. Therefore, compared with the prior art, the present invention does not have the deficiencies described in the core layer prior art.

[0045] In addition, with the core layer-free circuit structure, the areas of the circuit board that require fine circuit wiring design can be centrally accommodated and designed in the core layer-free circuit structure, and the spacing between the second conductive posts can be widened. There is no need to perform high-density processing of fine circuits on the circuit board. Therefore, compared with the prior art, the present invention can solve the problems of existing circuit boards. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] Figure 1 It is a schematic cross-sectional view of a CoWoS-type electronic package for large-size packaging in the prior art.

[0047] Figures 2A to 2F It is a schematic cross-sectional view of the manufacturing method of the first embodiment of the interposer substrate of the present invention.

[0048] Figure 2A-1 Corresponding to Figure 2A Partial perspective view.

[0049] Figure 2A-2 Corresponding to Figure 2A Another embodiment.

[0050] Figure 2B-1 Corresponding to Figure 2B Another embodiment.

[0051] Figure 2C-1 Corresponding to Figure 2C Another embodiment.

[0052] Figure 2D-1 Corresponding to Figure 2D Another embodiment.

[0053] Figure 2E-1 , Figure 2E-2 And Figure 2E-3 Corresponding to Figure 2E Schematic cross-sectional views of different embodiments.

[0054] Figure 2F-1 ,Figure 2F-2 and Figure 2F-3 are cross-sectional schematic diagrams of other embodiments corresponding to Figure 2F .

[0055] Figure 2F-4 are corresponding to Figure 2F-3 partial perspective schematic diagrams of

[0056] Figure 2G , 2G-1 and Figure 2G-2 are cross-sectional schematic diagrams of different embodiments of the application of the interposer substrate of the present invention.

[0057] Figures 3A to 3E is a cross-sectional schematic diagram of the manufacturing method of the second embodiment of the interposer substrate of the present invention.

[0058] Figure 3B-1 is corresponding to Figure 3B another embodiment of

[0059] Figure 3C-1 is corresponding to Figure 3C another embodiment of

[0060] Figure 3D-1 and Figure 3D-2 are corresponding to Figure 3D different embodiments of

[0061] Figure 3E-1 , Figure 3E-2 and Figure 3E-3 are corresponding to Figure 3E cross-sectional schematic diagrams of other embodiments of

[0062] Figures 4A to 4D is a cross-sectional schematic diagram of the manufacturing method of the third embodiment of the interposer substrate of the present invention.

[0063] Figure 4B-1 is corresponding to Figure 4B another embodiment of

[0064] Figure 4D-1 is another embodiment corresponding to Figure D.

[0065] Figures 5A to 5D is a cross-sectional schematic diagram of the manufacturing method of the fourth embodiment of the interposer substrate of the present invention.

[0066] Figure 5A-1 is corresponding to Figure 5A partial perspective schematic diagrams of

[0067] Figure 5D-1 , Figure 5D-2 and Figure 5D-3 are corresponding to Figure 5D cross-sectional schematic diagrams of other embodiments of

[0068] Figure 6 Cross-sectional schematic diagram of the fifth embodiment of the interposer substrate of the present invention.

[0069] Among them, the reference numerals are explained as follows:

[0070] 1, 9, 9’, 9”: Electronic package

[0071] 1’, 9a: Circuit board

[0072] 1a: Flip chip package substrate

[0073] 1b, 91: Silicon interposer

[0074] 1c: Encapsulation material

[0075] 10: Core layer

[0076] 10a, 10b: Circuit layer

[0077] 100: Conductive via

[0078] 100’: Filling material

[0079] 101: Solder pad

[0080] 102: Pre-solder body

[0081] 12, 92: Semiconductor chip

[0082] 12’: Chipset

[0083] 121: Solder bump

[0084] 13, 93: Conductive bump

[0085] 13’: Flip chip contact

[0086] 14, 94: Solder ball

[0087] 2, 2a, 2b, 2c, 3, 3a, 3b, 3c, 4, 4a, 5, 5a, 5b, 5c, 6: Interposer substrate

[0088] 20, 40: Carrier

[0089] 21, 31, 61: First conductive pillar

[0090] 21a, 31a, 61a: First end face

[0091] 21b, 31b, 61b: Second end face

[0092] 22, 32, 32’, 52, 52’, 52”: First support

[0093] 22a, 32a, 52a: First side

[0094] 22b, 32b, 52b: Second side

[0095] 220, 520, 520’, 520”: Opening

[0096] 221: Mesh hole

[0097] 222: Bonding layer

[0098] 23, 33: First insulating layer

[0099] 24: Coreless layer line structure

[0100] 24a: First surface

[0101] 24b: Second surface

[0102] 240: Dielectric layer

[0103] 241, 241’, 241”: Circuit layer

[0104] 242: Conductive blind hole

[0105] 25, 25’, 25”, 35, 35’, 45, 65: Second conductive column

[0106] 25a, 35a, 45a, 65a: First end face

[0107] 25b, 35b, 45b, 65b: Second end face

[0108] 26, 36, 46, 56, 56’, 56”: Second support

[0109] 26a, 36a, 46a, 56a: First side

[0110] 26b, 36b, 46b, 56b: Second side

[0111] 260, 560, 560’, 560”: Opening

[0112] 261: Mesh hole

[0113] 262: Bonding layer

[0114] 27, 37: Second insulating layer

[0115] 28: Heat sink

[0116] 280: Adhesive material

[0117] 281: Window

[0118] 311, 611: First cylinder

[0119] 312, 612: Second cylinder

[0120] 321: First plate body

[0121] 322: Second plate body

[0122] 331: First insulation layer

[0123] 332: Second insulation layer

[0124] 351, 651: Third column

[0125] 352, 652: Fourth column

[0126] 361: Third plate

[0127] 362: Fourth plate

[0128] 371: Third insulation layer

[0129] 372: Fourth insulation layer

[0130] 610, 650: Pad

[0131] 911: Circuit re - distribution layer

[0132] 95: Contact point

[0133] A, B: Region

[0134] C: Contact point area

[0135] d1, d2, h: Thickness

[0136] h1: Height

[0137] L: Cutting path

[0138] S1: Die - mounting side

[0139] S2: Circuit board bonding side

[0140] t, t1, t2: Spacing

[0141] w: Hole diameter. Detailed implementation manners

[0142] The following describes the implementation manners of the present invention through specific embodiments. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification.

[0143] It should be noted that the structures, proportions, sizes, etc. shown in the drawings of this specification are only used to cooperate with the content disclosed in the specification for the understanding and reading of those skilled in the art, and are not used to limit the conditions under which the present invention can be implemented. Therefore, they do not have a substantial technical meaning. Any modification of the structure, change in the proportional relationship, or adjustment of the size, without affecting the effects that the present invention can produce and the purposes that can be achieved, should still fall within the scope that can be covered by the technical content disclosed in the present invention. At the same time, terms such as "upper", "first", "second", "third", "fourth", "one", etc. cited in this specification are only for the convenience of clear narration and are not used to limit the scope of implementation of the present invention. The change or adjustment of their relative relationship, without substantial change in the technical content, should also be regarded as the scope within which the present invention can be implemented.

[0144] Figures 2A to 2G It is a schematic cross-sectional view of the manufacturing method of the first embodiment of the interposer substrate 2 for flip-chip packaging of the present invention.

[0145] As Figure 2A shown, a plurality of first conductive posts 21 and at least one first support member (stiffener) 22 as a rigid layer are formed on a carrier 20.

[0146] In this embodiment, the first conductive post 21 is formed as a single-layer columnar body, such as a metal column of copper, copper alloy, etc., and the first support member 22 is a single-layer plate body (such as Figure 2A-1A conductive substrate, a semiconductor substrate, or an insulating substrate (as shown), so that the plurality of first conductive posts 21 are located in at least one of the mesh openings (such as the opening 220) of the first support member 22, which can be used to bond a silicon interposer, a semiconductor chip, or a passive component, etc. For example, the first conductive posts 21 are grown from the surface of the carrier 20 by lithographic patterning followed by electroplating, deposition, or other methods, and the first support member 22 is an insulating substrate made of rigid ceramic, organic resin, or other suitable materials, etc., which is fixed to the carrier 20 by a bonding layer 222 such as an adhesive in a pasting manner or a thermal pressing (or vacuum pressing) manner. Specifically, the conductive substrate of the first support member 22 can be stainless steel or a metal conductor made of materials such as iron, nickel, copper, aluminum, magnesium, zinc, or their alloys. When the first support member 22 is formed of the organic resin, the material can be a substrate containing glass fiber and organic resin, such as BT (Bismaleimide Triazine), FR4, or FR5, etc., or a high-rigidity glass-fiber-free but filled (such as SiO2) organic substrate; or, the material forming the organic resin can be an epoxy resin material containing a high proportion of fillers, such as epoxy molding compound (abbreviated as EMC); even more, the material forming the organic resin can be a high-strength plastic such as plastic steel.

[0147] Furthermore, the first conductive posts 21 have opposite first end faces 21a and second end faces 21b, and the first support member 22 has opposite first sides 22a and second sides 22b, so that the first conductive posts 21 are bonded to the carrier 20 with their second end faces 21b, and the first support member 22 is bonded to the carrier 20 with its second sides 22b. For example, the plurality of first conductive posts 21 can be formed on the carrier 20 by patterned electroplating first, and then the first support member 22 having a plurality of mesh openings (such as the opening 220, mesh holes 221) is bonded to the carrier 20 by an adhesive bonding method. Or, alternatively, the first support member 22 having a plurality of mesh openings (such as the opening 220, mesh holes 221) can be bonded to the carrier 20 by an insulating adhesive bonding method first, and then the plurality of first conductive posts 21 are formed on the carrier 20 by patterned electroplating. It should be understood that the plurality of first conductive posts 21 are located in at least one of the mesh openings (such as the opening 220, mesh holes 221).

[0148] Or, as Figure 2A-2As shown, the plurality of first conductive posts 21 and the first support member 22 can also be formed on the carrier 20 by patterned electroplating; wherein, the plurality of first conductive posts 21 are formed as single-layer columns, and the first support member 22 is formed as a plate body having a plurality of mesh openings (such as openings 220 and mesh holes 221). It should be understood that the plurality of first conductive posts 21 are located in at least one of the mesh openings (such as the openings 220 and mesh holes 221).

[0149] In addition, in the preliminary process of manufacturing the first support member 22, if a metal plate such as stainless steel, copper alloy, aluminum alloy, iron-nickel alloy, etc. is selected, then for the process of its mesh openings, a photoresist is first laid, then exposed and developed, and then a chemically etched method is used to form a mesh plate body with regular or irregular, the same or different opening sizes. On the other hand, if an organic resin plate, plastic steel plate or ceramic insulating plate is selected and it is in a mesh shape, then the preferred process for its mesh openings is to form a plate body with regular or irregular, the same or different opening sizes in a mesh shape by laser, mechanical drilling, mechanical forming (NCRouter), plasma etching or chemical etching methods.

[0150] In addition, the thickness d1 of the first support member 22 (the bonding layer 222 is extremely thin and can be ignored) can be designed according to requirements, and the height h1 of the first conductive post 21 is slightly higher than or equal to the thickness d1 of the first support member 22.

[0151] As Figure 2B shown, a first insulating layer 23 is formed on the carrier 20 so that the first insulating layer 23 covers the plurality of first conductive posts 21 and the first support member 22, and fills the openings 220 and mesh holes 221 of the first support member 22, so that the plurality of first conductive posts 21 and the first support member 22 are embedded in the first insulating layer 23, and then a leveling process is performed on the first insulating layer 23 to expose the first end face 21a of the first conductive post 21 on the surface of the first insulating layer 23. Therefore, by filling the openings 220 and mesh holes 221 of the first support member 22 with the first insulating layer 23, the bonding force between the first insulating layer 23 and the first conductive posts 21 and the first support member 22 can be further increased.

[0152] In this embodiment, the material for forming the first insulating layer 23 is an organic photosensitive dielectric material or an organic non-photosensitive dielectric material (such as epoxy resin, that is, epoxy). For example, the types of the organic dielectric materials can include soldermask, ABF (Ajinomoto Build-up Film), prepreg, MoldingCompound, Epoxy Molding Compound (EMC) rich in fillers, Primer, etc.

[0153] Furthermore, the planarization process includes grinding, chemical etching, laser ablation, sandblasting, or plasma etching to remove part of the material of the first conductive pillar 21 and part of the material of the first insulating layer 23, so that the surface of the first insulating layer 23 is flush with the first end face 21a of the first conductive pillar 21, and the first end face 21a of the first conductive pillar 21 is exposed on the top surface of the first insulating layer 23.

[0154] In addition, the first support 22 is embedded in the first insulating layer 23. It should be understood that the first support 22 may or may not be exposed on the top surface of the first insulating layer 23 as required. For example, the surface of the first side 22a of the first support 22 is flush with the surface of the first insulating layer 23, so that the surface of the first side 22a of the first support 22 is exposed on the surface of the first insulating layer 23 (as Figure 2B-1 shown).

[0155] As Figure 2C shown, a coreless circuit structure 24 having at least one circuit layer 241, 241', 241'' is formed on the first insulating layer 23, the plurality of first conductive pillars 21, and the first support 22 by an additive process (semi-additive process, i.e., Semi-additive Process, abbreviated as SAP), so that one of the circuit layers 241' of the coreless circuit structure 24 is bonded to the first end face 21a of the first conductive pillar 21, and if necessary, one of the circuit layers 241' of the coreless circuit structure 24 can also be bonded to the first side 22a of the first support 22 (as Figure 2C-1 shown).

[0156] In this embodiment, the coreless circuit structure 24 has a plurality of dielectric layers 240, a plurality of circuit layers 241, 241', 241'' provided on the dielectric layers 240, and a plurality of conductive blind vias (or conductive pillars) 242 provided in the dielectric layers 240 and electrically connecting the respective circuit layers 241, 241', 241'', and the circuit layer 241' is electrically connected to the first conductive pillar 21. For example, the circuit layers 241, 241', 241'' are processed by semi-additive process technology, such as existing lithography patterning and electroplating processes, and the dielectric material of the dielectric layer 240 is, for example, prepreg (PP) such as ABF, photosensitive dielectric material, polybenzoxazole (PBO), polyimide (PI), BT, FR5, molding compound, film-like EMC, or others.

[0157] Furthermore, the material of the first insulating layer 23 may be the same as or different from the material of the dielectric layer 240. For example, the materials of the first insulating layer 23 and the dielectric layer 240 may be adjusted according to the requirements of CTE matching to meet the requirements of low CTE.

[0158] In addition, the coreless layer circuit structure 24 has opposite first and second surfaces 24a and 24b, and both the first surface 24a and the second surface 24b include exposed circuit layers 241', 241''. The circuit layer 241' exposed on the first surface 24a of the coreless layer circuit structure 24 is combined with the first end face 21a of the first conductive column 21. And as required, the circuit layer 241' exposed on the first surface 24a of the coreless layer circuit structure 24 can be combined with the first side 22a of the first support member 22 (as Figure 2C-1 shown).

[0159] As Figure 2D shown, a plurality of second conductive columns 25 are formed by patterned electroplating on the second surface 24b of the coreless layer circuit structure 24, and a plate-like second support member 26 including a plurality of mesh openings (defining larger openings 260 and smaller mesh holes 261) is formed (as the structure shown in Figure 2A-1 ). So that the plurality of second conductive columns 25 are located in at least one of the mesh openings (such as the openings 260 and mesh holes 261) of the second support member 26, and the second conductive columns 25 are electrically connected to the coreless layer circuit structure 24. And as required, the coreless layer circuit structure 24 can be electrically connected to the second support member 26.

[0160] In this embodiment, the second conductive column 25 has opposite first and second end faces 25a and 25b, so that the plurality of second conductive columns 25 are combined and electrically connected to the circuit layer 241'' on the second surface 24b of the coreless layer circuit structure 24 with their first end faces 25a. And the second support member 26 has opposite first and second sides 26a and 26b, so that the second support member 26 is disposed on the second surface 24b of the coreless layer circuit structure 24 with its first side 26a.

[0161] In this embodiment, the second support member 26 can be fixed to the coreless layer circuit structure 24 by means of a bonding layer 262 such as a glue material in a pasting manner or a hot pressing (or vacuum pressing) manner. For example, the plurality of second conductive posts 25 can be formed by patterned electroplating on the circuit layer 241” exposed on the second surface 24b of the coreless layer circuit structure 24 (the height of the second conductive posts 25 can be adjusted according to requirements), and then the second support member 26 having a plurality of mesh openings (such as openings 260 and mesh holes 261) can be bonded to the second surface 24b of the coreless layer circuit structure 24 by an insulating adhesive bonding method. Alternatively, the second support member 26 having a plurality of mesh openings (such as openings 260 and mesh holes 261) can be first bonded to the circuit layer 241” exposed on the second surface 24b of the coreless layer circuit structure 24 by an insulating adhesive bonding method, and then the plurality of second conductive posts 25 can be formed by patterned electroplating on the circuit layer 241” exposed on the second surface 24b of the coreless layer circuit structure 24. It should be understood that the plurality of second conductive posts 25 are located in at least one of the mesh openings (such as the openings 260 and mesh holes 261).

[0162] In this embodiment, the second conductive post 25 is made of copper or a copper alloy, and the second support member 26 is a conductive substrate, a semiconductor substrate or an insulating substrate in the shape of a plate body having an opening 260 and mesh holes 261. For example, the conductive substrate of the second support member 26 can be made of copper, a copper alloy, stainless steel, or a metal conductor containing materials such as iron, nickel, copper, aluminum, magnesium, zinc or their alloys. When the second support member 26 is formed of the organic resin, its material can be a substrate containing glass fiber and organic resin, such as BT (Bismaleimide Triazine), FR4 or FR5, or an organic substrate without glass fiber but containing a filler (such as SiO2) with high rigidity; or the second support member 26 is an insulating substrate such as rigid ceramic, organic resin or other suitable materials, and the material forming the organic resin can be an epoxy resin material containing a high proportion of filler, such as epoxy molding compound (abbreviated as EMC); even more, the material forming the organic resin can be a high-strength plastic such as plastic steel. Furthermore, the preliminary process for manufacturing the second support member 26 can be the same as that of the first support member 22.

[0163] Or, such as Figure 2D-1As shown, the plurality of second conductive posts 25 and the second support member 26 can also be formed simultaneously by patterned electroplating on the circuit layer 241 exposed on the second surface 24b of the coreless layer circuit structure 24; wherein, the second conductive posts 25 are formed as single-layer columns, and the second support member 26 is formed as a single-layer plate body having a plurality of mesh openings (such as openings 260 and mesh holes 261). It should be understood that a plurality of the second conductive posts 25 are located in at least one of the mesh openings (such as the opening 260), and the second conductive posts 25 and the second support member 26 can be made of the same material, such as copper or copper alloy.

[0164] Furthermore, in this embodiment, when the second conductive posts 25 are used as the circuit board side S2 of the intermediate substrate 2 for bonding to the circuit board (as Figure 2F shown), then the first conductive posts 21 are used as the die placement side S1 of the intermediate substrate 2 for bonding to the chip (as Figure 2F shown), so the pitch t1 of each of the first conductive posts 21 is much smaller than the pitch t2 of each of the second conductive posts 25. It should be understood that the intermediate substrate 2 can first fabricate the die placement side and then fabricate the circuit board side; or, the intermediate substrate 2 can also first fabricate the circuit board side in the reverse order and then fabricate the die placement side.

[0165] As Figure 2E shown, a second insulating layer 27 is formed on the coreless layer circuit structure 24 to cover the plurality of second conductive posts 25 and the second support member 26, so that the plurality of second conductive posts 25 and the second support member 26 are buried in the second insulating layer 27, and a planarization process is performed on the second insulating layer 27 to expose the second end faces 25b of the plurality of second conductive posts 25 on the surface of the second insulating layer 27.

[0166] In this embodiment, the material for forming the second insulating layer 27 can be the same as that of the first insulating layer 23. It should be understood that the material of the second insulating layer 27 and the material of the dielectric layer 240 can also be the same or different. For example, the material of the second insulating layer 27 and the material of the dielectric layer 240 can be adjusted according to the CTE matching requirements to meet the low CTE requirements.

[0167] Furthermore, the planarization process includes removing a part of the material of the second conductive posts 25 and a part of the material of the second insulating layer 27 by grinding, chemical etching, laser ablation, sandblasting, plasma etching or other methods, so that the surface of the second insulating layer 27 is flush with the second end faces 25b of the second conductive posts 25, and the second side 26b of the second support member 26 is not exposed on the top surface of the second insulating layer 27; or, a part of the material of the second insulating layer 27 can also be removed by etching or laser ablation, so that the surface of the second insulating layer 27 is slightly lower than the second end faces 25b of the second conductive posts 25' (asFigure 2E-1 (as shown), etching process can also be performed on the second conductive post 25, so that the second end face 25b of the second conductive post 25” is slightly lower than the surface of the second insulating layer 27, as Figure 2E-2 (as shown), so that the second end faces 25b of the second conductive posts 25, 25’, 25” are exposed (flush, protruding, or recessed) on the top surface of the second insulating layer 27. Alternatively, the surface of the second side 26b of the second support member 26 can also be flush with the surface of the second insulating layer 27, so that the surface of the second side 26b of the second support member 26 is exposed on the surface of the second insulating layer 27 (as Figure 2E-3 (as shown).

[0168] In addition, the thickness d2 of the second support member 26 (the bonding layer 262 is extremely thin and can be ignored) can be designed according to requirements, preferably 0.05 mm to 1.5 mm.

[0169] As Figure 2F (as shown), the carrier 20 is removed, so that the second end faces 21b of the plurality of first conductive posts 21 are exposed on the surface of the first insulating layer 23, and finally a singulation process is performed along the cutting path L as Figure 2E (as shown) to obtain the interposer substrate 2.

[0170] In this embodiment, after removing the carrier 20, the bonding layer 222 on the first support member 22 can be further removed, so that the second side 22b of the first support member 22 is exposed on the first insulating layer 23, such as the interposer substrate 2a as Figure 2F-1 (as shown). For example, the bonding layer 222 can be removed by grinding, chemical etching, laser ablation, sandblasting, plasma etching or other methods.

[0171] Furthermore, following the process as Figure 2E-1 (as shown) to obtain the interposer substrate 2b as Figure 2F-2 (as shown), and after removing the carrier 20, a heat sink 28 can be attached on the die placement side S1, that is, the surface side where the first insulating layer 23 and the second side 22b of the first support member 22 are exposed, by an adhesive material 280 (such as the frame as Figure 2F-3 and Figure 2F-4 (as shown), which has a window 281 for exposing the plurality of first conductive posts 21) to improve heat dissipation.

[0172] Therefore, the manufacturing method of the present invention can easily fabricate fine pitch (such as 15 to 100 microns, far better than the 300 microns of the through-hole pitch of the existing core layer) of the interlayer conductive posts and fine line wiring by the coreless layer line structure 24 to meet the requirements of high I / O number and high wiring density of large-size packaging.

[0173] Furthermore, in the manufacturing method of the present invention, by arranging the rigid layers (such as the first support member 22 and the second support member 26) and the insulating layers (such as the first insulating layer 23 and the second insulating layer 27), the thickness and rigidity of the intermediate substrates 2, 2a, 2b, 2c are increased, thereby strengthening the coreless layer circuit structure 24, enabling the intermediate substrates 2, 2a, 2b, 2c to form a strong sandwich rigid structure and meeting the required rigidity, thus effectively resisting warping. Therefore, compared with the prior art, the intermediate substrates 2, 2a, 2b, 2c are applicable to the manufacturing process of large-size packaging products.

[0174] In addition, compared with the prior packaging substrates using the circuit layer as the external heat conduction path, in the present invention, by using the first support member 22 and the second support member 26 as the external heat conduction paths with a larger area, the heat dissipation performance can be improved, and when used for electrical connection, it can be connected to the ground to enhance the electrical characteristics.

[0175] In addition, as Figure 2G shown in the electronic package 9, taking the intermediate substrate 2a Figure 2F-1 shown as an example for the packaging operation, wherein, the coreless layer circuit structure 24 defines opposite first surface 24a and second surface 24b, such that the first surface 24a correspondingly bonds to the first insulating layer 23, and the second surface 24b correspondingly bonds to the second insulating layer 27, making the side of the first insulating layer 23 (i.e., the side of the second end faces 21b of the plurality of first conductive posts 21) the die placement side S1, and the side of the second insulating layer 27 (i.e., the side of the second end faces 25b of the plurality of second conductive posts 25) the circuit board bonding side S2. Therefore, the plurality of first conductive posts 21 on the die placement side S1 are bonded to at least one semiconductor chip 92 in a flip-chip packaging manner by a plurality of conductive bumps 93 containing solder material, and the plurality of second conductive posts 25 on the circuit board bonding side S2 are bonded to and electrically connected to a plurality of contacts 95 on a circuit board 9a by a plurality of solder balls 94.

[0176] In another embodiment of the electronic package 9' (as Figure 2G-1 shown), the die placement side S1 of the intermediate substrate 2a is bonded to a silicon interposer 91 configured with a semiconductor chip 92 in a flip-chip packaging manner by a plurality of conductive bumps 93 containing solder material, and the silicon interposer 91 has a redistribution layer 911 for flip-chip bonding the semiconductor chip 92, so as to form a large-size electronic package 9' in the form of CoWoS.

[0177] Furthermore, in another embodiment of the electronic package 9'' as Figure 2G-2 shown, by using the socket method, a Figure 2F-2The shown interposer substrate 2b has its multiple second conductive posts 25' protruding from the surface of the second insulating layer 27 directly and electrically docked onto multiple contacts 95 of the circuit board 9a. And the socket method belongs to a better solution because there is no impact from the reflow high-temperature process of the soldering method.

[0178] It should be noted that by interchanging the processing procedures and adjusting the gaps between the conductive posts, the side of the first insulating layer 23 can be used as the circuit board side, while the side of the second insulating layer 27 can be used as the chip placement side.

[0179] Therefore, since the coreless circuit structure 24 adopts coreless technology, ultra-fine circuits and high-density wiring can be made. Thus, the ultra-fine circuits and high-density wiring required for large-size packages can be easily arranged in the coreless circuit structure 24 to match the fine pitch and fine circuit specifications of the conductive bumps 93 of the semiconductor chip 92 or the silicon interposer 91. Therefore, the outermost circuit layer 241' of the coreless circuit structure 24 can use these first conductive posts 21 as external connection points, which can meet the requirements of tens of thousands of contacts (I / O) of the semiconductor chip 92. Moreover, the rigidity of the interposer substrates 2, 2a, 2b, 2c also meets the requirements, so it can effectively resist warping to avoid problems such as the cracking of the semiconductor chip 92 itself or the electrical failure of the semiconductor chip 92 due to the delamination between layers of the carrier board (such as the interposer substrates 2, 2a, 2b, 2c) during the reliability test.

[0180] In addition, since the coreless circuit structure 24 adopts coreless technology, ultra-fine circuits and high-density wiring can be easily made to arrange the high-density and fine-pitch wiring required for the large-size package corresponding to the circuit board 9a in the coreless circuit structure 24. Through proper design, the pitch t2 of the multiple second conductive posts 25 on the outermost circuit layer 241” of the coreless circuit structure 24 or on the circuit board side S2 is widened to match the pitch and line width of the multiple contacts 95 of the traditional circuit board 9a. Therefore, compared with the prior art that the assembly of large-size packages requires a fine-pitch, high-density, and high-layer configuration to be formed on the circuit board 9a to meet the requirements, the present invention can keep the circuit board 9a in a traditional design to greatly save costs and effectively improve the yield.

[0181] In addition, the good fine line and fine pitch wiring design capabilities of the coreless layer circuit structure 24 can easily and appropriately adjust (such as widen) the spacing t2 of each second conductive column 25 on the circuit board combining side S2 to match the optimal mass production spacing and line width of the multiple contacts 95 of the traditional circuit board 9a, so that the circuit board 9a does not need to be processed and manufactured with ultra-fine line specifications for local areas. Therefore, the production of the circuit board 9a can maintain the traditional structure and processing. Therefore, compared with the existing technology, the circuit board 9a does not need to match the large-size electronic package 9, 9', 9" type to perform fine line, fine pitch and increased stacking processing, thereby effectively simplifying the processing procedures and difficulty, and greatly reducing costs.

[0182] Figures 3A to 3E The cross-sectional view of the manufacturing method of the second embodiment of the interposer substrate 3 of the present invention is shown in FIG. The difference between this embodiment and the first embodiment lies in the manufacturing of the conductive pillars and the support members. The other manufacturing processes are substantially the same, so the same parts will not be described in detail below.

[0183] like Figure 3A As shown, a plurality of first columns 311 and at least one first plate 321 having a plurality of mesh openings are formed on a carrier 20, and a first insulating layer 331 is formed on the carrier 20 so that the first insulating layer 331 covers the plurality of first columns 311 and the first plate 321. Next, a flattening process is performed so that the first insulating layer 331 is flush with the plurality of first columns 311 and the first plate 321, so that the plurality of first columns 311 and the first plate 321 are exposed.

[0184] like Figure 3B As shown, a plurality of second columns 312 connected to the first columns 311 and at least one pair of second plates 322 connected to the first plate 321 and having a plurality of mesh openings are formed on the first insulating layer 331 in stages, and then a second insulating layer 332 is formed on the first insulating layer 331, so that the second insulating layer 332 covers the plurality of second columns 312 and the second plate 322, and the first and second insulating layers 331, 332 form a first insulating layer 33. Then, a flattening process is performed to make the second insulating layer 332 flush with the plurality of second columns 312, so that the plurality of second columns 312 are exposed, so that the first columns 311 and the second columns 312 are stacked to form the first conductive column 31, and the first plate 321 and the second plate 322 are stacked to form the first support member 32.

[0185] In this embodiment, the manufacturing method of the first column 311 and the second column 312 is the same as that of the first conductive column 21 in the first embodiment, and the manufacturing method of the first plate 321 and the second plate 322 is the same as that of the first support 22 in the first embodiment, while the manufacturing method of the first insulating layer 331 and the second insulating layer 332 is the same as that of the first insulating layer 23 in the first embodiment.

[0186] Furthermore, based on the definition of the first embodiment, the first conductive column 31 has opposite first end faces 31a and second end faces 31b, and the first support 32 has opposite first sides 32a and second sides 32b.

[0187] Or, please refer in detail Figure 3B-1 As shown, in another embodiment, the first column 311 and the first plate 321 can be formed synchronously by patterned electroplating, and the second column 312 and the second plate 322 can also be formed synchronously by patterned electroplating.

[0188] As Figure 3C As shown, a coreless layer circuit structure 24 is formed on the first insulating layer 33, so that one circuit layer 241' of the coreless layer circuit structure 24 is combined with the first conductive column 31 (wherein, one circuit layer 241' of the coreless layer circuit structure 24 can also be combined with the first support 32 simultaneously, as Figure 3C-1 shown). Then, a plurality of third columns 351 and a third plate 361 having a plurality of mesh openings are formed on the coreless layer circuit structure 24, and a third insulating layer 371 is formed on the coreless layer circuit structure 24 to cover the plurality of third columns 351 and the third plate 361. Then, a planarization process is performed to make the third insulating layer 371 flush with the plurality of third columns 351 and the third plate 361, so as to expose the plurality of third columns 351 and the third plate 361.

[0189] As Figure 3D As shown, a plurality of fourth columns 352 docking with the third columns 351 and a fourth plate 362 docking with the third plate 361 and having a plurality of mesh openings are formed on the third insulating layer 371 in multiple steps, and then a fourth insulating layer 372 is formed on the third insulating layer 371 to cover the plurality of fourth columns 352 and the fourth plate 362, and the third insulating layer 371 and the fourth insulating layer 372 form a second insulating layer 37. Then, a planarization process is performed to make the fourth insulating layer 372 flush with the plurality of fourth columns 352, so as to expose the plurality of fourth columns 352, stack the third columns 351 and the fourth columns 352 to form a second conductive column 35, and stack the third plate 361 and the fourth plate 362 to form a second support 36.

[0190] In this embodiment, the third column 351 and the fourth column 352 are fabricated in the same manner as the second conductive column 25 in the first embodiment, and the third plate 361 and the fourth plate 362 are fabricated in the same manner as the second support 26 in the first embodiment, while the third insulating layer 371 and the fourth insulating layer 372 are fabricated in the same manner as the second insulating layer 27 in the first embodiment.

[0191] Furthermore, the widths of the columns stacked and butt-jointed may be the same (such as the first column 311 and the second column 312) or different (such as the third column 351 and the fourth column 352). It should be understood that the width of the first column 311 may also be greater than or less than the width of the second column 312; alternatively, when the conductive column has three segments of columns, the width of the first column 311 may also be greater than, equal to, or less than the width of the second column 312.

[0192] Furthermore, based on the definition of the first embodiment, the second conductive column 35 has opposite first end face 35a and second end face 35b, and the second support 36 has opposite first side 36a and second side 36b.

[0193] Alternatively, part of the material of the second insulating layer 37 may also be removed by etching or laser ablation, so that the second end face 35b of the second conductive column 35' protrudes from the surface of the second insulating layer 37 (as Figure 3D-1 shown).

[0194] In addition, please refer in detail to Figure 3D-2 shown. In another embodiment, the third column 351 and the third plate 361 may be formed synchronously by patterned electroplating, and the fourth column 352 and the fourth plate 362 may be formed synchronously by patterned electroplating.

[0195] As Figure 3E shown, the carrier 20 is removed, and a singulation process is performed along the cutting path L as Figure 3D shown to obtain the intermediate substrate 3.

[0196] In this embodiment, after removing the carrier 20, the bonding layer 222 on the first plate 321 may be further removed, such as the intermediate substrate 3a as Figure 3E-1 shown.

[0197] Furthermore, as Figure 3E-2 shown in the intermediate substrate 3b, the second end face 35b of the second conductive column 35' may protrude from the surface of the second insulating layer 37, so that the second end face 35b of the second conductive column 35' is exposed on the surface of the second insulating layer 37. Or, as Figure 3E-3The shown interposer substrate 3c, after removing the carrier 20, can be provided with a heat sink 28 as shown on the surface of the first insulating layer 33. Figure 2F-4 as shown.

[0198] Figures 4A to 4D FIG. is a cross-sectional schematic view of the manufacturing method of the third embodiment of the interposer substrate 4 of the present invention. The difference between this embodiment and the first embodiment lies in the manufacturing of the second conductive posts 45 and the second support members 46. Since the other manufacturing processes are substantially the same, the same parts will not be described in detail below.

[0199] As Figure 4A shown, in the manufacturing process of the third embodiment, first provide a carrier 40, which is a single-layer metal plate (in another embodiment, it can be multiple-layer metal plates), such as a stainless steel plate, a high-rigidity alloy plate (such as an iron-nickel alloy plate, etc.), a thick copper plate or a copper alloy plate metal conductor, and then form the coreless layer circuit structure 24 on the carrier 40 by the same manufacturing method as described in the foregoing first embodiment. Among them, one circuit layer 241' of the coreless layer circuit structure 24 is directly combined with the carrier 40.

[0200] As Figure 4B shown, form a plurality of first conductive posts 21, a first support member 22 having a plurality of mesh openings, and a first insulating layer 23, etc. on the coreless layer circuit structure 24.

[0201] In this embodiment, the plurality of first conductive posts 21 are formed on one circuit layer 241' of the coreless layer circuit structure 24 by patterned electroplating, and the first support member 22 is combined with the coreless layer circuit structure 24 by a bonding method; alternatively, the plurality of first conductive posts 21 and the first support member 22 can also be formed synchronously by patterned electroplating and are both directly combined with one circuit layer 241' of the coreless layer circuit structure 24 (as Figure 4B-1 shown).

[0202] Based on the definition of the first embodiment, the first conductive post 21 has opposite first end face 21a and second end face 21b, and the first support member 22 has opposite first side 22a and second side 22b.

[0203] As Figure 4C shown, etch the carrier 40 by a patterned etching process to form a plurality of second conductive posts 45 and a second support member 46 having a plurality of mesh openings; then, form a second insulating layer 47 on the coreless layer circuit structure 24 to cover the plurality of second conductive posts 45 and the second support member 46; finally, perform a planarization process to make the second insulating layer 47 flush with the plurality of second conductive posts 45 and the second support member 46, so as to expose one end face of the plurality of second conductive posts 45 and one side of the second support member 46.

[0204] In this embodiment, based on the definition of the first embodiment, the second conductive post 45 has opposite first and second end faces 45a and 45b, and the second support member 46 has opposite first and second sides 46a and 46b.

[0205] As Figure 4D shown, a dicing process is performed along the dicing path L as Figure 4C shown to obtain the intermediate substrate 4; wherein, the side of the first conductive post 21 (i.e., the side of the first insulating layer 23) serves as the crystal placement side S1 for bonding a chip or a silicon intermediate substrate in a flip-chip manner, and the side of the second conductive post 45 formed by etching (i.e., the side of the second insulating layer 47) serves as the circuit board bonding side S2 for bonding a circuit board.

[0206] Furthermore, taking the process of the first embodiment as an example, as Figure 4D-1 shown, on the surface (crystal placement side S1) of the first insulating layer 23 of the intermediate substrate 4a as Figure 2F-4 shown, a heat sink 28 as

[0207] Figures 5A to 5D shown is disposed to improve heat dissipation.

[0208] As Figure 5A shown, taking the first embodiment as an example, a plurality of first conductive posts 21 are formed by patterned electroplating on a carrier 20, and a first support member 52 having a plurality of mesh openings (defining openings 520 with larger sizes and mesh holes 221 with smaller sizes) as Figure 5A-1 shown is bonded to the carrier 20 in a fitting manner, and then a first insulating layer 23 is formed to cover the first conductive posts 21 and the first support member 52. Among them, the openings 520 of the first support member 52 can be formed into regular or irregular hole shapes or opening shapes of different sizes according to requirements; furthermore, the first conductive posts 21 and the first support member 52 can also be formed synchronously by patterned electroplating.

[0209] In this embodiment, the first support member 52 is a mesh plate, which has a contact area C provided with the openings 520, and the openings 520 correspond to the first conductive posts 21, so that each of the first conductive posts 21 is respectively located in each of the openings 520 and protrudes from each of the openings 520.

[0210] Furthermore, based on the definition of the first embodiment, the first support member 52 has opposite first and second sides 52a and 52b.

[0211] As Figure 5BAs shown, a coreless layer circuit structure 24 is formed on the first conductive pillar 21 and the first insulating layer 53.

[0212] As Figure 5C shown, a plurality of second conductive pillars 25 are formed on the coreless layer circuit structure 24 by patterned electroplating, and a second support member 56 having a plurality of mesh openings (defining larger openings 560 and smaller mesh holes 261) is bonded to the coreless layer circuit structure 24 in a bonding manner (as Figure 5A-1 shown), and then a second insulating layer 27 is formed to cover the second conductive pillars 25 and the second support member 56. Among them, the openings 560 of the second support member 56 can be formed into regular or irregular hole shapes or opening shapes of different sizes according to requirements; furthermore, the second conductive pillars 25 and the second support member 56 can also be formed synchronously by patterned electroplating.

[0213] In this embodiment, the second support member 56 is a mesh plate, which has a contact area C provided with the openings 560, and the openings 560 correspond to the second conductive pillars 25, so that each of the second conductive pillars 25 is respectively located in each of the openings 560 and protrudes from each of the openings 560.

[0214] Furthermore, based on the definition of the first embodiment, the second support member 56 has opposite first side 56a and second side 56b.

[0215] As Figure 5D shown, the carrier 20 and the bonding layer 222 are removed, and a singulation process is performed along the cutting path L as Figure 5C shown to obtain the interposer substrate 5.

[0216] Furthermore, as Figure 5D-1 shown, the embodiment of the heat sink 28 as Figure 2F-3 , 2F-4 shown can also be applied to this embodiment to obtain the interposer substrate 5a.

[0217] It should be understood that the feature that the first support member 52 / the second support member 56 in this embodiment has openings 520 / 560 that can respectively accommodate the first conductive pillar 21 / second conductive pillar 25 is also applicable to the second embodiment (such as the interposer substrate 5b shown in Figure 5D-2 , in which the first support member 52' and the second support member 56' are a plurality of laminate bodies having a plurality of openings 520', 560') and the third embodiment (such as the interposer substrate 5c shown in Figure 5D-3 , in which the first support member 52'' and the second support member 56'' are a mesh plate body having a plurality of openings 520'', 560'', and the second conductive pillar 45 and the second support member 56'' are formed by etching the carrier plate 20 by a patterned etching process).

[0218] Figure 6 A cross-sectional schematic view of the fifth embodiment of the interposer substrate 6 of the present invention. The difference between this embodiment and the above-mentioned embodiments lies in the fabrication of the conductive posts, and the other processes are substantially the same, so the same parts will not be described in detail below.

[0219] As Figure 6 shown, the first conductive post 61 is in the form of multiple layer cylinders, and a pad (Land) 610 is included between the layers, while the second conductive post 65 is in the form of multiple layer cylinders, and a pad 650 is included between the layers.

[0220] In this embodiment, taking the second embodiment as an example, on the carrier 20, the first cylinder 611, the pad portion 610, and the second cylinder 612 are sequentially formed by patterned electroplating in a stacked manner, and are combined to form the first conductive post 61. Its function is to serve as the die side for flip-chip bonding of the chip or the interposer. Therefore, a finer conductive post pitch is required. Therefore, the multi-segment post embodiment of the first conductive post 61 is beneficial to meet the fabrication requirements of the fine pitch.

[0221] It should be understood that the second conductive post 65 can also adopt a multi-segment post with a pad 650. It is sequentially formed by patterned electroplating on a circuit layer of the coreless layer circuit structure 24 in a stacked manner to form the third cylinder 651, the pad portion 650, and the fourth cylinder 652, and is combined to form the second conductive post 65.

[0222] Based on the definition of the first embodiment, the first conductive post 61 has opposite first end face 61a and second end face 61b, and the second conductive post 65 has opposite first end face 65a and second end face 65b.

[0223] Furthermore, it should be understood that before the singulation operation in the above-mentioned embodiments, the exposed parts of the conductive posts and the support members can be surface-treated first, and the material for forming the surface treatment layer is one of the group consisting of nickel, palladium, gold, tin, silver, copper alloys, multi-layer metals, or organic solderability preservatives (Organic Solderability Preservative, abbreviated as OSP), for example, electroplated nickel / gold, electroless nickel / gold, electroless nickel immersion gold (ENIG), electroless nickel palladium immersion gold (ENEPIG), immersion tin, or pre-solder, etc., but not limited to the above.

[0224] It should be understood that the second support member (or the first support member) in the above-mentioned embodiments can be designed with a thick metal layer to improve the rigidity and heat dissipation of the interposer substrate.

[0225] In summary, for the interposer substrate and its manufacturing method of the present invention, by adopting the coreless technology in the coreless layer circuit structure, it is easy to fabricate wirings with fine pitch, high density, and fine lines, thus meeting the requirements of high I / O count and high wiring density for large-size packaging.

[0226] Furthermore, through the configuration of the first support member and the second support member with the first insulating layer and the second insulating layer, and by utilizing the characteristics of the support members having good rigidity and appropriate thickening, the rigidity of the interposer substrate meets the requirements, thus effectively resisting warping. Therefore, when the interposer substrate is used for the packaging operation of chip components, the quality, reliability, and yield can be improved.

[0227] In addition, by using the coreless layer circuit structure, there is no need to perform the conductive via process, so the present invention does not have the deficiencies described in the prior art.

[0228] Moreover, with the coreless layer circuit structure, the area where the circuit board requires fine line wiring design is designed in the coreless layer circuit structure, and the spacing between the second conductive pillars is widened, so the present invention can solve the problems of the existing circuit board.

[0229] The above embodiments are only used to illustrate the principles and effects of the present invention by way of example, rather than to limit the present invention. Any person skilled in the art can modify the above embodiments without departing from the spirit and scope of the present invention. Therefore, the scope of the patent protection of the present invention shall be as listed in the claims.

Claims

1. An interposer substrate, characterized in that, Comprising: A coreless layer circuit structure having opposite first and second surfaces, and both the first surface and the second surface include exposed circuit layers; A plurality of first conductive posts having opposite first and second end faces, and the first end face is bonded and electrically connected to the circuit layer exposed on the first surface of the coreless layer circuit structure; A first support member which is a plate body provided with a plurality of mesh openings, having opposite first and second sides, and its first side is disposed on the first surface of the coreless layer circuit structure, and the plurality of first conductive posts are located in at least one mesh opening of the first support member; A first insulating layer is disposed on the first surface of the coreless layer circuit structure to cover the plurality of first conductive posts and the first support member, and the second end faces of the plurality of first conductive posts are exposed outside the first insulating layer; A plurality of second conductive posts having opposite first and second end faces, and the first end face is bonded and electrically connected to the circuit layer exposed on the second surface of the coreless layer circuit structure; A second support member which is a plate body provided with a plurality of mesh openings, having opposite first and second sides, and its first side is disposed on the second surface of the coreless layer circuit structure, and the plurality of second conductive posts are located in at least one mesh opening of the second support member; And A second insulating layer is disposed on the second surface of the coreless layer circuit structure to cover the plurality of second conductive posts and the second support member, and the second end faces of the plurality of second conductive posts are exposed outside the second insulating layer.

2. The intermediate substrate according to claim 1, characterized in that, The second side of the first support member is exposed outside the first insulating layer, and / or the second side of the second support member is exposed outside the second insulating layer.

3. The interposer substrate according to claim 1, wherein The first conductive post and / or the second conductive post includes a plurality of stacked columnar bodies.

4. The intermediate substrate according to claim 1, wherein, The first side of the first support member is bonded to the circuit layer exposed on the first surface of the coreless layer circuit structure, and / or the first side of the second support member is bonded to the circuit layer exposed on the second surface of the coreless layer circuit structure.

5. The interposer substrate according to claim 1, wherein The first support member and / or the second support member includes a plurality of stacked plate bodies each provided with a plurality of mesh openings.

6. The intermediate substrate according to claim 1, wherein The plurality of first conductive posts are respectively located in each of the mesh openings of the first support member, and / or the plurality of second conductive posts are respectively located in each of the mesh openings of the second support member.

7. The interposer substrate according to claim 1, wherein The plurality of first conductive posts and the first support member are made of copper or copper alloy, and the plurality of second conductive posts and the second support member are made of copper, copper alloy, stainless steel or iron-nickel alloy.

8. The interposer substrate according to claim 1, wherein The first support member and / or the second support member is made of metal material, organic resin material, plastic steel material or ceramic insulating material.

9. The interposer substrate according to claim 1, wherein The side of the second end face of the plurality of first conductive posts serves as a crystal placement side for flip-chip bonding with a chip or an interposer, and the side of the second end face of the plurality of second conductive posts serves as a circuit board bonding side for bonding with a circuit board.

10. A method for manufacturing an intermediate substrate, characterized in that, Comprising: Providing a carrier; Forming a plurality of first conductive posts and forming a plate-shaped first support member including a plurality of mesh openings on the carrier by patterned electroplating, so that the plurality of first conductive posts are located in at least one of the mesh openings of the first support member; Form a first insulating layer on the carrier such that the first insulating layer covers the plurality of first conductive posts and the first support member, and perform a planarization process on the first insulating layer such that one end surface of the plurality of first conductive posts exposes the surface of the first insulating layer; Form a coreless layer circuit structure having at least one circuit layer on the first insulating layer, the plurality of first conductive posts, and the first support member by a build-up method such that at least one of the circuit layers of the coreless layer circuit structure is bonded to one end surface of the plurality of first conductive posts; Form a plurality of second conductive posts by patterned electroplating on the coreless layer circuit structure and form a plate-shaped second support member having a plurality of mesh-shaped openings such that the plurality of second conductive posts are located in at least one of the mesh-shaped openings of the second support member, and one end surface of the plurality of second conductive posts is bonded to at least one of the circuit layers of the coreless layer circuit structure; Form a second insulating layer on the coreless layer circuit structure such that the second insulating layer covers the plurality of second conductive posts and the second support member, and perform a planarization process on the second insulating layer such that the other end surface of the plurality of second conductive posts is exposed on the surface of the second insulating layer; And Remove the carrier such that the other end surface of the plurality of first conductive posts is exposed on the first insulating layer.

11. The manufacturing method of the intermediate substrate according to claim 10, characterized in that, The first support member and the plurality of first conductive posts are simultaneously formed on the carrier by patterned electroplating, and the first conductive posts are formed as single-layer columns or multiple stacked layer columns, and / or the first support member is formed as a single-layer plate having a plurality of mesh-shaped openings or multiple stacked layer plates.

12. The method for manufacturing an interposer substrate according to claim 10, wherein, First, form the plurality of first conductive posts on the carrier by patterned electroplating, and then bond the first support member having the plurality of mesh-shaped openings to the carrier by an adhesive bonding method, wherein the first conductive posts are formed as single-layer columns or multiple stacked layer columns, and / or the first support member is formed as a single-layer plate having a plurality of mesh-shaped openings or multiple stacked layer plates; or first, bond the first support member having the plurality of mesh-shaped openings to the carrier by an adhesive bonding method, and then form the plurality of first conductive posts on the carrier by patterned electroplating, wherein the first conductive posts are formed as single-layer columns or multiple stacked layer columns, and / or the first support member is formed as a single-layer plate having a plurality of mesh-shaped openings or multiple stacked layer plates.

13. The method for manufacturing an interposer substrate according to claim 10, wherein, The second support member and the plurality of second conductive posts are simultaneously formed on a circuit layer on one surface of the coreless layer circuit structure by patterned electroplating, and the second conductive posts are formed as single-layer columns or multiple stacked layer columns, and / or the second support member is formed as a single-layer plate having a plurality of mesh-shaped openings or multiple stacked layer plates.

14. The method for manufacturing an interposer substrate according to claim 10, wherein First, form the plurality of second conductive pillars on a circuit layer on one surface of the coreless layer circuit structure by patterned electroplating, and then bond the second support member having the plurality of mesh openings to the circuit layer on one surface of the coreless layer circuit structure by an adhesive bonding method. Wherein, the second conductive pillar is formed as a single-layer pillar or a plurality of stacked layer pillars, and / or the second support member is formed as a single-layer plate body or a plurality of stacked layer plate bodies having the plurality of mesh openings; alternatively, first bond the second support member having the plurality of mesh openings to the circuit layer on one surface of the coreless layer circuit structure by an adhesive bonding method, and then form the plurality of second conductive pillars on the circuit layer on one surface of the coreless layer circuit structure by patterned electroplating. Wherein, the second conductive pillar is formed as a single-layer pillar or a plurality of stacked layer pillars, and / or the second support member is formed as a single-layer plate body or a plurality of stacked layer plate bodies having the plurality of mesh openings.

15. The manufacturing method of the intermediate substrate according to claim 10, characterized in that, The plurality of first conductive pillars are respectively located in the respective mesh openings of the first support member, and / or the plurality of second conductive pillars are respectively located in the respective mesh openings of the second support member.

16. The manufacturing method of the intermediate substrate according to claim 10, characterized in that, One side of the first support member is exposed outside the first insulating layer, and / or one side of the second support member is exposed outside the second insulating layer.

17. A manufacturing method of an intermediate substrate, characterized in that, Comprising: Provide a carrier, and the carrier is a plate body made of copper, copper alloy, stainless steel or iron-nickel alloy; Form a coreless layer circuit structure having a plurality of circuit layers on the carrier by an additive method, and bond at least one of the circuit layers of the coreless layer circuit structure to the carrier; On one circuit layer of the coreless layer circuit structure, form a plurality of first conductive pillars by patterned electroplating and form a plate-shaped first support member including a plurality of mesh openings, so that the plurality of first conductive pillars are located in at least one of the mesh openings of the first support member; Form a first insulating layer on the coreless layer circuit structure to cover the plurality of first conductive pillars and the first support member, and perform a planarization process on the first insulating layer so that one end surface of the plurality of first conductive pillars is exposed on the surface of the first insulating layer; Pattern-etch the carrier to form a plurality of second conductive pillars and a second support member. Wherein, the second support member is formed as a plate body including a plurality of mesh openings, and the plurality of second conductive pillars are located in at least one of the mesh openings of the second support member; And Form a second insulating layer on the coreless layer circuit structure to cover the plurality of second conductive pillars and the second support member, and perform a planarization process on the second insulating layer so that one end surface of the plurality of second conductive pillars is exposed on the surface of the second insulating layer.

18. The method for manufacturing an interposer substrate according to claim 17, wherein One side of the first support member is exposed outside the first insulating layer, and / or one side of the second support member is exposed outside the second insulating layer.

19. The manufacturing method of the intermediate substrate according to claim 17, characterized in that, The first support member and the plurality of first conductive pillars are simultaneously formed on the circuit layer of the coreless layer circuit structure by patterned electroplating, and the first conductive pillar is formed as a single-layer pillar or a plurality of stacked layer pillars, and / or the second support member is formed as a single-layer plate body or a plurality of stacked layer plate bodies.

20. The method for manufacturing an interposer substrate according to claim 17, wherein, First, form the plurality of first conductive pillars on one of the circuit layers of the coreless layer circuit structure by patterned electroplating, and then bond the first support member to one of the circuit layers of the coreless layer circuit structure by an adhesive bonding method. Among them, the first conductive pillars are formed as single-layer pillars or a plurality of stacked layer pillars, and the first support member is formed as a single-layer plate or a plurality of stacked layer plates; alternatively, first bond the first support member to one of the circuit layers of the coreless layer circuit structure by an adhesive bonding method, and then form the plurality of first conductive pillars on one of the circuit layers of the coreless layer circuit structure by patterned electroplating. Among them, the first conductive pillars are formed as single-layer pillars or a plurality of stacked layer pillars, and the first support member is formed as a single-layer plate or a plurality of stacked layer plates.

21. The manufacturing method of the intermediate substrate according to claim 17, characterized in that, The plurality of first conductive pillars are respectively located in the respective mesh openings of the first support member, and / or the plurality of second conductive pillars are respectively located in the respective mesh openings of the second support member.

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