HKMG parasitic capacitance test structure layout

Abstract

The present invention provides a layout of a HKMG parasitic capacitance test structure, including a dummy gate pattern; a plurality of contact hole patterns arranged between and on the dummy gate patterns; a dummy gate active region pattern arranged on the dummy gate pattern and having a length less than the dummy gate pattern, wherein the dummy gate active region pattern and the contact hole pattern do not overlap. The capacitor structure designed in the layout of the present invention does not increase any process cost, and effectively reduces process defects caused by the metal gate recess effect, is convenient for actual production application, is suitable for extracting the parasitic capacitance value of the back-end metal connection, and effectively calculates the electrical thickness of the oxide layer.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a layout of a HKMG parasitic capacitance test structure. Background Art

[0002] The design of electrical thickness capacitor structure extracted from the actual HKMG (high-k metal gate) platform is as follows Figure 1 As shown, a structure with a longer gate length is usually selected for testing, such as Figure 1 As shown in the dashed box, in order to calculate the parasitic capacitance between the metal gate and the back-end metal connection, the traditional structural design is as follows Figure 2 As shown in the dashed box, the active area (AA, such as Figure 2 The shaded part in the middle is removed, and the capacitance value tested is the capacitance of the back-end connection. However, in the actual production process, this design method will lead to a low local density of the device AA, and the subsequent CMP (chemical mechanical planarization) polishing process will cause the shallow trench isolation (STI) oxide surface depression and metal gate surface depression, resulting in abnormal metal gate formation of the device and abnormal metal gate filling, which is mainly manifested as incomplete metal filling, resulting in a small test capacitance value between the metal connection and the metal gate.

[0003] Therefore, a new parasitic capacitance structure compatible with the existing CMOS (complementary metal oxide semiconductor) process is needed. Summary of the invention

[0004] In view of the shortcomings of the prior art described above, the purpose of the present invention is to provide a layout of a HKMG parasitic capacitance test structure, which is used to solve the problem in the prior art that the local density of the active area of ​​the device is low, the subsequent CMP polishing process causes the shallow trench isolation oxide surface depression and the metal gate surface depression, resulting in abnormal metal gate formation of the device, abnormal metal gate filling, and small test capacitance value between the metal connection and the metal gate.

[0005] To achieve the above objectives and other related objectives, the present invention provides a layout of a HKMG parasitic capacitance test structure, including:

[0006] Pseudo-grid graphics;

[0007] A plurality of contact hole patterns are provided between the dummy gate patterns and on the dummy gate patterns;

[0008] A dummy gate active area pattern is disposed on the dummy gate pattern and is shorter than the dummy gate pattern in length, wherein the dummy gate active area pattern does not overlap with the contact hole pattern.

[0009] Preferably, the dummy gate pattern includes a first dummy gate pattern, and second, third, fourth dummy gate patterns and fifth, sixth, seventh dummy gate patterns located on both sides of the first dummy gate pattern and symmetrically distributed.

[0010] Preferably, at least one contact hole pattern is disposed between the second, third, fourth dummy gate patterns and the fifth, sixth, seventh dummy gate patterns.

[0011] Preferably, the number of the contact hole patterns is three and they are equidistantly distributed in the same column.

[0012] Preferably, at least one contact hole pattern is disposed at one end of each of the third and sixth dummy gate patterns.

[0013] Preferably, there are four contact hole patterns, which are equidistantly distributed in the same row.

[0014] Preferably, the second, fourth, fifth and seventh dummy gate patterns have the same shapes.

[0015] Preferably, the widths of the third and sixth dummy gate patterns are greater than the widths of the second, fourth, fifth and seventh dummy gate patterns, and the widths of the second, fourth, fifth and seventh dummy gate patterns are greater than the width of the first dummy gate pattern.

[0016] Preferably, each of the dummy gate patterns has a consistent height.

[0017] Preferably, the dummy gate active area patterns on the second and seventh dummy gate patterns share the same boundary therewith respectively.

[0018] Preferably, the widths of the dummy gate active area patterns on the third and sixth dummy gate patterns are both smaller than the widths of the third and sixth dummy gate patterns.

[0019] Preferably, the dummy gate active area pattern located on the first, fourth and fifth dummy gate patterns share the same border with the fourth and fifth dummy gate patterns respectively.

[0020] Preferably, the layout is used for CMOS technology.

[0021] As described above, the layout of the HKMG parasitic capacitance test structure of the present invention has the following beneficial effects:

[0022] The capacitor structure designed in the layout of the present invention does not increase any process cost, and effectively reduces the process defects caused by the metal gate recess effect, is convenient for actual production application, is suitable for extracting the parasitic capacitance value of the back-end metal connection, and effectively calculates the electrical thickness of the oxide layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 Shown is a schematic diagram of a layout of a capacitor structure in the prior art;

[0024] Figure 2 Shown is a schematic diagram of the prior art back-end connection capacitance test;

[0025] Figure 3 Shown is a schematic layout diagram of the parasitic capacitance test structure of the present invention. DETAILED DESCRIPTION

[0026] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0027] See also Figure 3 The present invention provides a layout of a HKMG parasitic capacitance test structure, comprising:

[0028] The dummy gate pattern is used to define the position where the dummy gate is formed. In the manufacture of semiconductor devices, after the dummy gate is formed, the dummy gate is removed to form a filling groove, and then a metal gate is deposited in the filling groove;

[0029] In an optional embodiment, the dummy gate pattern includes a first dummy gate pattern 11, and second, third, fourth dummy gate patterns (12, 13, 14) and fifth, sixth, seventh dummy gate patterns (15, 16, 17) located on both sides of the first dummy gate pattern 11 and symmetrically distributed.

[0030] In an optional implementation, the second, fourth, fifth and seventh dummy gate patterns (12, 14, 15, 17) have the same shape, that is, in the layout design, the design standards of the second, fourth, fifth and seventh dummy gate patterns (12, 14, 15, 17) are the same.

[0031] In an optional embodiment, the widths of the third and sixth dummy gate patterns (13, 16) are greater than the widths of the second, fourth, fifth, and seventh dummy gate patterns (12, 14, 15, 17), and the widths of the second, fourth, fifth, and seventh dummy gate patterns (12, 14, 15, 17) are greater than the width of the first dummy gate pattern 11.

[0032] In an optional implementation, each dummy gate pattern has a consistent height.

[0033] A plurality of contact hole patterns 18 disposed between and on the dummy gate patterns;

[0034] In an optional embodiment, at least one contact hole pattern 18 is disposed between the second, third, fourth dummy gate patterns (12, 13, 14) and the fifth, sixth, seventh dummy gate patterns (15, 16, 17).

[0035] In an optional embodiment, the number of contact hole patterns 18 between the second, third and fourth dummy gate patterns (12, 13, 14) and the fifth, sixth and seventh dummy gate patterns (15, 16, 17) are three respectively and are equidistantly distributed in the same column.

[0036] In an optional implementation, at least one contact hole pattern 18 is disposed at one end of each of the third and sixth dummy gate patterns (13, 16).

[0037] In an optional implementation, the number of contact hole patterns 18 at one end of the third and sixth dummy gate patterns (13, 16) are four respectively and are equidistantly distributed in the same row.

[0038] A dummy gate active area pattern 19 is provided on the dummy gate pattern and is shorter than the dummy gate pattern. The dummy gate active area pattern 19 does not overlap with the contact hole pattern 18. In the prior art, the active area (AA) in the original device is removed, and the capacitance value tested is the back-end connection capacitance. However, in the actual production process, this design method will result in a low local density of the device AA, and the subsequent CMP (chemical mechanical planarization) grinding process will result in shallow trench isolation (STI) oxide surface depression and metal gate surface depression, resulting in abnormal metal gate formation of the device. By adding a dummy gate active area pattern 19 (dummy AA) to the dummy gate pattern, the active area density is effectively increased. The semiconductor device manufactured by the layout in the subsequent process reduces the STI and metal gate depression phenomenon, and the capacitance value tested does not add any capacitance.

[0039] In an optional implementation manner, the dummy gate active area patterns 19 on the second and seventh dummy gate patterns (12, 17) share the same boundary with them respectively.

[0040] In an optional implementation, the width of the dummy gate active area pattern 19 on the third and sixth dummy gate patterns (13, 16) is smaller than the width of the third and sixth dummy gate patterns (13, 16).

[0041] In an optional implementation, the dummy gate active area pattern 19 located on the first, fourth and fifth dummy gate patterns (11, 14, 15) share the same border with the fourth and fifth dummy gate patterns (14, 15), respectively.

[0042] In an optional implementation, the layout is used in a CMOS process and is suitable for extracting parasitic capacitance values ​​of back-end metal connections and effectively calculating electrical thickness of an oxide layer.

[0043] It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner. Therefore, the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0044] In summary, the capacitor structure designed in the layout of the present invention does not increase any process cost, and effectively reduces the process defects caused by the metal gate recess effect, is convenient for actual production application, is suitable for extracting the parasitic capacitance value of the back-end metal connection, and effectively calculates the electrical thickness of the oxide layer. Therefore, the present invention effectively overcomes the various shortcomings of the prior art and has a high industrial utilization value.

[0045] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A layout of a HKMG parasitic capacitance test structure, characterized in that: include: The dummy gate pattern is used to define the position where the dummy gate is formed. In the manufacture of semiconductor devices, after the dummy gate is formed, the dummy gate is removed to form a filling groove, and then a metal gate is deposited in the filling groove; A plurality of contact hole patterns are provided between the dummy gate patterns and on the dummy gate patterns; a dummy gate active area pattern disposed on the dummy gate pattern and having a length shorter than that of the dummy gate pattern, wherein the dummy gate active area pattern does not overlap with the contact hole pattern; The dummy gate pattern includes a first dummy gate pattern, and second, third, fourth dummy gate patterns and fifth, sixth, and seventh dummy gate patterns located on both sides of the first dummy gate pattern and symmetrically distributed; At least one contact hole pattern is provided between the second, third and fourth dummy gate patterns; At least one contact hole pattern is provided between the fifth, sixth and seventh dummy gate patterns; At least one contact hole pattern is provided at one end of the third and sixth dummy gate patterns; The widths of the third and sixth dummy gate patterns are greater than the widths of the second, fourth, fifth and seventh dummy gate patterns, and the widths of the second, fourth, fifth and seventh dummy gate patterns are greater than the width of the first dummy gate pattern; The dummy gate active area patterns on the second and seventh dummy gate patterns share the same boundary with them respectively; The widths of the dummy gate active area patterns on the third and sixth dummy gate patterns are smaller than the widths of the third and sixth dummy gate patterns; The dummy gate active area patterns located on the first, fourth and fifth dummy gate patterns share the same border with the fourth and fifth dummy gate patterns respectively; In the manufacture of semiconductor devices, the active area of ​​the semiconductor device is removed, and the pseudo gate active area pattern is manufactured to increase the active area density, forming a metal gate and a back-end metal connection to obtain the parasitic capacitance between the two. Due to the increase in the active area density, the STI and the metal gate depression phenomenon are reduced.

2. The layout of the HKMG parasitic capacitance test structure according to claim 1, characterized in that: The number of the contact hole patterns is three and they are equidistantly distributed in the same column.

3. The layout of the HKMG parasitic capacitance test structure according to claim 1, characterized in that: The number of the contact hole patterns is four and they are distributed in the same row in sequence and at equal intervals.

4. The layout of the HKMG parasitic capacitance test structure according to claim 1, characterized in that: The second, fourth, fifth and seventh dummy gate patterns have the same shapes.

5. The layout of the HKMG parasitic capacitance test structure according to claim 1, characterized in that: The height of each of the dummy gate patterns is consistent.

6. The layout of the HKMG parasitic capacitance test structure according to claim 1, characterized in that: The layout is used for CMOS technology.

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