Silicon rectifier device for low-power circuits

Abstract

A silicon rectifier device for a low-power circuit, comprising a P substrate, an N well and a P well. On the surface of the N well, an N+ region one and a P+ region one connected to the anode of the device are arranged from outside to inside and separated by a shallow trench isolation region one. On the surface of the P well, a P+ region two and an N+ region two connected to the cathode of the device are arranged from outside to inside and separated by a shallow trench isolation region two. An N+ region three is also arranged on the surface of the N well and the surface of the P well. The N+ region three is separated from the P+ region one by a shallow trench isolation region three. The gate is used to connect the N+ region three and the N+ region two, thereby forming a MOS structure with the N+ region three as the drain and the N+ region two as the source; wherein the gate is connected to the cathode of the device. In the N well, an N shallow well is arranged below the P+ region one. In the P well, a P shallow well is arranged below the gate. The trigger voltage and the holding voltage of the device of the present invention are adjustable, can be flexibly used in a low-power circuit, and can avoid the occurrence of latch-up effect.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor devices, and particularly relates to a silicon rectifier device for low-power circuits. Background Art

[0002] Electrostatic and electrostatic protection are common phenomena in nature. With the continuous reduction of the semiconductor manufacturing process size and the continuous expansion of the integrated circuit scale, the damage of chips caused by static electricity during production, transportation, and use is becoming more and more serious. Therefore, it is of great significance to study electrostatic discharge (ESD) protection. Among the commonly used ESD protection devices, the SCR (Silicon Controlled Rectifier) has good characteristics in terms of ESD protection effect and parasitic influence on the circuit. Although the traditional SCR naturally has advantages such as high discharge efficiency, strong anti-electric overstress ability, low static leakage, and small parasitic capacitance, its trigger voltage is also very high, which is a problem that the traditional SCR must solve.

[0003] At the same time, in order to be applied in low-power circuits, the ESD device needs to work normally in low-power circuits and avoid the latch-up effect of the circuit. However, the trigger voltage and holding voltage of the traditional MLSCR (Modified Lateral Silicon Controlled Rectifier) are relatively high.

[0004] Therefore, exploring an ESD protection device with a low trigger voltage, low on-resistance, and high robustness is of great significance for the full-chip ESD protection scheme under sub-micron feature sizes. Summary of the Invention

[0005] In order to overcome the above-mentioned disadvantages of the prior art, the purpose of the present invention is to provide a silicon rectifier device for low-power circuits, which has a lower trigger voltage and holding voltage, so as to solve the problem that the device cannot work in low-power circuits due to high holding voltage, high trigger voltage, etc.

[0006] In order to achieve the above purpose, the technical solution adopted by the present invention is:

[0007] A silicon rectifier device for a low-power circuit includes a P substrate, an N well and a P well located on the P substrate. On the surface of the N well, an N+ region one and a P+ region one connected to the anode of the device are arranged from outside to inside and separated by a shallow trench isolation region one. On the surface of the P well, a P+ region two and an N+ region two connected to the cathode of the device are arranged from outside to inside and separated by a shallow trench isolation region two. An N+ region three is also arranged on the surface of the N well and the surface of the P well. The N+ region three is separated from the P+ region one by a shallow trench isolation region three. The gate is used to connect the N+ region three and the N+ region two, thereby forming a MOS structure with the N+ region three as the drain and the N+ region two as the source; wherein the gate is connected to the cathode of the device.

[0008] Optionally, the N well and the P+ region one form a reverse-biased PN junction.

[0009] Optionally, in the N well, an N shallow well is arranged below the P+ region one, and the concentration of the N shallow well is less than that of the N well, so as to form a PNP transistor with the P+ region one as the emitter, the N shallow well as the base, and the P well as the collector.

[0010] Optionally, in the P well, a P shallow well is arranged below the gate, and the concentration of the P shallow well is less than that of the P well, so as to form an NPN transistor with the N well as the collector, the P shallow well as the base, and the N+ region three and the N+ region two as the emitters.

[0011] Optionally, the concentration of the N shallow well is 1 / 10 of the concentration of the N well, and the concentration of the P shallow well is 1 / 10 of the concentration of the P well.

[0012] Optionally, the N shallow well connects at least the shallow trench isolation region one and the shallow trench isolation region three, and the P shallow well connects at least the N+ region three and the N+ region two.

[0013] Optionally, the current conduction path of the silicon rectifier device is P+ region two → N shallow well → N well → P well → P shallow well → N+ region three, and the current is mainly distributed in the N shallow well and P shallow well regions; after the diode is turned on, the current density distribution appears between the N well and the P well. At this time, the parasitic transistors PNP and NPN are turned on, but positive feedback has not been formed; after the current increases, the current gain of the parasitic NPN transistor increases with the increase of the current. When the product of the gains is greater than 1, positive feedback is formed and the SCR path is triggered. Finally, the current density distribution of the SCR path between the anode and the cathode dominates, and the triggered SCR undertakes most of the ESD current discharge responsibility.

[0014] Compared with the prior art, the trigger voltage and holding voltage of the device of the present invention can be adjusted, so it can be flexibly used in low-power circuits and can effectively avoid the latch-up effect of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 It is a schematic diagram of the structure of a traditional MLSCR device.

[0016] Figure 2 It is a schematic diagram of the structure of the MLSCR device of the present invention.

[0017] Figure 3 It is an equivalent circuit diagram of the MLSCR device of the present invention.

[0018] Figure 4 It is a simulation current density diagram of a traditional MLSCR device.

[0019] Figure 5 It is a simulation current density diagram of the MLSCR device of the present invention.

[0020] Figure 6 It is an I-V characteristic curve diagram of a traditional MLSCR device.

[0021] Figure 7 It is an I-V characteristic curve diagram of the MLSCR device of the present invention.

[0022] Figure 8 It is the influence of different d1 on the holding voltage of the MLSCR device of the present invention.

[0023] Figure 9 It is the influence of different d1 on the trigger voltage of the MLSCR device of the present invention. Detailed implementation manners

[0024] The following will describe in detail the implementation manners of the present invention with reference to the accompanying drawings and embodiments.

[0025] The structure of a traditional MLSCR device is as Figure 1 shown, including a P substrate 1, an N well 2 and a P well 3 are provided on the P substrate 1. On the surface of the N well 2, an N+-region one 4 and a P+-region one 6 connected to the anode of the device are arranged from outside to inside, and are separated by a shallow trench isolation (STI) region one. On the surface of the P well 3, a P+-region two 12 and an N+-region two 10 connected to the cathode of the device are arranged from outside to inside, and are separated by a shallow trench isolation region two 11. On the surfaces of the N well 2 and the P well 3, a P+-region three is also provided. The P+-region three is separated from the P+-region one 6 by a shallow trench isolation region three 7, and is separated from the N+-region two 10 by a shallow trench isolation region four.

[0026] The silicon-controlled rectifier (SCR) is an effective ESD protection device. When it is turned on, its conduction efficiency is very high, and a high ESD protection level can be achieved even with a small layout area. It uses the avalanche breakdown of the reverse PN junction as the turn-on method. The MLSCR structure consists of parasitic NPN and PNP transistors, and two resistors Rn and Rp. When a voltage is applied between the positive and negative poles of the MLSCR and exceeds the reverse avalanche breakdown voltage of the PN junction, the reverse-biased PN in the NPN transistor enters the avalanche breakdown state, generating electron-hole pairs. The electron and hole currents flow through resistors Rn and Rp respectively, generating a voltage drop, which turns on the NPN and PNP transistors, thereby efficiently discharging ESD charges. The basic conduction principle of traditional MLSCR devices is avalanche breakdown. Therefore, reducing the SCR trigger voltage essentially means reducing the reverse pn junction avalanche breakdown voltage inside the SCR. The avalanche breakdown region of traditional MLSCR devices is the contact surface between the N+ well and P+, and the trigger voltage is too high.

[0027] To overcome its shortcomings, the structural schematic diagram of the MLSCR device of the present invention is as shown in Figure 2 shown, in the Figure 1 structure, the following modifications are made:

[0028] 1. Replace P+ region three with N+ region three 8, and remove the shallow trench isolation region four. Above the N+ region three 8 and the N+ region two 10, connect the two with the gate 9, thereby forming a MOS structure with the N+ region three 8 as the drain and the N+ region two 10 as the source, and the gate 9 is connected to the cathode of the device. At this time, the N well 2 and the P+ region one 6 also form a reverse-biased PN junction.

[0029] Through this setting, on the one hand, since N-type mainly conducts electricity through electrons and P-type mainly conducts electricity through holes, under the same conditions, the mobility of electrons is three times that of holes. Carrier mobility is used to represent the overall movement speed of electrons and holes inside the semiconductor. The high electron mobility means fast movement, which can accelerate the working speed of the device and make it have a stronger discharge ability.

[0030] On the other hand, by introducing a MOS structure into the device and using the characteristic of the low trigger voltage of NMOS to trigger the voltage, it can ensure that the device is turned off when the circuit is working normally.

[0031] 2. In the N well 2, an N shallow well 13 is set below the P+ region one 6. The concentration of the N shallow well 13 is less than that of the N well 2, thereby forming a PNP transistor with the P+ region one 6 as the emitter, the N shallow well 13 as the base, and the P well 3 as the collector.

[0032] 3. In the P-well 3, a P-shallow well 14 is disposed under the gate 9. The concentration of the P-shallow well 14 is less than that of the P-well 3. Thus, an NPN transistor is formed with the N-well 2 as the collector, the P-shallow well 14 as the base, and the N+ region three 8 and the N+ region two 10 as the emitters.

[0033] Exemplarily, the N-shallow well 13 connects at least the shallow trench isolation region one 5 and the shallow trench isolation region three 7, and the P-shallow well 14 connects at least the N+ region three 8 and the N+ region two 10.

[0034] Exemplarily, the concentration of the N-shallow well 13 is 1 / 10 of the concentration of the N-well 2, and the concentration of the P-shallow well 14 is 1 / 10 of the concentration of the P-well 3.

[0035] Its equivalent circuit diagram is as Figure 3 shown. In the figure, Rn+well represents the resistance of the N-well 2, Rp+well represents the resistance of the P-well 3, the MOS transistor is the MOS structure formed by the N+ region three 8 / N+ region two 10 / gate 9, the PNP transistor is the PNP transistor formed by the P+ region one 6 / N-shallow well 13 / P-well 3, and the NPN transistor is the NPN transistor formed by the N-well 2 / P-shallow well 14 / N+ region three 8 and the N+ region two 10.

[0036] According to this structure, when the anode of the device is subjected to a forward ESD stress, the reverse-biased PN junction formed by the N-well 2 and the P+ region one 6 will undergo avalanche breakdown. The electrons generated by the avalanche breakdown flow into the N-well 2 through the N+ region one 4, and the holes flow into the P-well 3. When the voltage drop of Rp+well is greater than the base-emitter forward-biased junction voltage of the parasitic NPN transistor, the NPN transistor conducts, and a large number of electrons are injected into the emitter, and then flow into the N-well 2 after being amplified by the NPN transistor. When the voltage drop on Rn+well reaches about 0.7V, the PNP transistor conducts, and the emitter junction injects a large number of holes into the N-well 2. The NPN triode and the PNP triode form a positive feedback system, continuously amplifying the current, generating a strong conductance modulation effect, showing a hysteresis phenomenon, and the device enters the working state.

[0037] To illustrate the principle and effect of the present invention, modeling and simulation are carried out in Sentuarus, and the steps are as follows:

[0038] 1. Modeling

[0039] First, parameters such as the size, material, and doping of the device are defined in the TCAD software through a scripting language, and each region is defined, including each STI region, doping region, substrate and well region, and the gate 9 region of the embedded MOS structure, to obtain a model of the novel MLSCR device. The detailed key parameters are listed in Table 1.

[0040] Table 1

[0041] Thickness (d1) of P shallow trench 14 0.5um Concentration of N well 2 (Nn) <![CDATA[1*10 17 cm -3 > Thickness (d2) of N shallow trench 13 0.5um Doping concentration of N shallow trench 13 (Nlow-n) <![CDATA[1*10 18 cm -3 > Thickness (Hpn) of N+ region and P+ region 1um Doping concentration of P well 3 (Np) <![CDATA[1*10 17 cm -3 > Thickness (Hgate) of gate 9 0.5um Doping concentration of P shallow trench 14 (Nlow-p) <![CDATA[1*10 18 cm -3 >

[0042] Secondly, after the model is established, mesh generation is performed on the device. The optimization region is defined in the device optimization file, and mesh initialization is carried out. Through theoretical analysis, it can be obtained that the current density is relatively large at the junctions such as the junction of N-well 2 and P-well 3, and the junction of N+ region and P-well 3. Therefore, the mesh needs to be further refined at the junctions until the software calculation results converge.

[0043] Then, a suitable physical model is selected. The breakdown of the SCR device involves the breakdown of bipolar diodes, and avalanche breakdown models, Auger recombination, indirect recombination, etc. need to be considered.

[0044] Finally, the I-V characteristic curve of the SCR device is measured. A series of simulated TLP currents are applied to the SCR device in the simulation to obtain a series of the device's maximum temperature-time curves. When the maximum temperature reaches the melting temperature of silicon, the TLP current at this time is the second breakdown current of the device, and the I-V characteristic curve at this current is the working curve of the device.

[0045] To further verify the structure proposed in the present invention and analyze the influence of the shallow well on the device, simulation comparison of the device is carried out based on Sentaurus TCAD. The main physical models used in the simulation include the avalanche breakdown model, Auger recombination model, etc.

[0046] The same TLP pulse is applied to the anode of the device, with a pulse width of 150 ns and a pulse rise time of 10 ns. The current density distributions of the MLSCR structure of the present invention and the traditional MLSCR at different times are extracted from the simulation results, as Figure 4 and 5 shown.

[0047] From Figure 4 (a) and (b), it can be seen that Figure (a) is the current density diagram of the traditional MLSCR device when it just starts to conduct, and Figure (b) is the current density diagram when the device is fully conducting. It can be seen from the figure that the current of the MLSCR device is mainly distributed near the anode, and there is also the P+ region II 12. The trigger circuit starts from the P+ region II 12 and returns to the cathode.

[0048] From Figure 5 (a) and (b), it can be seen that Figure (a) and Figure (b) are the current density diagrams of the MLSCR device of the present invention when it is just triggered and after it is fully conducting, respectively. It can be seen from the figure that the current conduction path of the MLSCR device of the present invention is P+ region II 12 → N shallow well 13 → N-well 2 → P-well 3 → P shallow well 14 → N+ region III 8, changing the current path. And the current is mainly distributed in the N shallow well 13 and P shallow well 14 regions.

[0049] After the diode is turned on, the current density distribution appears between the N-well 2 and the P-well 3. At this time, the parasitic transistors PNP and NPN are turned on, but the positive feedback has not been formed yet, and the current density distribution of the diode string path is still relatively concentrated. After the current increases, the current gain of the parasitic NPN transistor increases with the increase of the current. When the product of the gains is greater than 1, the positive feedback is formed and the SCR path is triggered. Finally, the current density distribution of the SCR path between the anode and the cathode dominates, and the triggered SCR undertakes most of the ESD current discharge responsibility.

[0050] Figure 6 Shows the TLP I-V measurement curve of the traditional MLSCR. It can be seen from the I-V curve that the trigger voltage of the MLSCR is 20.51V and the holding voltage is 18.47V. The TLP I-V measurement results of the MLSCR of the present invention are as Figure 7 shown. It can be seen that the trigger voltage is 5.86V and the holding voltage is 4.93V.

[0051] Obviously, both the trigger voltage and the holding voltage of the MLSCR device of the present invention are reduced because the NMOS transistor is embedded, which changes the current path. The N-shallow well 13 and the P-shallow well 14 embedded in the new device obviously also have a significant impact on the trigger voltage. After adding the shallow well, the transistor amplification factor is reduced, the surface path resistance is increased, and it is difficult for the electrons injected from the emitter to reach the anode through the surface path, so as to achieve the purpose of reducing the voltage.

[0052] According to the analysis, the fundamental reason for the too low holding voltage of the traditional MLSCR is the positive feedback mechanism of the parasitic triode inside the device. If the holding voltage increases, the tendency of the emitter-collector voltage to decrease is reduced, which can be achieved by weakening the positive feedback. The present invention proposes a design method to weaken the internal positive feedback mechanism of the device by reducing the amplification factor of the NPN triode, so as to increase the holding voltage of the device.

[0053] The amplification factor of the triode is expressed as:

[0054]

[0055] In the formula, W B and L B are the base width and the base minority diffusion length, η is the base drift coefficient, which is a constant, R E and R B are the parasitic resistances of the emitter and the base. It can be seen from the formula that β is proportional to R B and inversely proportional to R E .

[0056] In the present invention, β is reduced by reducing R B .

[0057] R B The calculation formula of

[0058]

[0059] is as follows: where q is the absolute value of the electric charge carried by a single elementary charge, which is a constant, μ p is the hole mobility, and N B is the base doping concentration. Increasing N B will decrease R B , resulting in a decrease in β.

[0060] In the MLSCR structure of the present invention, an NMOS (N-channel metal oxide semiconductor) is embedded in the cathode to reduce the trigger voltage, and shallow wells are added under both the N-well 2 and the P-well 3. The doping concentration of the added shallow wells is less than that of the lower wells, increasing the doping concentration of the transistor base region, reducing the sheet resistance of the base region, reducing the amplification factor of the transistor, and weakening the feedback mechanism of the positive transistor. The area of the device remains unchanged. The device exhibits better performance without increasing the layout area. The latch-up effect can be avoided, and the service life of the device can be improved.

[0061] To further study the influence of the shallow wells on the device, the designed structure was optimized. With other parameters unchanged, only the vertical dimensions (d1 and d2) of the two shallow wells were changed, and the holding voltage and the change of the holding voltage of the MLSCR of the present invention were compared. The I-V characteristic curves are as Figure 8 and 9 shown. It can be seen that as d increases, the holding voltage of the MLSCR of the present invention becomes larger and the trigger voltage also becomes larger.

[0062] Table 2 Influence of the change of d on the holding voltage and trigger voltage of the new device

[0063] d1 / μm Vh / V Vt1 / V 0.35 4.88 5.81 0.40 4.93 5.86 0.45 4.97 5.93

[0064] In summary, in the MLSCR structure of the present invention, MOS, diodes, and transistors are effectively combined in a single device structure, effectively improving the current discharge capacity of the device. At the same time, new wells, namely N shallow well 13 and P shallow well 14, are added to the N-well 2 and P-well 3 of the device. The doping concentration of the added new wells is smaller than that of the original wells, changing the amplification factor of the triode and effectively improving the performance of the device. Specifically, its trigger voltage and holding voltage are lower than those of traditional devices. And the trigger voltage and holding voltage can be adjusted and applied to flexible low supply voltages. At the same time, its trigger voltage is also greater than the voltage in the low power supply circuit, thus effectively avoiding the latch-up effect of the device.

Claims

1. A silicon rectifier device for a low-power circuit, comprising a P substrate, an N well and a P well located on the P substrate. On the surface of the N well, an N+ region one and a P+ region one connected to the anode of the device are arranged from outside to inside and separated by a shallow trench isolation region one. The N well and the P+ region one form a reverse-biased PN junction. On the surface of the P well, a P+ region two and an N+ region two connected to the cathode of the device are arranged from outside to inside and separated by a shallow trench isolation region two. It is characterized in that an N+ region three is also arranged on the surface of the N well and the surface of the P well. The N+ region three and the P+ region one are separated by a shallow trench isolation region three. A gate is used to connect the N+ region three and the N+ region two, so as to form a MOS structure with the N+ region three as the drain and the N+ region two as the source; wherein the gate is connected to the cathode of the device; in the N well, an N shallow well is arranged below the P+ region one. The concentration of the N shallow well is less than that of the N well, so as to form a PNP transistor with the P+ region one as the emitter, the N shallow well as the base, and the P well as the collector; in the P well, a P shallow well is arranged below the gate. The concentration of the P shallow well is less than that of the P well, so as to form an NPN transistor with the N well as the collector, the P shallow well as the base, and the N+ region three and the N+ region two as the emitters.

2. The silicon rectifier device for a low-power circuit according to claim 1, It is characterized in that the concentration of the N shallow well is 1 / 10 of the concentration of the N well, and the concentration of the P shallow well is 1 / 10 of the concentration of the P well.

3. The silicon rectifier device for a low-power circuit according to claim 1, It is characterized in that the N shallow well at least connects the shallow trench isolation region one and the shallow trench isolation region three, and the P shallow well at least connects the N+ region three and the N+ region two.

4. The silicon rectifier device for a low-power circuit according to claim 1, It is characterized in that the current conduction path of the silicon rectifier device is P+ region two → N shallow well → N well → P well → P shallow well → N+ region three, and the current is mainly distributed in the N shallow well and P shallow well regions; after the diode is turned on, the current density distribution appears between the N well and the P well. At this time, the parasitic transistors PNP and NPN are turned on, but positive feedback has not been formed; after the current increases, the current gain of the parasitic NPN transistor increases with the increase of the current. When the product of the gains is greater than 1, positive feedback is formed and the SCR path is triggered. Finally, the current density distribution of the SCR path between the anode and the cathode dominates, and the triggered SCR undertakes most of the ESD current discharge responsibility.

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