A method of manufacturing a semiconductor device
By adding a hard mask during the semiconductor device manufacturing process, the problem of pattern erosion defects during chemical mechanical planarization was solved, resulting in higher process reliability and device quality.
Patent Information
- Application Number
- CN202110245765.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2021-03-05
- Publication Date
- 2025-12-19
- Estimated Expiration
- 2041-03-05
AI Technical Summary
During the fabrication of semiconductor devices, the thickness gradient difference between regions with high and low pattern density during chemical mechanical planarization can lead to pattern erosion defects, affecting subsequent processes and device reliability.
By sequentially forming first and second hard masks on a substrate, etching a second patterned structure using photoresist patterns, forming an oxide isolation layer on it, removing the second hard mask, making the hard mask heights on the first and second patterned structures equal, and then performing chemical mechanical planarization.
This reduces patterning etch defects, ensures the smooth progress of subsequent processes, and improves device reliability.
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Figure CN115020409B_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of semiconductor, and in particular to a manufacturing method of semiconductor device. BACKGROUND
[0002] In the process of preparing semiconductor device, there are areas with high pattern density and areas with low pattern density in the chip, and there is height difference between the two areas. When chemical mechanical planarization (CMP) is performed on the two areas, pattern erosion defects will be formed in the pattern density area due to the CMP. The defects will cause deviation in the subsequent process, and even failure of the device. SUMMARY
[0003] In view of the above problems, the present application is proposed to provide a manufacturing method of semiconductor device which overcomes the above problems.
[0004] The embodiment of the present application provides a manufacturing method of semiconductor device, comprising:
[0005] forming a first hard mask and a second hard mask on a substrate in sequence, wherein the substrate comprises a first area and a second area, and the first area comprises a first patterned structure;
[0006] forming a photoresist pattern on the second area, and etching the second area to form a second patterned structure in the second area by taking the photoresist pattern as a mask;
[0007] forming an oxidation isolation layer on the second patterned structure;
[0008] removing the second hard mask, so that the height of the first hard mask on the first patterned structure is equal to the height of the first hard mask on the second patterned structure.
[0009] Further, the first hard mask is specifically any one of the following materials:
[0010] SiN and SiO2.
[0011] Further, the second hard mask is specifically a metal hard mask.
[0012] Further, the metal hard mask is specifically any one of the following materials:
[0013] AlN, W, TiN and Ti.
[0014] Further, the thickness of the second hard mask is
[0015] Further, the filling the oxide isolation layer after the second patterning area, further comprises:
[0016] Chemical mechanical planarization processing the oxide isolation layer.
[0017] Further, the removing the second hard mask, comprises:
[0018] Wet etching the second hard mask by using a preset etchant.
[0019] Further, the preset etchant is a mixture of hydrogen peroxide, ammonia and sulfuric acid.
[0020] Further, the temperature of the preset etchant is 10-200 DEG C.
[0021] Further, the semiconductor device is a memory, the first area is a peripheral circuit area, and the second area is a memory cell area.
[0022] Further, before forming the first hard mask, further comprising:
[0023] Forming a gate pattern on the first area.
[0024] Further, the second patterning structure is a bit line pattern.
[0025] The one or more technical solutions in the embodiments of the present application have at least the following technical effects or advantages:
[0026] The present application provides a semiconductor device manufacturing method, comprising: sequentially forming a first hard mask and a second hard mask on a substrate, the substrate comprising a first area and a second area, the first area comprising a first patterning structure; forming a photoresist pattern on the second area, etching the second area with the photoresist pattern as a mask to form a second patterning structure on the second area; forming an oxide isolation layer on the second patterning structure; removing the second hard mask, so that the height of the first hard mask on the first patterning structure is equal to the height of the first hard mask on the second patterning structure, and then by increasing the mask, i.e. increasing the second hard mask, when etching to form the second patterning structure, although the second hard mask above the second patterning structure is consumed, by removing the second hard mask on the first patterning structure, the height of the first hard mask on the first patterning structure is equal to the height of the first hard mask on the second patterning structure, and then the graphing erosion defect is reduced, so as to facilitate the subsequent process. BRIEF DESCRIPTION OF DRAWINGS
[0027] Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments with reference made to the accompanying drawings. The drawings are for purposes of illustration only and are not intended to be limiting in
[0028] Figure 1 A device structure formed by using a chemical mechanical planarization process to remove a step in the prior art is shown in a schematic view;
[0029] Figure 2 A flow chart of a method of fabricating a semiconductor device in accordance with an embodiment of the present application is shown in a schematic view;
[0030] Figures 3-9 A structure of a semiconductor device fabrication process in accordance with an embodiment of the present application is shown in a schematic view. DETAILED DESCRIPTION
[0031] Example embodiments of the present disclosure will be described more fully hereinafter with reference to the accompanying drawings. While example embodiments of the present disclosure are shown in the drawings, it is to be understood that the present disclosure is not to be limited to the embodiments shown in the drawings, which are provided for illustration only. Rather, the present disclosure is to cover all modifications, equivalents, and alternatives falling within the scope of the present disclosure. Rather, the embodiments are provided for enabling a thorough and complete disclosure of the present disclosure and to convey full scope of the present disclosure to those skilled in the art.
[0032] Various schematic views of structures in accordance with embodiments of the present disclosure are shown in the drawings. These drawings are not drawn to scale, in which certain details are exaggerated for clarity and others are omitted, and the relative sizes and positions of various regions, layers, and the relative positions of the regions / layers are shown only schematically. The shapes, sizes, and relative positions of the regions / layers shown in the drawings are not intended to be limiting, and regions / layers having different shapes, sizes, and relative positions can be used in actual implementations depending on design, manufacturing, and technological constraints and considerations.
[0033] In the context of the present disclosure, when a layer / element is referred to as being "on" another layer / element, it can be directly on the other layer / element or intervening layers / elements can be present therebetween. Also, when a layer / element is referred to as being "under" or "beneath" another layer / element, it can be directly on the other layer / element or intervening layers / elements can be present therebetween.
[0034] In the prior art, as shown in FIG. 1, a device structure 100 is formed by using a chemical mechanical planarization process to remove a step 102 in a semiconductor device fabrication process. Figure 1As shown, in order to improve or eliminate the step difference, a chemical mechanical planarization (CMP) process can be performed on the high area after the deposition of the interlayer dielectric isolation layer, so as to reduce the step difference by the CMP. However, the larger the step difference eliminated by the CMP is, the more likely the pattern erosion defect (erosion) in the pattern dense area in the center of the memory cell region.
[0035] The present application adopts the method of increasing the mask to eliminate and improve the erosion defect in the pattern dense area caused by the step difference, and the specific implementation is as follows:
[0036] The embodiment of the present application provides a manufacturing method of a semiconductor device, which comprises the following steps of: Figure 2
[0037] S201, sequentially forming a first hard mask and a second hard mask on a substrate, the substrate comprising a first region and a second region, and the first region comprising a first patterned structure.
[0038] S202, forming a photoresist pattern on the second region, and etching the second region by taking the photoresist pattern as a mask, so as to form a second patterned structure in the second region.
[0039] S203, forming an oxidation isolation layer on the second patterned structure.
[0040] S204, removing the second hard mask, so that the height of the first hard mask on the first patterned structure is equal to the height of the first hard mask on the second patterned structure.
[0041] The following will take the CMP process after the bit line etching in the manufacturing of a DRAM device as an example to specifically describe the embodiment of the present application. The first region A is a peripheral circuit region, and the second region B is a memory cell region. Before the following embodiment steps, the active region, the isolation region, the buried gate transistor and the bit line contact part and other structures can be formed on the second region B of the substrate.
[0042] The first region A can be formed with the first patterned structure, for example, the gate pattern.
[0043] Specifically, as shown in the figure, first, the substrate 30 comprises a metal layer 302 and a mask layer 303 formed on a Si substrate 301 in sequence, and the metal layer 302 is partially used to form the first region A and partially used to form the second region B. Figure 3 The first region A is used to form the gate line, and the second region B is used to form the bit line.
[0044] Next, as shown in the figure, the first hard mask 301 is formed on the substrate 30, and the second hard mask 302 is formed on the first hard mask 301.
[0045] Figure 4 As shown, a first patterned structure 304 is formed in the first region A. Specifically, it is formed by etching.
[0046] Specifically, the mask layer 303 is used to protect the metal layer 302 during etching.
[0047] After forming the first patterned structure 304, an oxide isolation layer is formed on the first patterned structure 304 to fill the gaps in the first patterned structure 304.
[0048] Then, as Figure 5 As shown, a first hard mask 305 and a second hard mask 306 are sequentially formed on the substrate 30. The substrate 30 includes the first region A and the second region B, and the first region A includes the first patterned structure 304.
[0049] Specifically, the first hard mask 305 can be any of the following materials: SiN and SiO2.
[0050] The first hard mask 305 is made of the same material as the mask layer 303.
[0051] The second hard mask 306 is specifically a metal hard mask. The body of the metal hard mask can be any of the following materials:
[0052] AlN, W, TiN, and Ti.
[0053] Therefore, the first hard mask 305 and the second hard mask 306 are made of different materials.
[0054] The thickness of the second hard mask 30 is This thickness is used to facilitate subsequent chemical mechanical planarization.
[0055] Then, as Figure 6 As shown, in step S202, a photoresist pattern is formed on the second hard mask 306. This pattern exposes the locations to be etched. The photoresist pattern on the second region B corresponds to the bit line pattern to be formed. The second region B is etched using this photoresist pattern as a mask to form a second patterned structure 307, which may be a bit line pattern. The second patterning density corresponding to the second patterned structure 307 is greater than the first patterning density corresponding to the first patterned structure 304.
[0056] Specifically, during the second patterning etching of the second region B, the second hard mask 306 is consumed. Therefore, the aforementioned preset thickness is used. The second hard mask 306 ensures that during the second patterning etching of the second region B, only the second hard mask 306 is consumed, without consuming the first hard mask 305. The second hard mask 306 can be partially consumed or completely consumed to ensure that the height of the underlying first hard mask 306 remains unchanged.
[0057] Next, as Figure 7 As shown, in step S203, an oxide isolation layer 308 is formed on the second patterned structure 307 to achieve the isolation function.
[0058] After the formation of the oxide isolation layer 308, as Figure 8 As shown, it also includes: chemical mechanical planarization treatment of the oxide isolation layer 308.
[0059] Finally, as Figure 9 As shown, S204 is executed to remove the second hard mask 306, resulting in the height of the first hard mask 302 on the first patterned structure 304 being equal to the height of the first hard mask 302 on the second patterned structure 307.
[0060] Since the second hard mask 306 is made of any one of AlN, W, TiN and Ti, these materials are easily removed by wet etching solutions.
[0061] When removing the second hard mask 306, a wet etching process using a preset etchant is employed. Of course, dry etching, ion etching, or other methods can also be used; no specific method is specified here.
[0062] When the second hard mask 306 is removed by wet etching using a preset etchant, the preset etchant is a mixture of hydrogen peroxide (H2O2), ammonia (NH4OH), and sulfuric acid (H2SO4).
[0063] Specifically, the operating temperature of the preset etchant is 10–200°C. This temperature is used to ensure that the etchant can quickly remove the second hard mask 306.
[0064] This invention provides a method for manufacturing semiconductor devices that can be applied not only to memories with memory cell regions and peripheral circuit regions, but also to other semiconductor devices with regions of patterned structures of different densities. By employing this chemical-mechanical planarization method, patterning etching defects can be effectively improved or eliminated, facilitating subsequent processes. These subsequent processes specifically include forming landing pads in the memory cell regions and bit lines in the peripheral circuit regions, etc.
[0065] The one or more technical solutions in the embodiments of the present application have at least the following technical effects or advantages:
[0066] The present application provides a semiconductor device manufacturing method, comprising: sequentially forming a first hard mask and a second hard mask on a substrate, the substrate comprising a first region and a second region, the first region comprising a first patterning structure; forming a photoresist pattern on the second region, and etching the second region to form a second patterning structure using the photoresist pattern as a mask; forming an oxidation isolation layer on the second patterning structure; removing the second hard mask, so that the height of the first hard mask on the first patterning structure is equal to the height of the first hard mask on the second patterning structure, and then by increasing the mask, i.e. increasing the second hard mask, so that when etching to form the second patterning structure, the second hard mask is consumed, finally, by removing the second hard mask on the first patterning structure, so that the height of the first hard mask on the first patterning structure is equal to the height of the first hard mask on the second patterning structure, thereby reducing the patterned etching defects, so as to facilitate the subsequent process.
[0067] In the above description, the patterning, etching, chemical mechanical planarization and other technical details of each layer are not described in detail. However, those skilled in the art should understand that the layers, regions and the like with the required shape can be formed by various technical means. In addition, those skilled in the art can also design methods that are not exactly the same as the methods described above in order to form the same structure. In addition, although each embodiment is described above, this does not mean that the measures in each embodiment cannot be used advantageously in combination.
[0068] Although the preferred embodiments of the present application have been described, those skilled in the art can make further changes and modifications to these embodiments once they know the basic inventive concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications falling within the scope of the present application.
[0069] Obviously, those skilled in the art can make various modifications and variations to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include these modifications and variations.
Claims
1. A method of manufacturing a semiconductor device, characterized by, The application relates to a semiconductor device manufacturing method. Forming a first hard mask and a second hard mask on a substrate in sequence, the substrate comprising a first region and a second region, the first region comprising a first patterned structure; Forming a photoresist pattern on the second region, and etching the second region to form a second patterned structure in the second region as a mask of the photoresist pattern; Forming an oxidation isolation layer on the second patterned structure; Removing the second hard mask, so that the height of the first hard mask on the first patterned structure is equal to the height of the first hard mask on the second patterned structure.
2. The method of claim 1, wherein, The first hard mask is specifically any one of SiN and SiO2.
3. The method of claim 1, wherein, The second hard mask is a metal hard mask.
4. The method of claim 3, wherein, The metal hard mask is specifically any one of AlN, W, TiN and Ti.
5. The method of claim 1, wherein, a thickness of the second hard mask is 6. The method of claim 1, wherein, After forming the oxidation isolation layer on the second patterned structure, the method further comprises: Carrying out chemical mechanical planarization treatment on the oxidation isolation layer.
7. The method of claim 1, wherein, The removing of the second hard mask comprises: Removing the second hard mask by wet etching with a preset etchant.
8. The method of claim 7, wherein, The preset etchant is a mixture of hydrogen peroxide, ammonia and sulfuric acid.
9. The method of claim 7, wherein, The temperature of the preset etchant is 10-200 DEG C.
10. The method of one of claims 1 to 9, characterized in that, The semiconductor device is a memory, the first region is a peripheral circuit region, and the second region is a memory cell region.
11. The method of claim 10, wherein, Before forming the first hard mask, the method further comprises: Forming a gate pattern on the first region.
12. The method of claim 10, wherein, The second patterned structure is a bit line pattern.
Citation Information
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