Dac circuit with isolation circuit and method of controlling a dac circuit

Abstract

A digital-to-analog conversion circuit and a method of controlling the same are provided. The digital-to-analog conversion circuit includes N digital-to-analog conversion modules, N being an integer greater than 1, each of the digital-to-analog conversion modules including: an input port configured to provide a digital signal; a first control end configured to provide a first control signal; an output end; a digital-to-analog converter including a switched resistor network configured to generate an analog voltage corresponding to the digital signal at a first node based on at least a first reference voltage; and an isolation circuit connected between the first node and a second node and configured to selectively turn on or turn off the first node and the second node according to the first control signal at the first control end, wherein the second node is coupled to the output end.

Description

Technical Field

[0001] This disclosure relates to the field of circuit technology, and in particular to a digital-to-analog converter circuit and a method for controlling the digital-to-analog converter circuit. Background Technology

[0002] Digital-to-analog converters (DACs) are used to convert digital signals into analog signals and typically include a network of switched resistors. In some types of DACs, as the input digital signal changes, the switching state of the switched resistor network changes, causing the equivalent impedance between the reference voltage terminals to change accordingly. That is, the output current at the reference voltage terminals changes with the input digital signal. In the case of multi-channel DACs, this can lead to crosstalk between channels, thus affecting the accuracy of the output voltage. Summary of the Invention

[0003] It would be beneficial to provide a mechanism to alleviate, reduce, or even eliminate one or more of the aforementioned problems.

[0004] According to one aspect of this disclosure, a digital-to-analog converter circuit is provided, comprising: N digital-to-analog converter modules, where N is an integer greater than 1, each digital-to-analog converter module comprising: an input port configured to provide a digital signal; a first control terminal configured to provide a first control signal; an output terminal; a digital-to-analog converter including a switched resistor network configured to generate an analog voltage corresponding to the digital signal at a first node based at least on a first reference voltage; and an isolation circuit connected between the first node and a second node, configured to selectively turn the first node and the second node on or off according to the first control signal at the first control terminal, wherein the second node is coupled to the output terminal.

[0005] According to another aspect of this disclosure, a method for controlling a digital-to-analog converter circuit is provided, the method comprising: at a first time moment, in each of NM digital-to-analog converter modules out of N digital-to-analog converter modules, the isolation circuit disconnects a first node from a second node, where M is an integer greater than or equal to 1 and less than N; at a second time moment after the first time moment, in each of the M digital-to-analog converter modules other than the NM digital-to-analog converter modules, an updated digital signal at the input port is applied to the switched resistor network; and at a third time moment after the second time moment, in each of the NM digital-to-analog converter modules, the isolation circuit connects the first node to the second node.

[0006] These and other aspects of this disclosure will be apparent from the embodiments described below, and will be elucidated with reference to the embodiments described below. Attached Figure Description

[0007] Further details, features, and advantages of this disclosure are disclosed in the following description of exemplary embodiments in conjunction with the accompanying drawings, in which:

[0008] Figure 1A This is a schematic circuit diagram of a switched resistor network used in digital-to-analog conversion circuits in related technologies;

[0009] Figure 1B It is a schematic circuit diagram of a digital-to-analog converter circuit in related technologies;

[0010] Figure 2 This is a schematic block diagram illustrating a digital-to-analog converter circuit according to an exemplary embodiment of the present disclosure;

[0011] Figure 3 This is an exemplary circuit diagram illustrating a digital-to-analog converter circuit according to an exemplary embodiment of the present disclosure;

[0012] Figure 4A , Figure 4B and Figure 4C This is an exemplary circuit diagram illustrating a sample-and-hold circuit according to an exemplary embodiment of the present disclosure;

[0013] Figure 5 This is an exemplary circuit diagram illustrating a gating circuit according to an exemplary embodiment of the present disclosure;

[0014] Figure 6 This is a flowchart illustrating a method for controlling a digital-to-analog converter circuit according to an exemplary embodiment of the present disclosure;

[0015] Figure 7 This is a timing diagram illustrating the operation of a digital-to-analog converter circuit according to an exemplary embodiment of the present disclosure. Detailed Implementation

[0016] It will be understood that although the terms first, second, third, etc., may be used herein to describe various elements, components, areas, layers, and / or parts, these elements, components, areas, layers, and / or parts should not be limited by these terms. These terms are used only to distinguish one element, component, area, layer, or part from another. Therefore, the first element, component, area, layer, or part discussed below may be referred to as the second element, component, area, layer, or part without departing from the teachings of this disclosure.

[0017] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprising” and / or “including” as used in this specification designate the presence of the stated features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items, and the phrase “at least one of A and B” includes only A, only B, and both A and B.

[0018] It will be understood that when a component or layer is referred to as "connected to another component or layer" or "coupled to another component or layer," it may be directly connected to another component or layer or directly coupled to another component or layer, or there may be intermediate components or layers. Conversely, when a component is referred to as "directly connected to another component or layer" or "directly coupled to another component or layer," no intermediate components or layers are present. The terms "connected" and "coupled" are used interchangeably herein. As used herein, the terms "signal active" and "signal inactive" have meanings well understood in the art. For example, for edge-triggered, "signal active" means either rising edge active or falling edge active. For level-triggered, "signal active" means either high level active (N-type logic) or low level active (P-type logic). "Signal inactive" means the opposite of "signal active."

[0019] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having meanings consistent with their meanings in the relevant field and / or the context of this specification, and will not be interpreted in an idealized or overly formal sense unless expressly defined herein.

[0020] Figure 1A This is a schematic circuit diagram of a 100A switched resistor network used in digital-to-analog conversion circuits in related technologies. (Example:) Figure 1A As shown, the 100A switched resistor network is composed of an R-2R ladder resistor network, where R represents unit resistance, S0 is a fixed bit, and B1~BN represent the individual bits of the digital-to-analog converter circuit. Different codes are obtained by configuring each bit, i.e., the input digital signal, thereby obtaining the signal from V... REFP To V REFNThe output of the quantization result V OUT It can be seen that the characteristic of the R-2R ladder resistor network is that, without considering the arm resistance, the equivalent resistance looking to the left from each bit node is 2R, but from V... REFP To V REFN The equivalent resistance changes with the value of the code, i.e., V REFP The supplied current will vary depending on the encoding. When using the same V REFP When supplying multiple such R-2R ladder resistor networks to achieve multi-channel digital-to-analog conversion, V REFP The supplied current varies with the encoding of each channel, which leads to crosstalk between channels and affects the accuracy of the output voltage of each channel.

[0021] Figure 1B This is a schematic circuit diagram of the digital-to-analog converter circuit 100B in related technologies. For example... Figure 1B As shown, the reference voltage VBG can be divided by resistors and supplied to the digital-to-analog converter 102 via the reference voltage buffer 101 to provide the reference voltage V. REFP V REFN It can be connected to an ideal ground or other reference voltage. The switched resistor network in the digital-to-analog converter 102 can be, for example, a... Figure 1A The diagram shows an R-2R ladder resistor network. L_DAC is the identifier signal for writing data to the digital-to-analog converter 100B, which can be triggered by a rising edge. CODE is the digital signal input of the digital-to-analog converter 100B. When a short high pulse is input to L_DAC, the prepared CODE value is written to the switched resistor network in the digital-to-analog converter 102, thereby changing the output of the digital-to-analog converter 100B, and the new output voltage V is then passed through the output buffer 103. OUT Output. As mentioned earlier, switched resistor networks, such as R-2R ladder resistor networks, experience transient current jumps when switching digital signal inputs. Due to the limited bandwidth of the reference voltage buffer 101, it cannot adjust quickly, leading to V... REFP The voltage is pulled down rapidly. When using the same V REFP When supplying multiple such switched resistor networks to achieve multi-channel digital-to-analog conversion, V REFP The supplied current varies with the encoding of each channel, which leads to crosstalk between channels and affects the accuracy of the output voltage of each channel.

[0022] Exemplary embodiments of this disclosure will now be described in detail, which can be used for many reasons, such as mitigating or reducing these undesirable loss of accuracy.

[0023] Figure 2This is a schematic block diagram illustrating a digital-to-analog converter circuit 200 according to an exemplary embodiment of the present disclosure. Figure 2 As shown, the digital-to-analog converter circuit 200 includes N digital-to-analog converter modules 201-1 to 201-N, where N is an integer greater than 1. Each digital-to-analog converter module can have the same structure; the following description uses digital-to-analog converter module 201-1 as an example. Digital-to-analog converter module 201-1 includes an input port 202-1, a first control terminal 203-1, an output terminal 204-1, a digital-to-analog converter 205-1, and an isolation circuit 206-1.

[0024] Input port 202-1 is configured to provide the digital signal CODE1. First control terminal 203-1 is configured to provide the first control signal L_DACN_1. Digital-to-analog converter 205-1 includes a switched resistor network configured to operate at least based on a first reference voltage (e.g., ...). Figure 1A or Figure 1B V in REFP An analog voltage corresponding to the digital signal CODE1 is generated at the first node n1-1. An isolation circuit 206-1 is connected between the first node n1-1 and the second node n2-1, and is configured to selectively turn the first node n1-1 and the second node n2-1 on or off according to the first control signal L_DACN_1 at the first control terminal 203-1. The second node n2-1 is coupled to the output terminal 204-1. It is understood that the second node n2-1 can be directly connected to the output terminal 204-1, or indirectly connected to the output terminal 204-1 through an intermediate circuit (e.g., an output buffer).

[0025] The structure of the digital-to-analog converter module 201-N is the same as that of the digital-to-analog converter module 201-1, including an input port 202-N, a first control terminal 203-N, an output terminal 204-N, a digital-to-analog converter 205-N, a first node n1-N, an isolation circuit 206-1, and a second node n2-N. For the sake of simplicity, the digital-to-analog converter module 201-N will not be described in detail here.

[0026] N digital-to-analog converter modules 201-1 to 201-N correspond to N digital-to-analog conversion channels, and each module generates the analog voltage corresponding to its channel based on a first reference voltage and the corresponding digital signal. The first reference voltage may fluctuate due to updates to the digital signals in one or more channels. To prevent interference from updates to the digital signals of other channels, channels that do not undergo digital signal updates can have their first and second nodes disconnected via their corresponding isolation circuits. This ensures that the voltage output from the output terminal coupled to the second node is unaffected by fluctuations in the first reference voltage, thereby eliminating crosstalk between channels.

[0027] According to some embodiments, the switched resistor network includes, but is not limited to, any of an R-2R ladder resistor network, an inverted R-2R ladder resistor network, and a weighted resistor network. It is understood that the inventive concept of this disclosure is applicable to various digital-to-analog converters where the current supplied by the reference voltage varies with the input digital signal.

[0028] According to some embodiments, the structures of the N digital-to-analog conversion modules may be partially the same or different. For example, the switched resistor networks in the N digital-to-analog conversion modules may be partially the same or different.

[0029] According to some embodiments, the digital-to-analog converter circuit further includes a first operational amplifier. The first operational amplifier includes: a first amplifier output configured to output the first reference voltage; a non-inverting input configured to receive a reference voltage or a voltage divider of the reference voltage; and an inverting input connected to the first amplifier output.

[0030] Figure 3 This is an exemplary circuit diagram illustrating a digital-to-analog converter circuit 300 according to an exemplary embodiment of the present disclosure. Figure 3 As shown, the digital-to-analog converter circuit 300 includes a first operational amplifier 301 and N digital-to-analog converter modules 307-1 to 307-N, where N is an integer greater than 1. The first operational amplifier 301 uses a voltage divider of the reference voltage VBG as input to provide a first reference voltage to the digital-to-analog converters corresponding to the multiple digital-to-analog converter channels. The first operational amplifier 301 acts as a reference voltage buffer, reducing the impact of load fluctuations on the reference voltage. Compared to the conventional scheme that uses a single reference voltage buffer to drive one digital-to-analog converter, in... Figure 3 In the example, the digital-to-analog converter with N channels only requires one reference voltage buffer, saving a lot of circuit area and power consumption, while ensuring the performance of channel crosstalk.

[0031] The following will combine Figure 3 Taking the digital-to-analog converter module 307-1 as an example, the internal structure of the digital-to-analog converter module is described in detail. It can be understood that each digital-to-analog converter module has the same structure, and the reference numerals in digital-to-analog converter module 307-N that correspond to those in digital-to-analog converter module 307-1 specify the same circuit elements.

[0032] According to some embodiments, the isolation circuit includes: a gating circuit configured to generate a gating signal based on a first control signal; and a sample-and-hold circuit configured to turn on the first node and the second node in response to the gating signal being valid, and to turn off the first node and the second node and hold the analog voltage in response to the gating signal being invalid.

[0033] exist Figure 3In the example, the gating circuit 304-1 is configured to generate gating signals CHN1 and CHP1 based on the first control signal L_DACN_1. The sample-and-hold circuit 305-1 is configured to turn on the first node and the second node in response to the gating signals CHN1 and CHP1 being valid, and to turn off the first node and the second node and hold the analog voltage in response to the gating signals CHN1 and CHP1 being invalid. The gating signals CHN1 and CHP1 generated by the gating circuit 304-1 in response to the first control signal L_DACN_1 control the on / off state of the first node and the second node, and when the first node and the second node are off, the sample-and-hold circuit 305-1 holds the analog voltage output by the digital-to-analog converter, so that the output voltage of the first digital-to-analog converter channel that does not undergo digital signal updates is not affected by digital signal updates of other channels and fluctuations in the first reference voltage.

[0034] According to some embodiments, the sample-and-hold circuit includes: a first controllable switch connected between a first node and a second node, configured to be turned on in response to a valid strobe signal and turned off in response to an invalid strobe signal; and a first capacitor connected between the second node and a ground terminal. When the first controllable switch is turned off, the first capacitor connected between the second node and the ground terminal will maintain its voltage before the first controllable switch was turned off, thereby maintaining the voltage output at the output terminal substantially unchanged, and thus simultaneously achieving multi-channel digital-to-analog conversion and elimination of crosstalk between multiple channels.

[0035] According to some embodiments, the first controllable switch includes any one of an N-type field-effect transistor, a P-type field-effect transistor, and a complementary field-effect transistor. It is understood that the specific type of the first controllable switch can be selected based on the required transmission setup time for the corresponding channel.

[0036] According to some embodiments, the sample-and-hold circuit further includes a second capacitor connected between the first node and ground. Maintaining the analog voltage output by the switched resistor network using the second capacitor allows the voltage at the second node to recover more quickly to the voltage before the first controllable switch was turned off when the first controllable switch is turned off and then back on, thereby improving the stability of the output voltage.

[0037] The following will refer to Figure 4A , Figure 4B and Figure 4C Detailed descriptions are given for sample-and-hold circuits composed of complementary field-effect transistors, P-type field-effect transistors, and N-type field-effect transistors, respectively.

[0038] Figure 4A This is an exemplary circuit diagram illustrating a sample-and-hold circuit 400A according to an exemplary embodiment of the present disclosure. Figure 4AAs shown, the sample-and-hold circuit 400A includes a complementary field-effect transistor (FET) M0, a first capacitor C1, and a second capacitor C2 located between a first node n1 and a second node n2. Gating signals CHN1 and CHP1 are supplied to the gates of the N-type FET and the P-type FET in M0, respectively, to control the on / off state of M0. When FET CHN1 is valid at a low level and FET CHP1 is valid at a high level, M0 turns on in response to the valid FET signals. At this time, the channel can perform digital signal updates and digital-to-analog conversion. When FET CHN1 is invalid at a high level and FET CHP1 is invalid at a low level, M0 turns off in response to the invalid FET signals. The voltage at the second node n2 held by the first capacitor C1 before M0 turned off is maintained, thus maintaining the stability of the output voltage. Simultaneously, the second capacitor C2 holds the analog voltage output from the switched resistor network at the first node n1, allowing the voltage at the second node n2 to recover more quickly when M0 turns on again. In some examples, the second capacitor C2 is not required.

[0039] Figure 4B This is an exemplary circuit diagram illustrating a sample-and-hold circuit 400B according to an exemplary embodiment of the present disclosure. Figure 4B As shown, the sample-and-hold circuit 400B includes a P-type field-effect transistor M1, a first capacitor C1, and a second capacitor C2 located between a first node n1 and a second node n2. A strobe signal CHP2 is supplied to the gate of the P-type field-effect transistor M1 to control the on / off state of M1. When the strobe signal CHP2 is a valid high level, M1 turns on in response to the valid strobe signal, allowing for digital signal updates and digital-to-analog conversion. When the strobe signal CHP2 is an invalid low level, M1 turns off in response to the invalid strobe signal. The voltage at the second node n2 held by the first capacitor C1 before M1 turns off is maintained, thus ensuring a stable output voltage. Simultaneously, the second capacitor C2 holds the analog voltage output from the switched resistor network at the first node n1, allowing the voltage at the second node n2 to recover more quickly when M1 turns on again. In some examples, the second capacitor C2 is not necessary.

[0040] Figure 4C This is an exemplary circuit diagram illustrating a sample-and-hold circuit 400C according to an exemplary embodiment of the present disclosure. Figure 4CAs shown, the sample-and-hold circuit 400C includes an N-type field-effect transistor M2, a first capacitor C1, and a second capacitor C2 located between a first node n1 and a second node n2. A strobe signal CHN2 is supplied to the gate of the N-type field-effect transistor M2 to control the on / off state of M2. When the strobe signal CHN2 is a valid low level, M2 is turned on in response to the valid strobe signal. At this time, the channel can perform digital signal updates and digital-to-analog conversion. When the strobe signal CHN2 is an invalid high level, M2 is turned off in response to the invalid strobe signal. The voltage at the second node n2 before the switch was turned off is maintained by the first capacitor C1, thereby maintaining the stability of the output voltage. Simultaneously, the analog voltage output by the switched resistor network is maintained at the first node n1 by the second capacitor C2, allowing the voltage at the second node n2 to recover more quickly when M2 is turned on again. In some examples, the second capacitor C2 is not necessary.

[0041] According to some embodiments, the digital-to-analog converter circuit further includes a second operational amplifier, the second operational amplifier comprising: a second amplifier output terminal configured to output an output voltage proportional to the analog voltage; a non-inverting input terminal connected to a second node; and an inverting input terminal connected to the second amplifier output terminal. It should be understood that the inverting input terminal may be directly connected to the second amplifier output terminal, or it may be indirectly connected to the second amplifier output terminal through an intermediate circuit.

[0042] Return to reference Figure 3 The second operational amplifier 303-1 is configured to output an output voltage V proportional to the analog voltage. OUT 1. The non-inverting input is connected to the second node, and the inverting input is indirectly connected to the output of the second amplifier via a voltage divider resistor. Figure 3 In the example, the voltage divider resistor is an adjustable resistor, and the adjustable output voltage is achieved by adjusting the resistance value of the adjustable resistor.

[0043] According to some embodiments, each digital-to-analog converter module further includes a second control terminal configured to provide a second control signal to cause the digital-to-analog converter to apply a digital signal at the input port to a switched resistor network in response to the second control signal being valid. The digital-to-analog converter circuit also includes a timing controller configured to supply a digital signal to the input port, generate a first control signal and supply the first control signal to a first control terminal, and generate a second control signal and supply the second control signal to a second control terminal.

[0044] exist Figure 3In the example, the second control terminal provides a second control signal L_DAC_1 to the digital-to-analog converter 302-1. In one example, the second control signal L_DAC_1 is active on the rising edge, and the digital-to-analog converter 302-1 applies the digital signal CODE1 at the input port to the switched resistor network in the digital-to-analog converter 302-1 in response to the active second control signal L_DAC_1. The digital-to-analog converter circuit 300 may also include a timing controller 306 for providing input signals including a digital signal, a first control signal, and a second control signal to each digital-to-analog converter module. For example, the timing controller 306 may supply the digital signal CODE1 to the input port of the digital-to-analog converter module 307-1, generate a first control signal L_DACN_1 and supply the first control signal L_DACN_1 to a first control terminal, and generate a second control signal L_DAC_1 and supply the second control signal L_DAC_1 to a second control terminal. It will be understood that examples of timing controller 306 include, but are not limited to, general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs) or other programmable logic devices, discrete gate or transistor logic, discrete hardware components, or any combination thereof. It will also be understood that, in some embodiments, separate gating circuits 304-1 to 304-N are not required and may be integrated into timing controller 306.

[0045] According to some embodiments, the gating circuit includes a delay circuit configured to generate a leading edge of a gating signal in response to the leading edge of a first control signal, the trailing edge of which is delayed by a predetermined time interval relative to the leading edge of the first control signal. The predetermined time interval of the delay can be set according to actual needs. Generally, the predetermined time interval of the delay needs to be longer than the establishment time of the updated output voltage on the channel with digital signal updates, in order to avoid disturbances to the first reference voltage caused by the updates of the digital signals on that channel. After the updated output voltage is established, the first controllable switch is turned on again to ensure the stability of the output voltage of the channel without signal updates.

[0046] According to some embodiments, the delay circuit includes: a current source connected between a power supply voltage terminal and a third node; a third capacitor connected between the third node and a ground terminal; and a second controllable switch connected between the third node and the ground terminal, configured to turn on in response to the leading edge of a first control signal and turn off in response to the trailing edge of the first control signal. According to some embodiments, the delay circuit further includes a first branch and a second branch outputting two gating signals, the first branch and / or the second branch further including at least one inverter configured to generate gating signals based on the voltage at the third node. The two gating signals are used to control a complementary field-effect transistor (e.g., Figure 4A The on / off state of M0 in the equation.

[0047] Figure 5 This is an exemplary circuit diagram illustrating a gating circuit 500 according to an exemplary embodiment of the present disclosure. Figure 5 As shown, the gating circuit 500 includes: a current source Is connected between the power supply voltage terminal and the third node n3; a third capacitor C3 connected between the third node n3 and the ground terminal; a second controllable switch M3 connected between the third node n3 and the ground terminal, configured to be turned on in response to the leading edge of the first control signal L_DACN and turned off in response to the trailing edge of the first control signal; and a first branch and a second branch that output two gating signals CHP and CHN. The first branch includes an inverter I1, and the second branch includes inverters I1 and I2 connected in series, thereby outputting gating signals CHP and CHN that are inverted.

[0048] The first control signal L_DACN is high by default, the second controllable switch M3 is off, and the voltage at the third node n3 is charged to a high level by the third capacitor C3. At this time, the gating signal CHP is high and the gating signal CHN is low. When the falling edge of the first control signal L_DACN arrives, the second controllable switch M3 turns on, and the voltage at the third node n3 is pulled down to 0. At this time, the gating signal CHP has a falling edge, and the gating signal CHN has a rising edge. When the rising edge of the first control signal L_DACN arrives, the second controllable switch M3 turns off, and the voltage at the third node n3 is recharged to a high level by the third capacitor C3 after a predetermined time. At this time, the gating signal CHP has a rising edge, and the gating signal CHN has a falling edge. Thus, the gating circuit 500 operates as a delay circuit, realizing the delay function.

[0049] What will be understood is... Figure 5 The gating circuit 500 shown is illustrative and not limiting. In other embodiments, the gating circuit may take other forms. For example, the first branch or the second branch may include more inverters in series.

[0050] According to another aspect of this disclosure, a method 600 for controlling a digital-to-analog converter circuit is also provided. Here, the digital-to-analog converter circuit can be any of the digital-to-analog converter circuit embodiments described above. For example... Figure 6 As shown, method 600 includes steps S601 to S603. For descriptive purposes, the following description is in conjunction with... Figure 7 The example timing diagram is used to illustrate method 600.

[0051] Step S601: At the first time t0, in each of the NM digital-to-analog converter modules out of the N modules, the isolation circuit disconnects the first node from the second node, where M is an integer greater than or equal to 1 and less than N. Figure 7 In the example, M = N - 1. More specifically, only the digital converter of channel 1 needs to update the digital signal, and the digital converters of channels 2 to N need to be isolated. In this case, in channels 2 to N, the falling edge of the first control signal L_DACN_2 to L_DACN_2 triggers the invalid level of the strobe signals CHP and CHN of each channel, thereby disconnecting the first node from the second node.

[0052] Step S602: At a second time t1 after the first time t0, the updated digital signal at the input port of each of the M digital-to-analog converters (excluding the NM digital-to-analog converters) is applied to the switched resistor network. Figure 7 In the example, the second control signal L_DAC_1 of channel 1 has a rising edge at time t1 and triggers the digital signal update of that channel. At this time, since the first node and the second node are disconnected in channels 2 to N, the output voltage of these channels will not be affected by the digital signal update of channel 1.

[0053] Step S603: At the third time t3 after the second time t1, in each of the NM digital-to-analog conversion modules, the isolation circuit connects the first node to the second node. Figure 7 In the example, at the third time t3, the strobe signals CHP and CHN become active, causing the first node and the second node to resume conduction in channels 2 to N.

[0054] According to some embodiments, for each of the M digital-to-analog converter modules, the third time t3 is later than the time when the digital-to-analog converter module begins to output a stable output voltage at its output terminal in response to the updated digital signal. Figure 7 In the example, at time t2, the output V of the first channel... OUT 1. A stable output voltage is output from the start. Since the third time t3 is later than the time t2, it can avoid the disturbance of the first reference voltage and the crosstalk between channels caused by the update of digital signals in the M digital-to-analog conversion modules.

[0055] According to some embodiments, method 600 further includes: at a first time t0, ensuring that in each of the M digital-to-analog conversion modules, an isolation circuit maintains the first node connected to the second node. Figure 7 In the example, at the first time t0, the second control signal L_DAC_1 of the first channel is invalidated, causing the first node and the second node in the first channel to remain on. This allows each of the M digital-to-analog converter modules to update the digital signal.

[0056] According to some embodiments, method 600 further includes: at a second time t1, ensuring that in each of the NM digital-to-analog conversion modules, an isolation circuit keeps the first node disconnected from the second node. Figure 7 In the example, at the second time t1, the strobe signals CHP and CHN of channels 2 to N are invalid, thereby ensuring that the output voltage of these channels is not affected by the digital signal update of channel 1.

[0057] What will be understood is that when digital signals are updated simultaneously on all channels in a digital-to-analog converter circuit, the isolation circuit corresponding to each channel can connect the first node and the second node, thereby realizing multi-channel data updates.

[0058] Although this disclosure has been described and illustrated in detail in the accompanying drawings and the foregoing description, such description and illustration should be considered illustrative and suggestive, not restrictive; this disclosure is not limited to the disclosed embodiments. By studying the drawings, the disclosure, and the appended claims, those skilled in the art will be able to understand and implement variations of the disclosed embodiments in practice with respect to the claimed subject matter. In the claims, the word "comprising" does not exclude other elements or steps not listed, the indefinite article "a" or "an" does not exclude a plurality, the term "a plurality" means two or more, and the term "based on" should be interpreted as "at least partially based on". The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be beneficial.

Claims

1. A digital-to-analog conversion circuit, comprising: N digital-to-analog conversion modules, N being an integer greater than 1, each digital-to-analog conversion module comprising: an input port configured to provide a digital signal; a first control terminal configured to provide a first control signal; an output terminal; a digital-to-analog converter comprising a switched resistor network, an input of the switched resistor network being connected to the input port, and the switched resistor network being configured to generate an analog voltage corresponding to the digital signal at a first node based on at least a first reference voltage; an isolation circuit connected to the first control terminal and between the first node and a second node, configured to selectively turn on or off the first node and the second node according to the first control signal at the first control terminal, wherein the second node is coupled to the output terminal, wherein the isolation circuit is further configured to turn off the first node and the second node in response to the digital-to-analog conversion module determining no digital signal update.

2. The digital-to-analog conversion circuit of claim 1, wherein, the isolation circuit comprises: a gating circuit configured to generate a gate signal according to the first control signal; and a sample-and-hold circuit configured to turn on the first node and the second node in response to the gate signal being active, and turn off the first node and the second node and hold the analog voltage in response to the gate signal being inactive.

3. The digital-to-analog conversion circuit of claim 2, wherein, the sample-and-hold circuit comprises: a first controllable switch connected between the first node and the second node, configured to turn on in response to the gate signal being active, and turn off in response to the gate signal being inactive; and a first capacitor connected between the second node and a ground terminal.

4. The digital-to-analog conversion circuit of claim 3, wherein, the sample-and-hold circuit further comprises a second capacitor connected between the first node and a ground terminal.

5. The digital-to-analog conversion circuit of claim 3, wherein, the first controllable switch comprises any one of an N-type field effect transistor, a P-type field effect transistor, and a complementary field effect transistor.

6. The digital-to-analog conversion circuit of claim 2, wherein, the gating circuit comprises a delay circuit configured to generate a leading edge of the gate signal in response to a leading edge of the first control signal, a trailing edge of the gate signal being delayed from the leading edge of the first control signal by a predetermined time interval.

7. The digital-to-analog conversion circuit of claim 6, wherein, the delay circuit comprises: a current source connected between a power supply voltage terminal and a third node; a third capacitor connected between the third node and a ground terminal; a second controllable switch connected between the third node and a ground terminal, configured to turn on in response to the leading edge of the first control signal, and turn off in response to a trailing edge of the first control signal.

8. The digital-to-analog conversion circuit of claim 7, wherein, the delay circuit further comprises a first branch and a second branch of two gate signals, the first branch and / or the second branch further comprising at least one inverter configured to generate the gate signal based on a voltage at the third node, wherein the two gate signals are used to control the on-off of a complementary field effect transistor.

9. The digital-to-analog conversion circuit of any one of claims 1 to 8, wherein, the switched resistor network comprises any one of an R-2R ladder resistor network, an inverted R-2R ladder resistor network, and a weighted resistor network.

10. The digital-to-analog conversion circuit of any one of claims 1 to 8, further comprising a first operational amplifier, the first operational amplifier comprising: a first amplifier output configured to output the first reference voltage; a non-inverting input configured to receive a reference voltage or a voltage division of the reference voltage; and an inverting input connected to the first amplifier output.

11. The digital-to-analog conversion circuit of any one of claims 1 to 8, further comprising a second operational amplifier, the second operational amplifier comprising: a second amplifier output configured to output an output voltage proportional to the analog voltage; a non-inverting input connected to the second node; and an inverting input connected to the second amplifier output.

12. The digital-to-analog conversion circuit of any one of claims 1 to 8, each digital-to-analog conversion module further comprises a second control terminal configured to provide a second control signal to cause the digital-to-analog converter to apply a digital signal at the input port to the switched resistor network in response to the second control signal being active, and wherein the digital-to-analog conversion circuit further comprises a timing controller configured to supply the digital signal to the input port, generate and supply the first control signal to the first control terminal, and generate and supply the second control signal to the second control terminal. wherein 13. A method of controlling the digital-to-analog conversion circuit of any one of claims 1 to 12, the method comprising: at a first time, causing, in each of N-M digital-to-analog conversion modules of the N digital-to-analog conversion modules, the isolation circuit to disconnect the first node from the second node, M being an integer greater than or equal to 1 and less than N; at a second time after the first time, causing, in each of M digital-to-analog conversion modules of the N digital-to-analog conversion modules other than the N-M digital-to-analog conversion modules, an updated digital signal at the input port to be applied to the switched resistor network; and at a third time after the second time, causing, in each of the N-M digital-to-analog conversion modules, the isolation circuit to connect the first node to the second node. For each of the M digital-to-analog conversion modules, the third time is later than a time at which the digital-to-analog conversion module starts to output a stable output voltage at the output in response to the updated digital signal.

15. The method of claim 13, further comprising:

14. The method of claim 13, wherein, at the first time, causing, in each of the M digital-to-analog conversion modules, the isolation circuit to maintain the first node connected to the second node.

16. The method of claim 13, further comprising: at the second time, causing, in each of the N-M digital-to-analog conversion modules, the isolation circuit to maintain the first node disconnected from the second node. ​ ​

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