A data compression circuit and data compression method for particle images

Abstract

The invention discloses a data compression circuit for particle images, comprising: a readout channel, used for reading the address data of any group of hitting particles in a pixel array and then sending it, a compression readout circuit, connected to the readout channel, used for receiving the particle address data sent by the readout channel, compressing the particle address data, generating a first address and a compression code, and a lower-level data processing module, connected to the compression readout circuit, used for reading the first address and compression code of the group of hitting particles generated by the compression readout circuit. The method solves the data compression problem of two-dimensional particle image clusters.

Description

Technical Field

[0001] The present invention relates to the field of radiation detection technology, and more specifically to a data compression circuit and a data compression method for particle images. Background Art

[0002] In the field of radiation detection, we analyze physical quantities or physical phenomena by detecting the position, time, energy and other information of radiation particles. The detector receives the radiation signal and generates a charge, and the corresponding readout circuit or chip reads out the position, time, energy and other information of the charge generation. Pixel sensors can directly perform two-dimensional position resolution, and the pixel area is small, and the detector capacitance and leakage current are relatively small, so that good spatial resolution and high signal-to-noise ratio can be achieved. They are widely used in vertex detectors of high-energy physics experiments, X-ray imaging, medical imaging, material analysis and other aspects. In these applications, the sensor needs to cover a large area because the particles cannot be focused. The pixel size of the pixel detector varies from tens of microns to hundreds of microns depending on the application, and the pixel scale that needs to be read out by a single readout circuit chip often reaches hundreds of thousands to millions. To read out such a large amount of data, the chip needs to have an extremely high interface speed. The design of a high-speed data interface is complex and difficult, and the entire detection system will contain multiple detector modules, which will impose a huge burden on the entire detection system, making the detection system difficult to implement. Data compression is a commonly used method to reduce the amount of data. Generally speaking, particle imaging itself has the characteristics of sparseness and clustering, and we can compress the data based on these characteristics. The document "Himmi A, Doziere G, Torheim O, Hu Christine, Winter M, A Zero Suppression Micro-Circuit for Binary Readout CMOS Monolithic Sensors, Proceedings of the Topical Workshop on Electronics for Particle Physics, 2009" provides a data compression method. The method only reads out the address of the particle hitting position for the pixel array read out by row, and compresses the pixels hit continuously in a row into one data packet. Refer to the attached Figure 1 , the hit position in the image of the particle hitting the pixel array has the characteristics of a cluster. The prior art reads the address by row, defines a data structure to record the row address of the read row and the number of clusters in the row, and further defines a data structure to record the cluster situation. Assuming that the number of pixels corresponding to a cluster on a row does not exceed 4, refer to the attached Figure 2 Four possible hit pixel patterns and corresponding compression codes can be obtained. The data of a single cluster is shown in the attached figure. Figure 3As shown, it includes compression coding, the column address of the first pixel hit by the cluster, and other reserved information about the cluster. In the background technology, only the address is read out, and other information is empty.

[0003] The main disadvantages of existing data compression methods are: they only support row-based readout compression, while many chips are read out in double columns, and their versatility is poor; they can only perform one-dimensional image data compression, while clusters in particle images are usually two-dimensional. Summary of the invention

[0004] An embodiment of the present invention provides a particle image data compression circuit, comprising:

[0005] Readout channel;

[0006] Compression readout circuit, connected to the readout channel

[0007] The lower-level data processing module is connected to the compression readout circuit.

[0008] Further, the compression readout circuit comprises:

[0009] A first-level register connected to the readout channel;

[0010] The second level register is connected to the first level register;

[0011] A subtractor connected to the first-stage register and the second-stage register;

[0012] a controller connected to the first-stage register, the second-stage register and the subtractor;

[0013] The lower level data processing module is connected to the controller and the second level register.

[0014] Furthermore, the controller prepares a signal according to the data sent by the readout channel, sends a particle address readout enable and an enable of the first-level register to the readout channel, sends an enable to the second-level register according to the difference, sends an enable to the subtractor, sends a data valid signal to the lower-level data processing module, and performs compression encoding.

[0015] Preferably, the controller prepares a signal according to the data sent by the readout channel, sends a particle address readout enable and an enable of the first-level register to the readout channel, sends an enable to the second-level register according to the difference, sends an enable to the subtractor, sends a data valid signal to the lower-level data processing module, and performs compression encoding.

[0016] The present invention also provides a data compression method based on a particle image data compression circuit, comprising:

[0017] Define the address proximity range N for data compression;

[0018] receiving the first particle hitting address coding data as the first address coding data and storing it;

[0019] Continuously receiving new particle hitting address encoding data as new address encoding data;

[0020] Calculate the difference between the first address encoding data and the new address encoding data to obtain the distance value;

[0021] Determine the distance value to be between 1 and N;

[0022] Output the new compression encoding.

[0023] Preferably, if the distance value is greater than N, the first address and the current compression code are output.

[0024] Preferably, the generation of the compression code includes:

[0025] Set the compression code to N-1 bits, the highest bit to N-1 bits, the lowest bit to 0, and the initial value to all 0;

[0026] If the distance value m is less than N, the Nmth bit of the compression code is changed to 1, and the other bits remain unchanged;

[0027] It is determined that the distance value m is greater than or equal to N, the compression ends, and the compressed code is restored to the initial value of all 0.

[0028] The embodiment of the present invention provides a data compression circuit and a data compression method for a particle image. Compared with the prior art, the advantageous effects thereof are as follows:

[0029] 1. Data compression is performed according to the output order of pixel addresses in the channel, without being restricted by the row and column readout method;

[0030] 2. Data compression is achieved through only two levels of registers, which is simple and reliable;

[0031] 3. No additional memory is required for buffering before data analysis and compression, which enables real-time processing of information and saves resources. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 It is a schematic diagram of the image produced by particles hitting pixels;

[0033] Figure 2 It is the encoding method of data compression in the background technology;

[0034] Figure 3 It is the data format of data compression in the background technology;

[0035] Figure 4 The present invention is used for data compression encoding when reading out in parallel by row in the background technology;

[0036] Figure 5 is the data compression encoding method of the present invention for dual-column S-type address encoding output;

[0037] Figure 6 is the circuit implementation block diagram of the present invention;

[0038] Figure 7 is the timing diagram of data compression of the present invention. Specific embodiments

[0039] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0040] See Figures 1 to 7 , the embodiments of the present invention provide a data compression circuit and a data compression method for particle images, including:

[0041] The data compression method for particle images disclosed by the present invention can be used in the data readout process of a pixel sensor array. In the field of radiation detection, the pixel sensor array is large in scale and the hit pixels are sparse. Usually, only the addresses of the pixels hit by particles can be recorded. A pixel array is divided into multiple readout channels, and the data of each channel is read out and compressed. In a readout channel, the addresses of the hit pixels are encoded and the addresses of the hit pixels are output in a certain order, and the addresses of the unhit pixels are not output. The present invention compresses the consecutive or adjacent addresses output, and the compressed data consists of the start address of the hit pixels in this group and the compression encoding. The main process of data compression is as follows: (1) Define the address adjacent range for data compression as N; (2) Receive data as the start address and store it; (3) Continue to receive a new address, compare the new address with the start address, and judge the distance between the new address and the start address; (4) If the distance is from 1 to N, it means that the new address can be compressed, generate the compression encoding, and then go to (3); if the distance exceeds N, it means that the new address and the start address cannot be compressed, output the start address and the current compression encoding, and then go to (2) until the data reception is completed. The compression encoding is generated in the following way: The compression encoding has N-1 bits, which are recorded as the (N-2)th to the 0th bit from high to low, and the initial value is all 0; The difference between the newly received address and the start address is used to judge the distance, and let the difference be m; If m < N, change the (N-m)th bit of the compression encoding to 1, and the other bits remain unchanged; If m ≥ N, the data compression ends, and the compression code resumes the initial value of all 0.

[0042] The compression readout circuit of the present invention receives a data ready signal and a readout address from a readout channel, sends a readout enable to the readout channel, and sends a compression code, a first address, and a data valid signal to a lower-level data processing module. After the readout channel detects a particle, it sends a data ready signal, the compression readout circuit sends a readout enable, and the readout channel sends a readout address until all the data in the readout channel is read out and the data ready signal is invalid. The compression readout circuit reads the address in the channel to perform data compression to generate a first address and a compression code, and sends a data valid signal to the lower-level data processing module. The lower-level data processing module reads the first address and the compression code according to the data valid signal. The compression readout circuit includes a two-level register, a subtractor, and a controller. The first-level register stores the currently received address data, and the second-level register stores the first address. The currently received address and the first address are sent to the subtractor for difference, and the subtractor ensures that the difference is a positive number according to the ascending and descending configuration information of the address data, and the difference is sent to the controller. The controller sends a readout enable and an enable of the first-stage register according to a data ready signal, and sends an enable of the second-stage register, a subtraction enable, a data valid signal and a compression code with reference to a difference value.

[0043] Example:

[0044] Refer to the attached Figure 4 , the technology of the present invention is applied to the situation of parallel readout by row in the background technology. The column address of the first hit pixel is recorded, and the next three pixels are represented by compression code, 0 represents no hit, and 1 represents hit. The initial compression code is 000, and the address received after the first address is subtracted from the first address to modify the compression code. If the difference is 1, it means that the first pixel after the first address is hit, the highest bit (second bit) of the compression code is modified to 1, and the remaining bits remain unchanged; if the difference is equal to 2, it means that the second pixel after the first address is hit, the first bit of the compression code is modified to 1, and the remaining bits remain unchanged; if the difference is equal to 3, it means that the third pixel after the first address is hit, the 0th bit of the compression code is modified to 1, and the remaining bits remain unchanged; if the difference is greater than 3, it means that it is not within the compressible range of this group, and the current compression code is output. According to this method, 8 hit situations and corresponding codes can be obtained. The first four situations correspond to the background technology, and the last four will generate new data packets according to the continuity of the graphics in the background technology.

[0045] More generally, the present invention can be used for compression coding of two-dimensional images. Figure 5, the pixel address is encoded in double-column S-type, and the four adjacent addresses are still compressed and encoded. There are four possible first address positions according to the S-type encoding order. In each first address case, the following three pixels have 8 possible hit images, and 8 codes correspond to these 8 cases. The encoding method is still to subtract the newly received address from the first address. If the difference is greater than 3, the encoding ends; when the difference is 3, 2, and 1, the 0th, 1st, and 2nd bits of the compression code are modified to 1. The pixel position hit by the particle can be restored based on the first address and the compression code.

[0046] Refer to the attached Figure 6-7 , a circuit implementation block diagram and timing diagram of the data compression method in the present invention are given. After the readout channel detects a particle, it sends a data ready signal. The controller in the compression readout circuit sends a readout enable to read the address of the pixel, and sends an address cache enable 1 according to the readout time, and stores the address in the first-level register; when there are still particles hitting at this time, the controller continues to send readout enable, cache enable 1 and cache enable 2, the next address will be read out, the first address is stored in the second-level register, and the current address is stored in the first-level register; the outputs of the two-level register are connected to the subtractor as the subtrahend and minuend of the subtractor, and the subtractor determines which of the two inputs is the subtrahend and the minuend according to whether the address code is in ascending or descending order, so as to ensure that the result of the subtraction is positive; the controller sends a subtraction enable signal to control the timing of the subtraction operation; the controller generates a compression code, a data valid signal and a cache enable 2 according to the comparison result. Assuming that addresses 8, 95, 96, 97 and 259 are hit in the current channel, and the compression is adjacent to 4 addresses, the implementation process is described in detail below. After the readout channel detects a particle, it sends a data ready signal. The controller in the compressed readout circuit sends a readout enable to read the address of the pixel and sends a cache enable 1 according to the readout time, and stores the address 8 in the first-level register. At this time, if there are still particles hitting, the controller continues to send a readout enable, the next address 95 will be read out, the first address 8 will be stored in the second-level register, and the current address 95 will be stored in the first-level register. The result of the subtraction of the subtractor is 87, which is greater than 3, and the cache enable 2 is valid. The first address is updated in the next cycle; the output data is valid, and the next-level processing unit can obtain the address 8 and the compression code '000' according to the signal. Continue to read out the new address 96, then 95 will be stored in the second-level register as the first address, the subtraction result is 1, indicating that it can be compressed, the compression code is '100', cache enable 2 is invalid, and the first address is still 95; continue to read out the new address 97, the subtraction result is 2, the compression code is changed to '110'; continue to read out the new address 259, the subtraction result is 164, which is greater than 3, cache enable 2 is valid, and the first address is updated in the next cycle; the output data is valid, and the next-level processing unit can obtain the address 95 and the compression code '110'. At this time, there is no data in the read channel, and the data valid signal is directly output, and the next-level processing unit can obtain the address 259 and the compression code '000'.

[0047] This method can effectively compress data when particles hit multiple pixels in the same channel. Assuming that the address of each pixel is 20 bits, without data compression, the data obtained when the particle hits 2, 3, and 4 pixels are 40, 60, and 80 bits respectively; after data compression, the data volume is 3 bits of compression code and 20 bits of first address, a total of 23 bits; the compression multiples are 1.74, 2.6, and 3.48 respectively.

[0048] Disclosed above are only a few specific embodiments of the present invention. Those skilled in the art may make various changes and modifications to the embodiments of the present invention without departing from the spirit and scope of the present invention. However, the embodiments of the present invention are not limited thereto. Any changes that can be conceived by those skilled in the art should fall within the scope of protection of the present invention.

Claims

1. A data compression method, characterized in that: include: Reading the address data of any group of hitting particles in the particle image pixel array; Receiving the particle address data sent by the read channel, compressing the particle address data, and generating a first address and a compression code, which includes: Define the address proximity range N for data compression; receiving the first particle hitting address coding data as the first address coding data and storing it; Continuously receiving new particle hitting address encoding data as new address encoding data; Calculate the difference between the first address encoding data and the new address encoding data to obtain the distance value; Determine the distance value to be between 1 and N; Output new compression code; Read the first address and compression code of the group of hitting particles generated by the compression readout circuit; If the distance value is greater than N, the first address and the current compression code are output; The generation of the compression code comprises: Set the compression code to N-1 bits, the highest bit to N-1 bits, the lowest bit to 0, and the initial value to all 0; If the distance value m is less than N, the Nmth bit of the compression code is changed to 1, and the other bits remain unchanged; It is determined that the distance value m is greater than or equal to N, the compression ends, and the compression code restores the initial value to all 0.

2. A particle image data compression circuit applied to the data compression method according to claim 1, characterized in that: include: A readout channel is used to read the address data of any group of hitting particles in the particle image pixel array; A compression readout circuit is connected to the readout channel and is used to receive the particle address data sent by the readout channel, perform data compression on the particle address data, and generate a first address and a compression code; The lower-level data processing module is connected to the compression readout circuit and is used to read the first address and compression code of the hitting particles in this group generated by the compression readout circuit.

3. A particle image data compression circuit as claimed in claim 2, characterized in that: The compression readout circuit comprises: A first-level register connected to the readout channel; The second level register is connected to the first level register; A subtractor connected to the first-stage register and the second-stage register; a controller connected to the first-stage register, the second-stage register and the subtractor; The lower level data processing module is connected to the controller and the second level register.

4. A particle image data compression circuit as claimed in claim 3, characterized in that: The controller prepares a signal according to the data sent by the readout channel, sends a particle address readout enable and an enable of the first-level register to the readout channel, sends an enable to the second-level register according to the difference, sends an enable to the subtractor, sends a data valid signal and compression coding to the lower-level data processing module.

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