A processing method, apparatus and electronic device

Abstract

The application provides a processing method, device and electronic equipment. When an operating system of the electronic equipment runs an application, a core calling instruction capable of representing a required number of processor cores of the application running can be sent to a processor. The processor responds to the obtained core calling instruction, flexibly adjusts a core working mode of the processor according to the number of processor cores, so that a task thread created by the application running is executed according to the adjusted core working mode, all cores of the processor can be fully utilized to participate in calculation, the use requirement of the application with different required numbers of processor cores is met, the waste of processing resources is avoided, and the application running speed is greatly improved.

Description

TECHNICAL FIELD

[0001] The present application mainly relates to the field of computer application, and more particularly to a processing method and device and electronic equipment. BACKGROUND

[0002] At present, in order to improve the processing capability of electronic equipment, a multi-core processor CPU is usually used, each physical core can be simulated into two logical cores, and the use demand of logical cores (also called cores or processors) of different applications running can be met through multiple task threads.

[0003] In actual application, after the operating system determines the number of cores required by the application running, the processor can be triggered to call the corresponding number of logical cores to be allocated to the application, and track multiple task threads of the application. In this way, in the case that the number of cores required by the application running is small, the unallocated logical cores will be idle, causing waste of CPU processing resources. SUMMARY

[0004] Therefore, the present application provides a processing method, which comprises:

[0005] obtaining a core calling instruction for the operating system running an application; the core calling instruction can represent the number of processor cores required by the application running;

[0006] adjusting the core working mode of the processor in response to the core calling instruction; wherein the number of cores supported by the processor for the application running is different in different core working modes;

[0007] executing the task threads created by the application running according to the adjusted core working mode.

[0008] Optionally, the adjusting the core working mode of the processor in response to the core calling instruction comprises:

[0009] determining the core working mode corresponding to the number of processor cores required by the application running in response to the core calling instruction;

[0010] processing the physical cores of the processor into at least one logical core according to the determined core working mode;

[0011] the executing the task threads created by the application running according to the adjusted core working mode comprises:

[0012] executing the task threads created by the application running by the obtained logical core.

[0013] Optionally, the adjusting the core working mode of the processor in response to the core calling instruction comprises:

[0014] obtaining a task type of the application in response to the core calling instruction; the task type is determined by the operating system;

[0015] adjusting the processor to enter a core working mode corresponding to the task type according to a preset corresponding relationship;

[0016] The preset corresponding relationship represents a corresponding relationship between different task type applications and different core working modes of the processor.

[0017] Optionally, the core working mode of the processor includes a hyper-threading working mode and a reverse hyper-threading working mode, and the adjusting the processor to enter the core working mode corresponding to the task type according to the preset corresponding relationship includes:

[0018] determining a required processor core quantity for running the application of the task type;

[0019] if the required processor core quantity is less than a core threshold value, adjusting the processor to enter the reverse hyper-threading working mode, and processing a plurality of physical cores of the processor into a logical core quantity of the required processor core quantity; the core threshold value is determined based on the physical core quantity of the processor and the logical core quantity that can be processed by each physical core;

[0020] if the required processor core quantity is greater than or equal to the core threshold value, adjusting the processor to enter the hyper-threading working mode, and processing one physical core of the processor into a plurality of logical cores, so that the logical core quantity of the processor is greater than or equal to the required processor core quantity.

[0021] Optionally, the core working mode of the processor includes a hyper-threading working mode and a reverse hyper-threading working mode, and the adjusting the processor to enter the core working mode corresponding to the task type according to the preset corresponding relationship includes:

[0022] if the task type is a single-thread task, adjusting the processor to enter the reverse hyper-threading working mode, and processing a plurality of physical cores of the processor into one logical core;

[0023] if the task type is a multi-thread task, adjusting the processor to enter the hyper-threading working mode, and processing one physical core of the processor into a plurality of logical cores.

[0024] Optionally, the processing the physical core of the processor into one or more logical cores includes:

[0025] The physical cores of the processor are virtualized to obtain one or more logical cores, the same number of processor cores required for the operating system to run applications; or,

[0026] All the physical cores of the processor are packaged into a single logical core and then mounted on a bus, so that the operating system can be aware of this single logical core; or,

[0027] All physical cores of the processor are grouped and packaged, and the resulting multiple logical cores are mounted on the bus so that the operating system can be aware of the multiple logical cores.

[0028] Optionally, the method further includes:

[0029] The system receives an application status notification from the operating system, determines that the single-threaded application has ended running, and adjusts the processor to switch from the reverse hyper-threading working mode to the hyper-threading working mode, thus processing one physical core of the processor into multiple logical cores.

[0030] This application also proposes a processing apparatus, the apparatus comprising:

[0031] The core call instruction acquisition module is used to acquire core call instructions for applications running on the operating system; the core call instructions can represent the number of processor cores required for the application to run.

[0032] A core operating mode adjustment module is used to respond to the core call instruction and adjust the core operating mode of the processor; the number of cores supported by the processor for the application to run varies under different core operating modes.

[0033] The execution module is used to execute the task threads created by the application in accordance with the adjusted core working mode.

[0034] This application also proposes an electronic device, the electronic device comprising:

[0035] The memory is used to store programs that implement the processing methods described above;

[0036] A processor having at least one physical core for loading and executing the program stored in the memory to implement the processing method described above.

[0037] This application also proposes a computer storage medium storing a plurality of computer instructions, which are executed by a processor to implement the processing method described above.

[0038] Therefore, the application provides a processing method, device and electronic equipment, when an operating system of the electronic equipment runs an application, a core calling instruction representing a required number of processor cores of the application is sent to the processor, the processor responds to the obtained core calling instruction, and the core working mode of the processor is flexibly adjusted according to the number of processor cores, so that the task threads created by the application are executed according to the adjusted core working mode, all logical cores of the processor can be fully utilized, the use requirements of applications with different required numbers of processor cores are met, and the application running speed is improved without wasting processing resources. BRIEF DESCRIPTION OF DRAWINGS

[0039] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed to be used in the embodiments or the prior art description will be briefly introduced. Obviously, the drawings in the following description are only embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative effort on the basis of the provided drawings.

[0040] Figure 1 A processor structure schematic diagram of an electronic equipment;

[0041] Figure 2 A hardware structure schematic diagram of an optional example of an electronic equipment suitable for the processing method proposed in the present application;

[0042] Figure 3 A flowchart schematic diagram of an optional example of the processing method proposed in the present application;

[0043] Figure 4 A flowchart schematic diagram of another optional example of the processing method proposed in the present application;

[0044] Figure 5 A flowchart schematic diagram of another optional example of the processing method proposed in the present application;

[0045] Figure 6a An optional structure schematic diagram of the processor in the processing method proposed in the present application in a reverse hyperthreading working mode;

[0046] Figure 6b Another optional structure schematic diagram of the processor in the processing method proposed in the present application in a reverse hyperthreading working mode;

[0047] Figure 6c Another optional structure schematic diagram of the processor in the processing method proposed in the present application in a reverse hyperthreading working mode;

[0048] Figure 6dThis is a schematic diagram of an optional structure in the processing method proposed in this application, where the processor is in hyper-threaded working mode;

[0049] Figure 7 A flowchart illustrating yet another optional example of the processing method proposed in this application;

[0050] Figure 8 This is a schematic diagram of an optional example of the processing apparatus proposed in this application;

[0051] Figure 9 A schematic diagram of another alternative example of the processing apparatus proposed in this application;

[0052] Figure 10 A schematic diagram of another alternative example of the processing apparatus proposed in this application;

[0053] Figure 11 This is a schematic diagram of another alternative example of the processing apparatus proposed in this application. Detailed Implementation

[0054] Regarding the description in the background technology section, multi-core processors in electronic devices can employ Hyper-Threading (HT) technology, simulating each physical core as two logical cores. In this way, while one logical core is tracking and processing a task thread (such as performing floating-point operations), the other logical core can utilize the CPU's idle resources to track and process another task thread (such as performing integer operations like addition). This allows more work to be completed in each clock cycle, improving the CPU's resource utilization and the corresponding data and instruction throughput.

[0055] For example, such as Figure 1 The schematic diagram of the processor structure shown shows that the CPU of the electronic device has 4 physical cores. Using HT technology, each physical core can be simulated as two logical cores. In this way, if the operating system determines that application A needs N (8≥N≥1) logical cores to run, the processor can select N idle logical cores to allocate to the application and run N task threads. This processing method cannot avoid wasting CPU processing resources.

[0056] In order to improve the above problems, the present application hopes that all logical cores can be used to process the task threads of an application, such as processing M physical logical cores (such as 4 Physical Cores in the above example) of an electronic device into N logical cores, assigning N task threads of the application A to run, and avoiding core idling and causing waste of processing resources. Based on this, in actual application, the processor CPU can determine the number of processor cores required by the application (i.e. the number of logical cores required to be called) by calling instructions for the operating system to run the core of the application, and then process the physical cores of the processor according to the corresponding core working mode (such as HT working mode, reverse HT working mode), and execute the task threads created by the application by the obtained logical cores, to meet the use demand of different applications for more cores or fewer cores.

[0057] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative labor are within the scope of protection of the present application.

[0058] Referring to Figure 2 , the hardware structure diagram of an optional example of an electronic device suitable for the processing method proposed in the present application. The electronic device can be a server, such as a standalone physical server, a server cluster composed of multiple physical servers, or a cloud server capable of implementing cloud computing, etc. In some embodiments, the electronic device can also be a user terminal with certain data processing capability, such as a desktop computer, a robot, a tablet computer, a smart medical device, a smart transportation device, an augmented reality (AR) device, a virtual reality (VR) device, a vehicle-mounted device, a notebook computer, etc. The type of electronic device product can be determined according to the scene requirements.

[0059] As Figure 2 shown, the electronic device can include but is not limited to at least one memory 21 and at least one processor 22, wherein:

[0060] The memory 21 can be used to store the program for implementing the processing method described in the following method embodiment description; the processor 22 can load and execute the program stored by the memory to implement each step of the processing method described in the following corresponding method embodiment description. The specific implementation process can refer to the description of the corresponding part of the following embodiment, and this embodiment will not be described in detail here.

[0061] In actual application, the memory 21 and the processor 22 can be connected with a communication bus, through which data interaction between each other and between the electronic device and other structures (such as various I / O (Input / Output) devices connected with the communication bus, etc.) is realized, which can be determined according to actual needs, and the present application does not make detailed description.

[0062] In the embodiment of the present application, the memory 21 can include a high-speed random access memory, and can also include a non-volatile memory, for example, at least one magnetic disk storage device or other volatile solid-state storage device. The processor 22 can be a central processing unit (CPU), an application-specific integrated circuit (ASIC), a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a ready-to-program gate array (FPGA) or other programmable logic device, etc. The present application does not limit the structure and model of the above-mentioned memory 21 and processor 22, which can be flexibly adjusted according to actual needs.

[0063] It should be understood that, Figure 2 The structure of the electronic device shown does not constitute a limitation on the electronic device in the embodiment of the present application. In actual application, the electronic device can include more components than Figure 2 those shown, or some components can be combined. For example, the electronic device can further include at least one input component such as a touch sensing unit for sensing touch events on a touch display panel, a keyboard, a mouse, a camera, a sound pickup, etc.; at least one output component such as a display, a speaker, a vibration mechanism, a lamp, etc.; an antenna; a sensor module; a power supply module, etc. Figure 2 The listed input components and output components are not shown, and the hardware structure can be determined according to the type of terminal device and its functional requirements, which will not be enumerated one by one in the present application.

[0064] Referring to Figure 3 , the flowchart of an optional example of the processing method proposed in the present application, which can be executed by an electronic device, such as Figure 3 , the processing method can include:

[0065] Step S31, obtaining core calling instructions for running applications of the operating system;

[0066] In combination with the foregoing description of the technical solutions of the present application, the number of processor cores required for running an application is determined in the application development process. Thus, when the operating system of the electronic device starts running an application, the number of processor cores required for running the application can be obtained, and a core calling instruction for the application can be generated according to the number of processor cores required for running the application, and the core calling instruction is sent to the processor to request to meet the core calling requirement of the application. It can be seen that the core calling instruction can represent the number of processor cores required for running the application, but the content of the core calling instruction and the generation method thereof are not limited in the present application.

[0067] In step S32, the core working mode of the processor is adjusted in response to the core calling instruction.

[0068] In the embodiments of the present application, the number of cores supported by the processor for running an application is different in different core working modes. In combination with the foregoing description of the multi-core processor, the simulation processing of the plurality of physical cores of the processor can be different in different core working modes of the processor. For example, in the first core working mode, the processor can simulate each physical core as two or more logical cores to meet the running requirement of an application requiring more cores. In the second core working mode, the processor can simulate a plurality of physical cores as a smaller number of logical cores or even one logical core to meet the running requirement of an application requiring fewer cores, or even a single-threaded application, while fully utilizing the processing resources and improving the running speed.

[0069] It should be noted that the working principle of the processor supporting the first core working mode and the second core working mode as described above is not described in detail in the present application. Different core working modes can be configured in combination with the hyper-threading (HT) technology, and the implementation process is not described in detail in the embodiments of the present application.

[0070] According to the foregoing analysis, after the processor obtains the core calling instruction for running the application of the operating system, the number of cores required for running the application is determined by analyzing the core calling instruction, and the processor can be controlled to enter the corresponding core working mode, and the plurality of physical cores of the processor are simulated according to the processing mode corresponding to the core working mode. The implementation process is not described in detail in the embodiments of the present application.

[0071] In step S33, the task thread created for running the application is executed according to the adjusted core working mode.

[0072] Referring to the above description of the different core operating modes of the processor, if the processor is running in the first core operating mode (such as the hyper-threading operating mode), it can process one or more physical cores of the processor into a larger number of logical cores; if the processor is running in the second core operating mode (such as the reverse hyper-threading operating mode), it can simulate the processing of multiple physical cores of the processor into a smaller number of logical cores. This application does not describe in detail the processing methods for these two operating modes.

[0073] As can be seen, when the processor is in any core operating mode, all physical cores of the processor, or all logical cores contained within it, will participate in application execution, making full use of the processor's available processing resources. Compared to only one or a few logical cores participating in application execution, the processing method proposed in this application greatly improves the running speed. The implementation process of how the logical cores execute application task threads to meet application requirements will not be detailed in the embodiments of this application.

[0074] In summary, in the embodiments of this application, when the operating system of an electronic device is running an application, a core call instruction that represents the number of processor cores required for the application to run can be sent to the processor. The processor responds to the obtained core call instruction and flexibly adjusts the processor's core working mode according to the number of processor cores. In this way, the task threads created by the application are executed according to the adjusted core working mode, which can make full use of all the logical cores of the processor, meet the usage needs of applications with different numbers of processor cores, avoid waste of processing resources, and improve the application running speed.

[0075] Reference Figure 4 This is a flowchart illustrating another optional example of the processing method proposed in this application. This method can be an optional refined implementation of the processing method described in the above embodiments, but it is not limited to the refined implementation described in this embodiment. Furthermore, this refined implementation method can still be executed by an electronic device, such as... Figure 4 As shown, the method may include:

[0076] Step S41: Obtain the core call instructions for the operating system to run the application;

[0077] Based on the description of the corresponding part of the above embodiments, the core call instruction can represent the number of processor cores required for the application to run. The number of processor cores is usually determined during the application development process. The method for determining the processor core data and the process for obtaining the core call instruction will not be described in detail here.

[0078] Step S42: In response to the core call instruction, determine the core operating mode corresponding to the number of processor cores required for the application to run;

[0079] According to the above description of the core working mode of the processor, the processor has different processing manners for the physical cores, different numbers of logical cores that can be detected by the operating system, and different application types that can be run by the operating system. Therefore, the number of processor cores required by the application started by the electronic device is related to the core working mode that the processor needs to enter. The dynamic management of the processor cores can be achieved according to the correlation, and the running requirements of different applications can be met.

[0080] Therefore, after the processor determines the number of processor cores required by the application running of the operating system according to the obtained core calling instruction, the core working mode corresponding to the number of processor cores can be determined according to the above correlation. The representation and determination method of the correlation are not limited in the present application, and the core working mode of the processor includes but is not limited to the two core working modes described above. The number and working principle of the core working mode can be configured according to the actual situation, and the number of logical cores simulated by the processor in each core working mode is not described in detail in the present application.

[0081] For example, if the number of processor cores required by the application is small, such as less than the core threshold, the processor can be controlled to enter the reverse hyper-threading working mode to fully utilize all the logical cores of the processor. Conversely, if the number of processor cores required by the application is large, such as greater than or equal to the core threshold, the processor can be controlled to enter the hyper-threading working mode to improve the running speed of the application and complete more work in the same time.

[0082] Step S43: processing the physical cores of the processor into at least one logical core according to the determined core working mode;

[0083] Step S44: executing the task thread created by the application running by the obtained logical core.

[0084] After the core working mode of the processor is determined according to the above method, the processor can simulate the physical cores of the processor according to the working principle corresponding to the core working mode, and obtain a number of logical cores corresponding to the core working mode. The implementation process of how to simulate all the physical cores of the processor into at least one logical core is not described in detail in the present application.

[0085] For example, according to the above description of the core working mode of the processor, Figure 1The processor structure may need to simulate the 4 physical cores of the processor as 8 or more or less (which can be determined according to the number of cores required by the application running) logical cores according to the first core working mode, or simulate the 4 physical cores of the processor as 3 / 2 / 1 logical core according to the second core working mode, to execute a plurality of task threads created by the application running.

[0086] It can be seen that in the embodiment of the application, the processor can enter the corresponding core working mode according to the number of processor cores actually required by the operating system running the application, simulate all physical cores of the processor as a corresponding number of logical cores, execute one task thread created by the application by each logical core, meet the core use demand of different thread applications, improve the application running speed, fully utilize the processing resources, and avoid the waste of processing resources caused by the idle of part of the cores.

[0087] Reference Figure 5 The flowchart of another optional example of the processing method proposed in the application can be another optional refinement of the processing method described in the above embodiment, as shown in Figure 5 The method can include:

[0088] Step S51, obtaining a core calling instruction for the operating system running the application;

[0089] The core calling instruction can represent the number of processor cores required by the application running, which can be greater than or equal to 1 and less than or equal to the maximum number of logical cores that the processor can simulate, and the value thereof is not limited by the application and can be determined as appropriate.

[0090] Step S52, obtaining the task type of the application in response to the core calling instruction;

[0091] Step S53, determining the number of processor cores required by the application running of the task type;

[0092] In the embodiment of the application, the task type to which each application in the electronic device belongs can usually be determined by the operating system before task execution, for example, it can be determined in the application development stage or in the later upgrading process that the application belongs to what task type, such as N-thread application, N is a positive integer, and the application does not limit each task type of the application and its representation.

[0093] After any application of a known task type is started, the operating system can send core calling instructions containing the number of processor cores required by the application to the processor; or the processor can record the association between different task types of the application and the number of processor cores required by the application, so that, after the processor receives the core calling instructions for the application running on the operating system, the task type to which the application belongs can be determined according to the application identifier and other information of the application, and then the number of processor cores required by the application belonging to the task type is determined by using the association, and the method for obtaining the task type of the application and the number of processor cores required by the application is not limited in the present application.

[0094] In some embodiments of the present application, after the task type of the application is determined, the corresponding relationship between different task types of the application and different core working modes of the processor can be called, so that the processor is adjusted to enter the core working mode corresponding to the task type according to the preset corresponding relationship, and then the physical cores of the processor can be processed according to the processing process of each core working mode described below, to obtain at least the required number of logical cores, and the implementation process is not described in detail in the present embodiment.

[0095] Step S54: It is detected whether the number of processor cores is less than the core threshold value, if yes, step S55 is entered; if no, step S56 is executed.

[0096] Referring to the related description of the different core working modes of the processor above, in order to fully utilize the processing resources of the processor and avoid waste of processing resources caused by core idling, for different numbers of processor cores required by the application running on the operating system, the processor can enter different core working modes and be simulated according to the corresponding processing mode.

[0097] Therefore, in order to determine the core working mode for the application running on the operating system, the differences between different core working modes can be analyzed, and the core threshold value for distinguishing the logical cores corresponding to different core working modes can be determined in advance, so that the number of processor cores required by the application is compared with the core threshold value to determine which core working mode the processor should work in.

[0098] It should be noted that the core threshold value can be determined based on the number of physical cores possessed by the processor and the number of logical cores that can be processed from each physical core, and the value of the core threshold value is not limited in the present application and can be determined as appropriate.

[0099] Step S55: The processor is adjusted to enter the reverse hyper-threading working mode, and the multiple physical cores possessed by the processor are processed into the required number of logical cores of the processor;

[0100] In the case that the number of processor cores required by the application is less than the core threshold value, the application can be considered as a single-threaded application, a two-threaded application, a three-threaded application, and the like. If the processor still simulates one physical core as two or more logical cores, and the corresponding number of logical cores is allocated to the application, the other unallocated logical cores will be idle, resulting in waste of processing resources of the processor and affecting the running speed of the application and the throughput of data and instructions of the processor.

[0101] To improve the above problems, in the case that the number of processor cores required by the application is less than the core threshold value, the working principle of the hyper-threading technology is combined, that is, each physical core of the processor is simulated as two or more logical cores. Since the number of logical cores required to be displayed to the operating system is small at this time, the processor can be controlled to enter the reverse hyper-threading working mode, and the reverse processing mode of the working principle of the hyper-threading technology is adopted to simulate the multiple physical cores of the processor as a smaller number of logical cores. For example, the number of obtained logical cores is less than the number of physical cores possessed by the processor, but is consistent with the number of processor cores required by the application. In this way, all physical cores of the processor and all logical cores simulated therefrom will participate in the thread execution task of the application, greatly improving the running speed of the application and avoiding waste of processing resources.

[0102] For example, in the processor structure as shown in Figure 1 , after the operating system notifies the processor to enter the reverse hyper-threading working mode, if the application requires two cores, as shown in Figure 6a , two physical cores can be simulated as one logical core (such as the logical core represented by the dashed box in Figure 6a ); or, as described in Figure 6b , three of all physical cores can be simulated as one logical core, and the remaining one physical core can be simulated as one logical core, so that the operating system can perceive two logical cores to support the running of this type of application. Of course, according to the application requirements, such as a single-threaded application, as shown in Figure 6c , four physical cores can also be simulated as one logical core, which better meets the running system of the single-threaded application. It should be noted that the reverse hyper-threading processing method of the physical core of the processor includes but is not limited to the processing process described in the embodiment.

[0103] In step S56, the processor is adjusted to enter the hyper-threading working mode, and one physical core of the processor is processed as multiple logical cores, so that the number of logical cores of the processor is greater than or equal to the number of required processor cores.

[0104] According to the above detection mode, if the number of processor cores required by the application to run is greater than or equal to the core threshold, it indicates that the application running occupies a large number of cores, which is often greater than the number of physical cores of the processor. In order to meet the core usage requirements of such applications, the processor can be adjusted to enter the super-thread working mode, so that each physical core of the processor is simulated as a plurality of logical cores, so that the processor can provide enough logical cores to meet the core calling requirements of such applications.

[0105] In actual application, after the processor enters the super-thread working mode, the processor can simulate each physical core as a corresponding number of logical cores according to the number of processor cores required by the application to run. For example, as shown in the processor structure in Figure 1 , if the application running requires 8 cores, the processor can simulate each of the four physical cores as two logical cores to obtain 8 logical cores and allocate them to the application; if the application running requires 12 cores, the processor can simulate each of the four physical cores as three logical cores to obtain 12 logical cores required by the application, without causing waste of processing resources. Figure 6d

[0106] It should be noted that in the process of simulating each physical core of the processor, the number of logical cores simulated by each physical core does not necessarily need to be the same, and the number of logical cores obtained is a multiple of the number of physical cores. In some embodiments, different physical cores of the processor can be simulated as different numbers of logical cores, such as physical core 1 can be simulated as two logical cores, physical core 2 can be simulated as three logical cores, and physical core 3 can be simulated as four logical cores, etc. The number of logical cores can be determined according to the number of cores required by the application. The virtualization process of each physical core is not described in detail in the present application, and can be referred to but is not limited to the working principle of the super-thread technology.

[0107] Step S57: The logical cores obtained by the processing execute the task threads created by the application running.

[0108] ​In summary, in the embodiments of the present application, based on the demand of different applications for the number of running processor cores, the core working mode of the processor is dynamically managed. When an application calls the maximum number (or a larger number, i.e., at least more than the number of physical cores) of logical cores provided by the processor through the operating system, it indicates that the application mainly runs in the multi-core mode of the processor, and the core working mode of the processor can be switched to the hyper-threading working mode. When the application calls a smaller number of processor cores provided by the processor (such as only 1 or 2 CPUs) through the operating system, the processor can be controlled to switch to the reverse hyper-threading working mode, so that more physical cores or even all physical cores simultaneously complete the work completed by the smaller number of cores, maximize the utilization of CPU processor performance, and improve the running speed of the application.

[0109] With reference to Figure 7 The flowchart of another optional example of the processing method proposed in the present application can be another optional refinement of the processing method described in the above embodiments. As shown in Figure 7 The method can include:

[0110] In step S71, a core calling instruction for running an application by an operating system is obtained.

[0111] The core calling instruction can represent the number of processor cores required by the application to run.

[0112] In step S72, in response to the core calling instruction, the task type of the application is obtained.

[0113] For the implementation process of step S71 and step S72, refer to the description of the corresponding part in the above embodiments, which will not be described in detail in this embodiment.

[0114] In step S73, if the task type is a multi-threaded task, the processor is adjusted to enter the hyper-threading working mode, and one physical core of the processor is processed as a plurality of virtual logical cores.

[0115] In step S74, a plurality of task threads created by the multi-threaded application are executed by the plurality of virtual logical cores.

[0116] In practical application, a user starts an application (application program APP in the present application) of an electronic device, and an operating system can predict whether the application is a single-thread (ST) application or a multi-thread (MT) application, which is usually determined when the application is developed and designed. Then, the operating system can send a core calling instruction for the application to a processor according to the prediction result, or the operating system can send a core calling instruction for the task type of the application to the processor after determining that the application is a multi-thread application or a single-thread application, so that the processor knows the task type of the application run by the operating system, such as a multi-thread task or a single-thread task.

[0117] It should be noted that in the embodiments of the present application, the multi-thread task / application refers to an application that requires a large number of processor cores, such as an 8-thread application under the processor architecture shown in Figure 1 Therefore, when it is determined that the started application is a multi-thread application, the operating system generates a corresponding core calling instruction and sends it to the processor to notify the processor to switch to the hyper-thread working mode.

[0118] When the processor is in the hyper-thread working mode, referring to the processor structure diagram shown in Figure 6d the physical cores of the processor can be virtually processed to obtain a plurality of logical cores with the same number of processor cores required by the operating system to run the application, so that each task thread created by the application is assigned a logical core, the processing resources of the processor are fully utilized, and the core utilization rate and the throughput of the corresponding data and instructions of the processor are improved.

[0119] If the task type is a single-thread task, the processor is adjusted to enter the reverse hyper-thread working mode, and the plurality of physical cores of the processor are processed as one logical core in step S75.

[0120] In step S76, a single task thread created by the single-thread application is executed by the logical core.

[0121] As described above, for a single-thread test program such as Cinebench (a set of CPU and graphics card test systems), only one processor core needs to be called to run, so that when facing Figure 1In order to avoid waste of processing resources, the reverse hyperthreading function is configured to the processor CPU based on the hyperthreading function of the processor architecture. Under the cooperation of the operating system OS, it is determined that the running application belongs to a single-threaded application. The processor can be notified to enter the reverse hyperthreading working mode. Therefore, the reverse hyperthreading function of the processor is used to virtualize all physical cores of the processor. All physical cores are simulated as a logical core. That is, a logical core with the same number of processor cores required by the operating system to run the application is obtained. The implementation process can be combined with the working principle of the hyperthreading technology in reverse processing method. The embodiment will not be described in detail.

[0122] In some embodiments, the multi-core processor CPU of the electronic device can include a package multi-core and a native multi-core. The package multi-core refers to packaging multiple cores together to obtain a logical core mounted on the bus of the electronic device. Each core of the native multi-core is completely independent and is mounted on the bus of the electronic device to avoid conflict and reduce performance loss. Based on this, referring to the principle of the package multi-core, in order to process each physical core of the processor as a logical core, all physical cores of the processor can be packaged as a logical core and then mounted on the bus, so that the operating system can perceive one logical core for executing a single-threaded application.

[0123] Similarly, in the case where the number of processor cores required by the running application is small, such as 2 processor cores, the operating system can notify the processor to switch to the reverse hyperthreading working mode. The multiple physical cores of the processor can be grouped and packaged to obtain a plurality of (in this embodiment, 2 processor cores required by the application are taken as an example) logical cores. For example, 4 physical cores are divided into two groups (for example, as shown in Figure 6a Two physical cores are divided into a group; or as shown in Figure 6b One physical core is a group, and the other three physical cores are another group), one group of physical cores is packaged as a logical core, and the packaged logical core is mounted on the bus, so that the operating system can perceive two logical cores, which are allocated to the running 2-threaded application. All processing resources of the processor are fully utilized, the performance of the processor in processing the application is improved in a short time, and the CPU performance utilization rate can be maximized, thereby greatly improving the running speed of the application.

[0124] It should be understood that in other processor architectures of electronic devices, due to the different numbers of physical cores the processor has, virtualization can result in different logical cores, allowing the use of all processor cores to meet the core usage requirements of various threaded applications. The virtualization process of encapsulating multiple physical cores (which can be grouped evenly or unevenly based on their performance and available processing resources) into a single logical core can be referred to the description in the corresponding section above; the virtualization process of simulating one physical core as multiple logical cores can be referred to the description of hyper-threading technology above, and will not be repeated here.

[0125] As the above analysis shows, the processor architecture of electronic devices not only supports simulating one physical core as two or more logical cores, but also supports simulating two or more physical cores as one logical core. This allows the processor architecture to support instruction sets including hyper-threading and reverse hyper-threading. Through a management and control unit for the processor core's operating mode, dynamic switching between hyper-threading and reverse hyper-threading modes is achieved. For details on how to dynamically switch the processor core's operating mode based on the application's requirements for the number of running processor cores, please refer to the description in the corresponding section of the above embodiments.

[0126] Step S77: Receive application status notification sent by the operating system;

[0127] Step S78: Based on the application status notification, determine that the single-threaded application has ended running, adjust the processor to switch from reverse hyper-threading mode to hyper-threading mode, and process the processor's one physical core into multiple logical cores.

[0128] During the startup and operation of a single-threaded application on an electronic device, the operating system can monitor changes in the number of processor cores required by the application. When the required number of processor cores changes, the operating system can promptly notify the processor to switch the core operating mode to meet the actual needs of the application.

[0129] In practical applications, many applications require a large number of processor cores to run. The processor's core operating mode can be set to hyper-threading by default. This allows the operating system to monitor the application's running status during single-threaded operation, thus determining its real-time running state. Upon determining the application's termination, a notification indicating the application's completion can be sent to the processor. After receiving this notification, the processor can switch from its current reverse hyper-threading mode to hyper-threading mode. The application status monitoring and notification acquisition methods are not detailed in this application.

[0130] Similarly, during the operation of the above multi-threaded application, the number of processor cores required during the operation of the application can be monitored in accordance with, but not limited to, the method described above, to determine the switch from multi-threaded task to single-threaded task operation. The processor can be notified to switch to the reverse hyper-threading working mode in accordance with the method described above. The implementation process can be referred to the description of the corresponding part of the above embodiment, which will not be described in detail here.

[0131] In summary, in the practical application of this application, after the operating system determines the number of processor cores required for the application to run, it can compare this number with a preset core threshold to notify the processor to dynamically switch to the corresponding core working mode, hyper-threading working mode, or reverse hyper-threading working mode. This allows all physical cores of the processor to be used to execute the application's task threads, thus enabling the application to run on the required number of logical cores. This method of involving all physical cores in application computation improves the utilization of processing resources and significantly increases the application's running speed.

[0132] Reference Figure 8 The diagram below illustrates an optional example of the processing apparatus proposed in this application. The apparatus may include:

[0133] The kernel call instruction acquisition module 81 is used to acquire kernel call instructions for applications running on the operating system; the kernel call instructions can represent the number of processor cores required for the application to run.

[0134] The core operating mode adjustment module 82 is used to adjust the core operating mode of the processor in response to the core call instruction; the number of cores supported by the processor for the application to run varies under different core operating modes.

[0135] Execution module 83 is used to execute the task threads created by the application in accordance with the adjusted core working mode.

[0136] In some embodiments, such as Figure 9 As shown, the core working mode adjustment module 82 mentioned above may include:

[0137] The core working mode determination unit 821 is used to respond to the core call instruction and determine the core working mode corresponding to the number of processor cores required for the application to run.

[0138] The core virtualization processing unit 822 is used to process the physical cores of the processor into at least one logical core according to the determined core working mode.

[0139] Based on this, such as Figure 9 As shown, the execution module 83 described above may include:

[0140] The first execution unit 831 is configured to execute a task thread created by the application running by the obtained logical core.

[0141] In some embodiments, as shown in Figure 10 The core working mode adjustment module 82 can also include:

[0142] The task type obtaining unit 823 is configured to obtain a task type of the application in response to the core calling instruction; the task type is determined by the operating system.

[0143] The core working mode adjustment unit 824 is configured to adjust the processor to enter a core working mode corresponding to the task type according to a preset corresponding relationship.

[0144] The preset corresponding relationship represents a corresponding relationship between different task type applications and different core working modes of the processor.

[0145] Optionally, the core working mode of the processor includes a hyper-threading working mode and a reverse hyper-threading working mode, as shown in Figure 11 The core working mode adjustment unit 824 can include:

[0146] The processor core quantity determining unit 8241 is configured to determine a processor core quantity required by the application of the task type to run.

[0147] The first processing unit 8242 is configured to, in a case where the required processor core quantity is less than a core threshold value, adjust the processor to enter the reverse hyper-threading working mode, and process a plurality of physical cores of the processor into a logical core quantity of the required processor core quantity.

[0148] The core threshold value can be determined based on the physical core quantity of the processor and the logical core quantity that each of the physical cores can be processed into.

[0149] The second processing unit 8243 is configured to, in a case where the required processor core quantity is greater than or equal to the core threshold value, adjust the processor to enter the hyper-threading working mode, and process one physical core of the processor into a plurality of logical cores, so that the logical core quantity of the processor is greater than or equal to the required processor core quantity.

[0150] In some embodiments, the core working mode adjustment unit 824 can also include:

[0151] The third processing unit is configured to, in a case where the task type is a single-thread task, adjust the processor to enter the reverse hyper-threading working mode, and process a plurality of physical cores of the processor into one logical core.

[0152] The fourth processing unit is configured to, when the task type is a multi-threaded task, adjust the processor to enter the super-threaded working mode, and process one physical core of the processor into a plurality of logical cores.

[0153] According to the processing apparatus described in the above embodiments, the processing units can include:

[0154] The first processing unit is configured to process the physical core of the processor to obtain one or more logical cores with the same number of processor cores required by the operating system to run an application; or

[0155] The first packaging processing unit is configured to package all the physical cores of the processor into one logical core and then mount the logical core on the bus, so that the operating system can perceive one logical core.

[0156] The second packaging processing unit is configured to group and package all the physical cores of the processor, and mount the obtained plurality of logical cores on the bus, so that the operating system can perceive the plurality of logical cores.

[0157] Optionally, the processing apparatus further includes:

[0158] The application state notification receiving module is configured to receive the application state notification sent by the operating system.

[0159] The core working mode recovery module is configured to, according to the application state notification, determine that the single-threaded application ends running, adjust the processor to switch from the reverse super-threaded working mode to the super-threaded working mode, and process one physical core of the processor into a plurality of logical cores.

[0160] It should be noted that, as to various modules, units, etc. in the above-mentioned apparatus embodiments, they can be stored in the memory as program modules, and the processor executes the above-mentioned program modules stored in the memory to realize corresponding functions. As to the functions realized by each program module and its combination, and the achieved technical effects, reference can be made to the descriptions of the corresponding parts of the above-mentioned method embodiments, and the present embodiment will not be described again.

[0161] The present application also provides a computer readable storage medium, which can store a plurality of computer instructions, the computer instructions can be called and loaded by the processor to realize each step of the processing method described in the above embodiments.

[0162] Finally, it is indicated that, in the above-mentioned embodiments, unless the context clearly indicates otherwise, the words "one", "a", "an", and / or "the" do not mean "only one", but can include a plurality or more than one, unless the context clearly indicates otherwise. Generally, the terms "comprise", "comprising", "include", "including" and "contains", "containing" indicate that the steps and elements listed after these terms are included, but not as an exhaustive list of steps and elements, and the method or device can also include other steps or elements. The element defined by the phrase "comprising a" does not exclude the presence of additional identical elements in the process, method, product or device including the element.

[0163] In the description of the embodiments of the present application, unless otherwise specified, " / " means or, for example, A / B can mean A or B; "and / or" in this document is only a description of the relationship between the associated objects, which means that there can be three relationships, for example, A and / or B, which means that there are three cases of A alone, A and B together, and B alone. In addition, in the description of the embodiments of the present application, "multiple" means two or more than two.

[0164] The terms such as "first", "second" and the like used in the present application are only for the purpose of description, and are used to distinguish one operation, unit or module from another operation, unit or module, without necessarily requiring or implying any such actual relationship or order between the units, operations or modules. And it cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features, so the features with "first", "second" can explicitly or implicitly include one or more features.

[0165] In addition, each embodiment in the present specification is described in a progressive or parallel manner, and each embodiment focuses on the difference from other embodiments, and the same or similar parts between each embodiment can be referred to each other. For the device and electronic equipment disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple, and the related parts can be referred to the method part.

[0166] The above description of the disclosed embodiments enables a person skilled in the art to implement or use the present application. Various modifications to the embodiments will be apparent to those skilled in the art, and the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application will not be limited to the embodiments shown herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A processing method, comprising: obtaining a core calling instruction for an operating system to run an application; the core calling instruction being capable of representing a number of processor cores required by the application to run; adjusting a core working mode of a processor in response to the core calling instruction; wherein the processor supports different numbers of cores for the application to run in different core working modes; executing task threads created by the application to run in the adjusted core working mode, so that logical cores of the processor participate in the application to run in any core working mode; the core working mode of the processor comprising a first working mode and a second working mode, the first working mode being to process physical cores of the processor into logical cores more than the number of the physical cores, and the second working mode being to process physical cores of the processor into logical cores less than the number of the physical cores.

2. The method of claim 1, wherein the adjusting the core working mode of the processor in response to the core calling instruction comprises: determining a core working mode corresponding to the number of processor cores required by the application to run in response to the core calling instruction; processing physical cores of the processor into at least one logical core in the determined core working mode; the executing the task threads created by the application to run in the adjusted core working mode comprises: executing the task threads created by the application to run by the obtained logical cores.

3. The method of claim 1, wherein the adjusting the core working mode of the processor in response to the core calling instruction comprises: obtaining a task type of the application in response to the core calling instruction; the task type being determined by the operating system; adjusting the processor to enter a core working mode corresponding to the task type according to a preset correspondence; wherein the preset correspondence represents a correspondence between different task type applications and different core working modes of the processor.

4. The method of claim 3, wherein the adjusting the processor to enter the core working mode corresponding to the task type according to the preset correspondence comprises: determining a number of processor cores required by the application of the task type to run; if the number of processor cores required is less than a core threshold, adjusting the processor to enter the second working mode to process a plurality of physical cores of the processor into logical cores of the number of processor cores required; the core threshold being determined based on the number of the physical cores of the processor and the number of logical cores that each of the physical cores can be processed into; if the number of processor cores required is greater than or equal to the core threshold, adjusting the processor to enter the first working mode to process one physical core of the processor into a plurality of logical cores, so that the number of logical cores of the processor is greater than or equal to the number of processor cores required.

5. The method of claim 3, wherein the adjusting the processor to enter the core working mode corresponding to the task type according to the preset correspondence further comprises: ​ If the task type is a single-threaded task, adjusting the processor to enter the second working mode, processing multiple physical cores of the processor as one logical core; If the task type is a multi-threaded task, adjusting the processor to enter the first working mode, processing one physical core of the processor as multiple logical cores.

6. The method of claim 2 or 4 or 5, processing the physical core of the processor as at least one logical core, comprising: virtualizing the physical core of the processor to obtain one or more logical cores same as the number of processor cores required by the operating system to run the application; or, encapsulating all physical cores of the processor as one logical core and mounting it on the bus to enable the operating system to perceive one logical core; or grouping and encapsulating all physical cores of the processor to obtain multiple logical cores and mounting them on the bus to enable the operating system to perceive the multiple logical cores.

7. The method of claim 5, further comprising: receiving an application state notification sent by the operating system, determining that the single-threaded task ends running, adjusting the processor to switch from the second working mode to the first working mode, and processing one physical core of the processor as multiple logical cores.

8. A processing device, comprising: a core invocation instruction obtaining module for obtaining a core invocation instruction for an operating system to run an application; the core invocation instruction being able to represent the number of processor cores required by the application to run; a core working mode adjusting module for adjusting the core working mode of a processor in response to the core invocation instruction; in different core working modes, the processor supports different numbers of cores for the application to run; an execution module for executing a task thread created by the application to run according to the adjusted core working mode, so that in any core working mode, the logical cores of the processor participate in the application running; the core working mode of the processor includes a first working mode and a second working mode, the first working mode is to process the physical cores of the processor as more than the number of physical cores of logical cores, and the second working mode is to process the physical cores of the processor as less than the number of physical cores of logical cores.

9. An electronic device, comprising: a memory for storing a program for implementing the processing method of any one of claims 1-7; a processor having at least one physical core for loading and executing the program stored in the memory to implement the processing method of any one of claims 1-7.

10. A computer storage medium having a plurality of computer instructions stored thereon, the computer instructions being executed by a processor to implement the processing method of any one of claims 1-7.

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