A hardware detection and defense mechanism for microprocessor buffer overflow

Abstract

The present invention discloses a hardware detection and defense mechanism for microprocessor buffer overflow, which is applied to the fields of processor hardware security and large-scale digital integrated circuits. The present invention addresses the following problems in the prior art: (1) it is impossible to detect the overflow behavior of a buffer array crossing the boundary; (2) the defense measures may cause the processor to stop running, crash, or run away; (3) the impact on the processor's operating performance is relatively serious; and (4) the detection and defense mechanism deployed at the software level is easily bypassed. The present invention is based on the custom extension of microprocessor instructions and the real-time construction of a program control flow graph in the microprocessor, so as to achieve real-time detection of buffer overflow behavior and real-time protection of return addresses at the hardware level of the microprocessor, shield the processor's permission to access the memory buffer of the current instruction execution according to the real-time detection result, invalidate the buffer overflow attack suffered by the microprocessor, and ensure the security and reliability of the microprocessor hardware level to a certain extent.

Description

Technical Field

[0001] The present invention belongs to the field of processor hardware security and large-scale digital integrated circuits, and particularly relates to a hardware detection and defense technology. Background Art

[0002] A buffer overflow attack refers to a situation where the data written into the buffer exceeds the allocated buffer boundary because the program does not check the buffer boundary conditions or the boundary checking mechanism is bypassed, thereby overwriting the adjacent memory area, causing the local variables stored in the processor buffer to be tampered with, and even the risk of hijacking the processor control flow. Generally speaking, buffer overflows are divided into stack overflows and heap overflows. There are two main situations for stack overflows: (1) the local data is too large, exceeding the stack space allocated by the compiler, causing the stack to overflow upwards and overwriting existing data; (2) the function is recursive too many times, causing the stack space to grow rapidly downwards, thereby overwriting the data in the heap, bss segment, and data segment. Heap overflow is a memory overflow behavior, similar to the stack overflow (1). Buffer overflow attacks can cause processor crashes, loss of access control, control flow hijacking, and other hazards.

[0003] There are currently four main methods for detecting and defending against processor buffer overflows:

[0004] (1) Setting stack canary values. When the buffer overflow overwrites the return address, the buffer overflow attack is detected by detecting whether the canary value has been tampered with, such as "A. De, A. Basu, S. Ghosh and T. Jaeger," Hardware Assisted Buffer Protection Mechanisms for Embedded RISC-V," in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 39, no. 12, pp. 4453-4465, Dec. 2020, doi: 10.1109 / TCAD.2020.2984407." Random canary values ​​are generated using a physical unclonable function (PUF) and a true random number generator (TRNG);

[0005] (2) Protect the return address during processor operation to prevent the processor from being subjected to more serious control flow hijacking attacks, such as "D.Asmit, S Ghosh.HeapSafe:Securing Unprotected Heaps in RISC-V.ArXiv abs / 2105.08712 2021." The security of the return address is ensured by adding a security tag bit to the return address, "Zhang Yuxin, Rui Zhiqing, Li Weiwei, et al. PEC-V: Memory overflow defense mechanism based on RISC-V coprocessor. Computer System Applications, 2021, 30(11):9." Use PUF to encrypt / decrypt the return address, "Wang.Y, Wu.J, Yue.T, Ning.Z and Zhang.F.RetTag:hardware-assisted return address integrity on RISC-V.Proceedings of the 15th European Workshop on Systems Security.2022" Add an encrypted pointer verification code to the return address at the processor hardware level to ensure the integrity of the processor return address;

[0006] (3) Ensure the integrity of the processor program control flow. Ensure that the constructed program control flow graph is followed during program execution to achieve defense against control flow hijacking attacks. For example, "Shrivastava.KR, Concessao.KJ, Hota.C. Code Tamper-Proofing using Dynamic Canaries. 2019 25th Asia-Pacific Conference on Communications (APCC). pp. 238-243. 2019" ensures the integrity of the control flow by using dynamic canary values ​​to perform a series of XOR calculations at function call points and return points;

[0007] (4) Implementing buffer boundary checking at the processor hardware level, such as "S.Chiamwongpaet andK.Piromsopa, Boundary Bit: Architectural Bound Checking for Buffer-Overflow Protection, ECTI-CIT Transactions, vol.14, no.2, pp.162–173, Sep.2020." The compiler sets a boundary bit to define an object, and then the hardware will use the boundary bit to dynamically check the boundary of the object each time the memory is accessed;

[0008] The above-mentioned methods (1), (2), and (3) for detecting and defending against processor buffer overflows can only detect when the processor function return address has been attacked by a buffer overflow attack. They cannot detect overflows caused by buffer arrays crossing the boundary. Moreover, their defense measures will cause the processor to stop running. The encryption / decryption method of the return address in (2) will cause the processor to crash and run away. The disadvantages of method (4) are: (a) the setting of its boundary bits is implemented by the compiler, which may cause the mechanism to be bypassed; (b) each memory access requires a certain amount of time to complete the scanning of the access object boundary, which affects the processor's operating performance. Summary of the Invention

[0009] In order to solve the above technical problems, the present invention proposes a hardware detection and defense mechanism for microprocessor buffer overflow. Based on the custom extension of microprocessor instructions and the real-time construction of the program control flow graph in the microprocessor, real-time detection of buffer overflow behavior and real-time protection of return addresses are achieved at the hardware level of the microprocessor, and the permission of the processor to access the memory buffer of the current execution instruction is shielded according to the real-time detection results.

[0010] The technical solution adopted by the present invention is: a hardware detection and defense mechanism for microprocessor buffer overflow, comprising: a buffer overflow detection circuit 1, a buffer overflow detection circuit 2, and a buffer overflow defense circuit;

[0011] The first buffer overflow detection circuit implements pre-detection of buffer overflows one clock cycle in advance based on a custom extension of microprocessor instructions; the second buffer overflow detection circuit implements pre-detection of return address tampering attacks one clock cycle in advance based on the program control flow graph in the microprocessor;

[0012] The buffer overflow defense circuit completes the recovery or shielding of the memory buffer permission for executing instructions of the current processor according to the detection result of the buffer overflow detection circuit 1 or the buffer overflow detection circuit 2.

[0013] The beneficial effects of the present invention are as follows: the present invention realizes pre-detection of a buffer overflow attack one clock cycle in advance by combining a microprocessor compiler and a hardware circuit through a custom extended buffer overflow detection circuit based on microprocessor instructions, and can perform real-time detection of overflow behavior of an array crossing the boundary; the present invention uses a buffer overflow detection circuit constructed in real time based on a program control flow graph in a microprocessor, and uses a pure hardware method to ensure that the detection mechanism will not be bypassed by an attacker, and at the same time, a pre-detection result can be obtained one clock cycle in advance for the malicious behavior of a buffer overflow attack overwriting a function return address; the buffer overflow defense circuit can shield the permission of the current processor to execute instructions to access the memory buffer before the buffer overflow attack is completed based on the pre-detection results of the two buffer overflow detection circuits, thereby invalidating the buffer overflow attack suffered by the microprocessor and ensuring that the processor can continue to execute the program normally regardless of the buffer overflow attack; the present invention has the following advantages:

[0014] (1) The present invention uses a custom extended buffer overflow detection circuit based on microprocessor instructions, combined with a microprocessor compiler and a hardware circuit to achieve pre-detection of buffer overflow attacks one clock cycle in advance, and can also perform real-time detection of array overflow behavior;

[0015] (2) The present invention uses a buffer overflow detection circuit constructed in real time based on the program control flow graph in the microprocessor, and uses a pure hardware method to ensure that the detection mechanism cannot be bypassed by attackers. At the same time, the malicious behavior of overwriting the function return address by a buffer overflow attack can be detected in advance one clock cycle in advance;

[0016] (3) The present invention uses a buffer overflow defense circuit to block the current processor's permission to execute instructions and access the memory buffer before the buffer overflow attack is completed, based on the pre-detection results of the two buffer overflow detection circuits. This disables the buffer overflow attack suffered by the microprocessor and ensures that the processor can operate normally without being affected by the buffer overflow attack.

[0017] (4) The present invention is simple and efficient, does not require too many hardware resources, and only requires minor modifications to the microprocessor core. At the same time, it continuously and in real time collects the instructions and valid signals of the microprocessor decoding stage and the data addresses of the write-back stage, and can be easily deployed in the microprocessor. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 This is a functional structure diagram of the mechanism proposed in this invention.

[0019] Figure 2 This is a simplified diagram of the mechanism proposed in the present invention deployed in the open source RISC-V processor PULPino.

[0020] Figure 3 Schematic diagram of a buffer overflow attack designed to test the effectiveness of the present invention.

[0021] Figure 4 A graph showing the comparative simulation results of executing a buffer overflow attack example on a baseline processor and a processor deploying the mechanism proposed in the present invention.

[0022] Figure 5 The present invention provides some simulation results for real-time detection of buffer overflow attacks using the buffer overflow detection circuit of the present invention.

[0023] Figure 6 The results of the simulation of real-time detection of buffer overflow attacks using the buffer overflow detection circuit 2 of the present invention are as follows;

[0024] Figure 7 This is a comparison chart of area resource consumption when the present invention is deployed on the RISCV processor PULPino. DETAILED DESCRIPTION

[0025] To facilitate those skilled in the art to understand the technical content of the present invention, the present invention is further explained below with reference to the accompanying drawings.

[0026] Example 1

[0027] This embodiment combines the attached Figure 1 The content of the present invention is introduced in detail:

[0028] like Figure 1 As shown, a hardware detection and defense mechanism for microprocessor buffer overflow includes two buffer overflow detection circuits and a buffer overflow defense circuit. The two buffer overflow detection circuits continuously collect, process and analyze in real time the instructions, instruction valid signals, and data addresses of the memory access buffer in the write-back phase of the microprocessor, thereby pre-detecting buffer overflow and return address tampering attacks one clock cycle in advance. Finally, the detection results are input to the buffer defense circuit to complete the shielding of the current processor's instruction access buffer permissions, thereby completing the pre-defense of the buffer overflow attack one clock cycle in advance.

[0029] Buffer overflow detection circuit - based on a custom extension of microprocessor instructions to achieve pre-detection of buffer overflow one clock cycle in advance;

[0030] The buffer overflow detection circuit 2 realizes the pre-detection of the return address tampering attack one clock cycle in advance based on the program control flow graph in the microprocessor.

[0031] like Figure 1As shown, the buffer overflow detection circuit 1 includes: a Store instruction information decoding module, a buffer boundary checking module, a custom extended instruction, and a security register; the buffer overflow detection circuit 1 performs the following detection process on the buffer overflow:

[0032] First, based on the customizable extensibility of microprocessor instructions, by modifying the source code of the processor compilation tool chain and the hardware logic of the kernel decoding stage and execution stage, the following can be achieved: Figure 1 The custom extension instruction shown in the figure. When executed in the microprocessor, this custom extension instruction generates a drive signal for buffer overflow detection circuit 1 and a reference value, REF_BS, for the buffer space requested by the current function, required for hardware-level bounds checking. When writing C code, adding this custom extension instruction before functions that may cause buffer overflows (such as gets(), fgets(), strcpy(), strncpy(), and strlen()) implements hardware-level buffer space bounds checking for these functions.

[0033] Secondly, the instructions and instruction valid signals of the microprocessor decoding stage are collected in real time. According to the Store instruction information decoding module, the currently collected valid instruction (the instruction corresponding to the period when the instruction valid signal is high is the valid instruction) is analyzed in real time to see whether it is a Store instruction type, whether the immediate value imm carried by the instruction is greater than or equal to 0, and whether the increment △imm of the immediate value carried by the Store instruction compared to the immediate value carried by the previous Store instruction is 0 / 1 / 2 / 4. If the above conditions are met at the same time, the size value Y of the buffer space that the current Store instruction will consume is generated according to the funct3 code of the instruction. i Otherwise, Y i Set to 0, where i is 1 to N, and N represents the maximum count value of valid instructions that meet the conditions;

[0034] Finally, the buffer boundary check module calculates the buffer space consumption size value RT_BS in the current function segment in real time, where At the same time, the buffer space size value REF_BS requested by the function stored in the security register S0 is read and compared with RT_BS in real time. If REF_BS-RT_BS≥0, there is no buffer overflow attack in the current function segment, otherwise there is a buffer overflow attack.

[0035] like Figure 1 As shown, the buffer overflow detection circuit 2 includes: a program control flow graph real-time construction module, a buffer accessible upper limit address generation module, and an upper limit address check; the buffer overflow detection circuit 2 detects return address tampering attacks in the following process:

[0036] First, the program control flow graph (PCFG) is constructed in real time based on the processor instruction stream information. The steps are as follows: (1) Instructions and instruction valid signals of the microprocessor decoding stage are collected in real time; (2) The function entry address jump instruction (JAL) is detected in the collected valid instructions, and the target register (rd) of the JAL instruction is x1; (3) Based on the completion of (2), the SW instruction is detected, and the source register (rs2) of the SW instruction is x1; (4) Based on the completion of (3), the function return address and its corresponding buffer data address are pushed (PUSH); (5) The LW instruction is detected in the collected valid instructions, and the target register (rd) of the LW instruction is x1; (6) Based on the completion of (5), the function return address jump instruction JALR is detected; (7) Based on the completion of (6), the stack data is popped (POP).

[0037] Secondly, the upper limit address MAX_A of the memory accessible to the current function segment buffer is generated in real time according to the PCFG stack. When the real-time construction module of the program control flow graph is in the PUSH operation, the real-time upper limit address of the memory accessible to the buffer is the data address corresponding to the current return address stored in the buffer; when the real-time construction module of the program control flow graph is in the POP operation, the real-time upper limit address of the memory accessible to the buffer is the data address POPed out by the PCFG stack; the upper limit address MAX_A of the memory accessible to the current function segment buffer is selected from the initial value of the buffer accessible upper limit address and the real-time upper limit address of the buffer according to the signal indicating whether the PCFG stack starts to be built.

[0038] Finally, the upper limit address check module collects the data address RT_A of the memory access buffer in the processor write-back phase in real time, and compares it with the buffer accessible upper limit address MAX_A generated by the buffer accessible upper limit address generation module in real time. If |MAX_A-RT_A|>4, there is no overflow overwrite attack on the return address of the storage buffer in the current function segment running by the processor. Otherwise, there is an overflow overwrite attack on the return address. || indicates the absolute value.

[0039] like Figure 1 As shown, the buffer overflow defense circuit includes a finite state machine FSM and a Store instruction memory buffer access permission control logic. The buffer overflow defense circuit completes the shielding of the current processor's Store instruction memory buffer access permission based on the detection results of the buffer overflow detection circuit 1 or the buffer overflow detection circuit 2. The specific implementation process is as follows:

[0040] First, in the idle state of the finite state machine (FSM), it waits for the real-time detection results of the two buffer overflow detection circuits. If a buffer overflow attack occurs, the finite state machine (FSM) jumps to the next state. Otherwise, the Store instruction maintains the permission to access the memory buffer.

[0041] Secondly, the finite state machine (FSM) jumps to the next state to complete the pause processing of all pipelines of the microprocessor. Taking the open source RISC-V processor PULPino as an example, it includes the value acquisition stage, decoding stage, execution stage, and write-back stage.

[0042] Then, the finite state machine FSM jumps to the next state to complete the shielding of the memory buffer access permission of the Store type instruction executed by the current function segment of the processor.

[0043] Finally, the finite state machine FSM jumps to the next state to complete the recovery processing of all previously suspended pipelines of the microprocessor, and the finite state machine FSM jumps to the idle state.

[0044] Example 2

[0045] The method of shielding the permission of the current processor to execute instruction memory access buffer is: forcibly pulling down the enable signal of the write processor buffer generated by the processor write back stage according to the Store instruction.

[0046] Example 3

[0047] The reason why the mechanism proposed in the present invention can respectively realize pre-detection and defense against buffer overflow and return address tampering attacks one clock cycle in advance is that: both buffer overflow detection circuits collect information from the processor decoding and write-back stages to give detection results, the buffer overflow defense circuit is implemented in the processor write-back stage, and the attack point of buffer overflow and return address tampering attacks is at the time of buffer data rewriting, which lags one clock cycle compared to the processor write-back stage.

[0048] Example 4

[0049] This embodiment combines the attached Figure 2 , to illustrate the ease of deployment of the present invention:

[0050] like Figure 2 As shown, the two buffer overflow detection circuits of the present invention are connected to the processor pipeline by continuously and in real time collecting the instructions and valid signals of the microprocessor decoding stage and the data addresses of the write-back stage; the buffer overflow defense circuit of the present invention is connected to the processor pipeline by modifying the enable signal of the processor buffer generated according to the Store instruction in the processor write-back stage.

[0051] Example 5

[0052] This embodiment combines the attached Figure 3-6 , to illustrate the effectiveness of the present invention:

[0053] The open source RISCV processor PULPino is used as the experimental verification platform. The baseline processor and the processor implementing the mechanism proposed by the present invention are compared and run as follows: Figure 3 The buffer overflow attack example shown in the following example. The result of its operation is as follows Figure 4 As shown in the figure, the baseline processor suffered a control flow hijacking after executing the buffer sample code. When executing function method11 in the processor, its function return address was overflowed and overwritten with the entry address of the function shellcode, resulting in the processor control flow being hijacked to execute shellcode after executing method11. When the processor deploying the mechanism proposed by the present invention executed the buffer sample code, due to the existence of the mechanism proposed by the present invention, the processor was not affected by the buffer overflow attack and could run correctly.

[0054] Get the simulation waveforms of the two buffer overflow detection circuits in the mechanism proposed by the present invention when executing the buffer overflow attack example code, such as Figure 5 、 6 shown.

[0055] right Figure 5 Analysis: From the signal security_regs_rdata_i, we can know that the buffer size requested by the current function segment transmitted by the custom extension instruction is REF_BS = 0x14Byte. According to the signal stack_use_total, the actual buffer space consumption value calculated in real time by the buffer boundary check module increases from 0x to 0x18. When RT_BS = 0x18Byte, it is greater than REF_BS, that is, REF_BS-RT_BS = -4 < 0. According to stack_remain_space = 0xffff_fffc, the buffer requested by the currently executed function segment is about to overflow. According to is_buffer_overflow_o = 1'b1, the buffer overflow detection circuit based on the custom extension of the RISCV processor instruction successfully detected the buffer overflow attack.

[0056] right Figure 6Analysis: From the signal limit_addr_reg, we can know that the upper limit address that the current executing function segment can access is MAX_A=0x107fdc. According to the signal sw_dtcm_addr, the data address of the memory access buffer in the real-time acquisition write-back phase has RT_A=0x107fd8 and RT_A=0x107fdc, that is, |MAX_A-RT_A|=4or 0≤4, so there is a buffer overflow attack. According to the signal is_buffer_overflow_2o=1'b1, it can be confirmed that there is a buffer overflow attack.

[0057] Example 6

[0058] This embodiment combines the attached Figure 7 , to illustrate the advantage of the present invention of low area resource consumption:

[0059] The mechanism of the present invention deployed in PULPino is used to obtain the area through DC (Design Compiler) synthesis and compared with the DC comprehensive area of ​​PULPino, as shown in the following example: Figure 7 The process library used by DC is TSMC 130nm, with a clock cycle of 6ns.

[0060] right Figure 7 Analysis: The DC comprehensive area of ​​the present invention under TSMC's 130nm process library accounts for 9.1% of the PULPino area; the DC comprehensive area of ​​the buffer detection circuit one accounts for 0.48% of the PULPino area; the buffer detection circuit two accounts for 8.64% of the PULPino area; the DC comprehensive area of ​​the buffer defense circuit accounts for 0.01% of the PULPino area; among them, the buffer detection circuit two has a higher area consumption due to the existence of the program control flow dynamic stack created in real time, but it is no more than 9% of the total processor area.

[0061] In summary, the present invention proposes a hardware detection and defense mechanism for microprocessor buffer overflow. Through a custom extended buffer overflow detection circuit based on microprocessor instructions, combined with a microprocessor compiler and hardware circuit, pre-detection of buffer overflow attacks one clock cycle in advance is achieved, and overflow behavior of arrays crossing the boundary can be detected in real time; through a buffer overflow detection circuit constructed in real time based on the program control flow graph in the microprocessor, a pure hardware method is used to ensure that the detection mechanism will not be bypassed by attackers, and at the same time, a pre-detection result can be obtained one clock cycle in advance for the malicious behavior of overwriting the function return address in a buffer overflow attack; through a buffer overflow defense circuit, based on the pre-detection results of the two buffer overflow detection circuits, the permission of the current processor to execute instructions to access the memory buffer can be shielded before the buffer overflow attack is completed, invalidating the buffer overflow attack suffered by the microprocessor and ensuring that the processor can operate normally without being affected by the buffer overflow attack; the present invention is simple and efficient, does not require too many hardware resources, only requires minor modifications to the microprocessor core and can be easily deployed in the microprocessor.

[0062] Those skilled in the art will appreciate that the embodiments described herein are intended to aid the reader in understanding the principles of the present invention, and it should be understood that the scope of the present invention is not limited to such specific descriptions and embodiments. Various modifications and variations are readily apparent to those skilled in the art. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention are intended to be included within the scope of the claims.

Claims

1. A hardware detection and defense mechanism for microprocessor buffer overflow, characterized in that: include: a buffer overflow detection circuit 1, a buffer overflow detection circuit 2, and a buffer overflow defense circuit; The first buffer overflow detection circuit implements pre-detection of buffer overflow based on a custom extension of microprocessor instructions; the second buffer overflow detection circuit implements pre-detection of return address tampering attacks based on the program control flow graph in the microprocessor; The buffer overflow defense circuit completes the recovery or shielding of the memory buffer permission for executing instructions of the current processor according to the detection result of the buffer overflow detection circuit 1 or the buffer overflow detection circuit 2.

2. A hardware detection and defense mechanism for microprocessor buffer overflow according to claim 1, characterized in that: The buffer overflow detection circuit includes: a custom extension instruction, a Store instruction information decoding module, a buffer boundary check module and a security register; When writing C code, add custom extension instructions before functions where buffer overflow may occur; The Store instruction information decoding module analyzes in real time whether the currently collected valid instructions meet the following conditions: Whether it is a Store instruction type, whether the immediate value imm carried by the instruction is greater than or equal to 0, and whether the delta imm of the immediate value carried by the current Store instruction compared to the immediate value carried by the previous Store instruction is 0 / 1 / 2 / 4; If both are satisfied, the size value Y of the buffer space that the current Store instruction will consume is generated according to the funct3 code of the instruction. i Otherwise, Y i Set to 0, where i is 1 to N, and N represents the maximum count value of valid instructions that meet the conditions detected continuously; The buffer boundary check module calculates the buffer space consumption value RT_BS in the current function segment in real time, where At the same time, the buffer space size value REF_BS requested by the function stored in the security register is read and compared with RT_BS in real time. If REF_BS-RT_BS≥0, there is no buffer overflow attack in the current function segment, otherwise there is a buffer overflow attack.

3. A hardware detection and defense mechanism for microprocessor buffer overflow according to claim 1, characterized in that: The second buffer overflow detection circuit includes: a program control flow graph real-time construction module, a buffer accessible upper limit address generation module, and an upper limit address check; The buffer accessible memory upper limit address generation module is in a push operation or a pop operation according to the program control flow graph in real time to obtain the buffer accessible memory upper limit address in real time; The upper limit address check module collects the data address RT_A of the memory access buffer during the processor's write-back phase in real time, and compares it with the upper limit address MAX_A of the memory accessible to the buffer in real time. If |MAX_A-RT_A|>4, then there is no overflow overwrite attack on the return address of the storage buffer in the current function segment running by the processor. Otherwise, there is an overflow overwrite attack on the return address.

4. A hardware detection and defense mechanism for microprocessor buffer overflow according to claim 3, characterized in that: When the real-time construction module of the program control flow graph is in PUSH operation, the upper limit address of the buffer memory that can be accessed in real time is the data address corresponding to the current return address stored in the buffer; when the real-time construction module of the program control flow graph is in POP operation, the upper limit address of the buffer memory that can be accessed in real time is the data address POPed out by the PCFG stack.

5. A hardware detection and defense mechanism for microprocessor buffer overflow according to claim 1, characterized in that: The buffer overflow defense circuit includes: a finite state machine (FSM) and a Store instruction access buffer permission control logic. The implementation process of the buffer overflow defense circuit is as follows: A1. In the idle state of the finite state machine (FSM), wait for the real-time detection results of the two buffer overflow detection circuits. If a buffer overflow attack occurs, execute step A2. Otherwise, maintain the permission of the Store instruction to access the buffer. A2, the finite state machine FSM performs state jump and completes the pause processing of all pipelines of the microprocessor; A3. The finite state machine (FSM) performs a state jump to complete the shielding of the memory buffer access permission of the Store type instruction executed by the current function segment of the processor; A4. The finite state machine FSM performs a state jump to complete the recovery processing of all previously paused pipelines of the microprocessor. At the same time, the finite state machine FSM performs a state jump to the idle state.

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