Semiconductor device and method of manufacturing the same, system

Abstract

This application provides a semiconductor device and a method and system for fabricating the same. The method for fabricating the semiconductor device includes: forming a first stacked structure, the first stacked structure including a core region and a diced region; forming a dielectric isolation layer on the first stacked structure, and forming a via groove in a portion of the dielectric isolation layer corresponding to the core region; forming a first channel hole penetrating the first stacked structure, wherein the projection of the first channel hole onto the dielectric isolation layer is at least partially aligned with the projection of the via groove onto the dielectric isolation layer; and forming a second stacked structure on the dielectric isolation layer, and forming a second channel hole penetrating the second stacked structure, wherein the projection of the second channel hole onto the dielectric isolation layer is located within the projection range jointly formed by the via groove and the first channel hole on the dielectric isolation layer.

Description

Technical Field

[0001] This application relates to the field of semiconductor design and manufacturing, and more specifically, to the structure, fabrication method, and semiconductor device system of a semiconductor device (3D NAND). Background Technology

[0002] In current 3D NAND memories, the storage performance of 3D NAND is typically achieved by vertically stacking multiple layers of memory cells. 3D NAND uses three-dimensional stacking technology to transform traditional 2D integrated film into 3D stacked integration, effectively improving the integration density of memory devices.

[0003] In 3D NAND flash memory, the storage cells with storage function are provided by channel structures. As the number of vertically stacked layers increases, the etching difficulty of high aspect ratio channel holes also increases. Therefore, existing technologies typically employ dual-stack or multi-stack techniques to etch channel holes. Specifically, a first stacked structure can be formed first, and a lower channel hole (LCH) can be etched. Then, a second stacked structure is formed on the first stacked structure, and an upper channel hole (UCH) connected to the lower channel hole is etched within the second stacked structure. The lower and upper channel holes together constitute the channel hole (CH) of the stacked structure. Stepwise etching of the channel holes reduces the processing difficulty and improves product yield.

[0004] It should be understood that the content described in the background section is only for the purpose of helping to understand the technical solutions disclosed in this application, and is not necessarily prior art before the filing date of this application. Summary of the Invention

[0005] This application provides a method for fabricating a semiconductor device. The method includes: forming a first stacked structure, the first stacked structure including a core region and a diced region; forming a dielectric isolation layer on the first stacked structure, and forming a via groove in a portion of the dielectric isolation layer corresponding to the core region; forming a first channel hole penetrating the first stacked structure, wherein the projection of the first channel hole onto the dielectric isolation layer is at least partially aligned with the projection of the via groove onto the dielectric isolation layer; and forming a second stacked structure on the dielectric isolation layer, and forming a second channel hole penetrating the second stacked structure, wherein the projection of the second channel hole onto the dielectric isolation layer is located within the projection range jointly formed by the via groove and the first channel hole on the dielectric isolation layer.

[0006] In one embodiment, prior to forming the enlarged via groove, the method further includes: forming a first photoresist layer having a first photolithographic pattern and a second photolithographic pattern on the side of the dielectric isolation layer away from the first stacked structure, wherein the first photolithographic pattern corresponds to the dicing region and the second photolithographic pattern corresponds to the core region; forming a marking groove through the dielectric isolation layer and extending into the first stacked structure via the first photolithographic pattern; and forming an initial enlarged via groove extending into the dielectric isolation layer via the second photolithographic pattern.

[0007] In one embodiment, the marking groove and the initial enlarged groove are formed in a single process.

[0008] In one embodiment, the step of forming the enlarged aperture groove includes: forming a hard mask layer in the marking groove, the initial enlarged aperture groove, and the dielectric isolation layer; and removing the hard mask layer in the initial enlarged aperture groove to form the enlarged aperture groove.

[0009] In one embodiment, the step of forming the enlarged aperture groove during the removal of the hard mask further includes: removing a portion of the dielectric isolation layer via the initial enlarged aperture groove to form the enlarged aperture groove, wherein the critical dimension of the initial enlarged aperture groove is larger than the critical dimension of the first channel hole.

[0010] In one embodiment, the step of removing the hard mask layer within the initial enlarged aperture groove includes: forming a second photoresist layer having a third photolithographic pattern on the hard mask layer; and removing the hard mask layer within the initial enlarged aperture groove via the third photolithographic pattern.

[0011] In one embodiment, the method further includes: removing a portion of the hard mask located on the dielectric isolation layer, wherein a portion of the hard mask located within the marking groove is retained to form an alignment mark.

[0012] In one embodiment, after forming the second stacked structure, the method further includes: forming a third photoresist layer having a fourth photolithographic pattern on the second stacked structure; and performing overlay alignment using the alignment mark, and forming a second channel hole through the second stacked structure via the fourth photolithographic pattern.

[0013] In one embodiment, the step of forming the first stacked structure includes: forming alternately stacked dielectric layers and sacrificial layers; removing a portion of the dielectric layers and the sacrificial layers to form a stepped structure; and forming a stepped dielectric layer on the stepped structure and within the cut region, wherein the stepped structure is located in the stepped region, and the stepped region is adjacent to the cut region.

[0014] In one embodiment, in the stacking direction of the first and second stacked structures, the size of the dielectric layer is smaller than the size of the dielectric isolation layer.

[0015] In one embodiment, before forming the second stacked structure, the method further includes: forming a filling structure within the first channel hole and the enlarged groove; and after forming the second channel hole, the method further includes: removing the filling structure via the second channel hole.

[0016] Another aspect of this application provides a semiconductor device, comprising: a first stacked structure; a dielectric isolation layer located on the first stacked structure and having a via channel structure, wherein the via channel structure penetrates at least one side of the dielectric isolation layer; a first channel structure penetrating the first stacked structure and at least partially aligned with and connected to the via channel structure; a second stacked structure located on the dielectric isolation layer; and a second channel structure penetrating the second stacked structure and at least partially aligned with and connected to the via channel structure.

[0017] In one embodiment, the critical dimension of the enlarged channel structure is greater than the critical dimension of the first channel structure, and / or the critical dimension of the enlarged channel structure is greater than the critical dimension of the second channel structure.

[0018] In one embodiment, the first stacked junction includes a core region, a step region, and a dicing region, the step region being adjacent to the dicing region, the first channel structure being located in the core region, and the semiconductor device further includes an alignment mark located in the dicing region and penetrating the dielectric isolation layer.

[0019] In one embodiment, in the stacking direction of the first stack structure and the second stack structure, the size of the dielectric isolation layer is larger than the size of the dielectric layer.

[0020] In another aspect, this application provides a semiconductor device system including a semiconductor device as described in any of the above embodiments; and a controller electrically connected to the semiconductor device and configured to control the semiconductor device to perform at least one of a read operation, a program operation, and an erase operation.

[0021] The method for fabricating the semiconductor device provided in this application may have at least one of the following beneficial effects:

[0022] According to some embodiments of this application, by enlarging the top region of the lower channel hole, the overlay window of the upper and lower channel holes is increased, thereby avoiding the risk of leakage caused by overlay misalignment.

[0023] According to some embodiments of this application, the top of the lower channel hole can be enlarged in the same process as the alignment groove is formed, which helps to save costs.

[0024] According to some embodiments of this application, the landing window of the upper channel hole on the lower channel hole can be significantly increased without adding an additional photoresist layer. Attached Figure Description

[0025] Other features, objects, and advantages of this application will become more apparent from the following detailed description of non-limiting embodiments, taken in conjunction with the accompanying drawings. In the drawings:

[0026] Figure 1 is a scanning transmission electron microscope image of a partial structure of a semiconductor device according to some embodiments;

[0027] Figure 2 This is an X-ray energy dispersive spectroscopy (EDS) diagram of a partial structure of a semiconductor device according to some implementation methods;

[0028] Figure 3 This is a flowchart of a method for fabricating a semiconductor device according to an exemplary embodiment of this application;

[0029] Figures 4 to 8 This is a process schematic diagram of a method for fabricating a semiconductor device according to an exemplary embodiment of this application;

[0030] Figure 9 is a schematic diagram of the mutual alignment relationship between the first channel hole, the second channel hole, and the enlarged groove of a semiconductor device according to an exemplary embodiment of this application;

[0031] Figure 10 This is a process diagram illustrating the formation of a second stacked structure in a semiconductor device according to an exemplary embodiment of this application;

[0032] Figure 11 This is a schematic diagram of the process for forming a second channel via in a semiconductor device according to an exemplary embodiment of this application;

[0033] Figure 12 This is a schematic diagram of the structure of a semiconductor device according to an exemplary embodiment of this application; and

[0034] Figure 13 This is a schematic diagram of a semiconductor device system according to an exemplary embodiment of this application. Detailed Implementation

[0035] To better understand this application, various aspects of this application will be described in more detail with reference to the accompanying drawings. It should be understood that these detailed descriptions are merely illustrative of exemplary embodiments of this application and are not intended to limit the scope of this application in any way. Throughout the specification, the same reference numerals refer to the same elements. The expression "and / or" includes any and all combinations of one or more of the associated listed items.

[0036] It should be noted that in this specification, the terms "first," "second," "third," etc., are used only to distinguish one feature from another and do not imply any limitation on the features, especially not any order of precedence. Therefore, without departing from the teachings of this application, the first stacking structure discussed herein may also be referred to as the second stacking structure, and the first channel via may also be referred to as the second channel via, and vice versa.

[0037] In the accompanying drawings, the thickness, dimensions, and shapes of the components have been slightly adjusted for ease of illustration. The drawings are for illustrative purposes only and are not drawn to scale. For example, the thickness of the dielectric isolation layer shown in the drawings of this application is not proportional to actual production. Terms such as “approximately,” “about,” and similar terms used herein are used as expressions of approximation, not as expressions of degree, and are intended to illustrate inherent deviations in measured or calculated values ​​that will be recognized by those skilled in the art.

[0038] It should also be understood that expressions such as "comprising," "including," "having," "containing," and / or "comprising" are open-ended rather than closed-ended expressions in this specification, indicating the presence of the stated features, elements, and / or components, but not excluding the presence of one or more other features, elements, components, and / or combinations thereof. Furthermore, when expressions such as "at least one of..." appear after a list of listed features, they modify the entire list of features, not just individual elements in the list. Additionally, when describing embodiments of this application, the word "may" is used to mean "one or more embodiments of this application." And the term "exemplary" is intended to refer to examples or illustrations.

[0039] Unless otherwise specified, all terms used herein (including engineering and technical terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains. It should also be understood that, unless expressly stated herein, terms defined in common dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the relevant art, and not as having an idealized or overly formalized meaning.

[0040] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0041] The features, principles and other aspects of this application are described in detail below.

[0042] The inventors of this application have discovered that in dual-stack (or multi-stack) stacking technology, an overlay process is typically used to form multiple aligned vias in multiple stacked structures step by step, thereby connecting the multiple vias to form a deep via (CH). Furthermore, in the current process of forming two stacked structures, an overlay process is required to form alignment grooves on the surface of the upper stacked structure. These alignment grooves can be used to align the subsequently formed upper and lower vias. Both the upper and lower vias are formed by etching the stacked structure layer by layer. However, due to limitations in the etching process, after the upper and lower vias are overlaid, there may be a certain degree of alignment misalignment. This will cause vias that should not be interconnected to connect, and pose a risk of interconnection leakage in the channel structures formed by subsequent processes.

[0043] Figure 1a These are scanning transmission electron microscope images of a partial structure of a semiconductor device according to some embodiments. Figure 1b yes Figure 1a A magnified view of a portion (dashed circle). Combined with... Figure 1a and Figure 1b It is clear that the alignment of the upper and lower channel structures has shifted. Figure 2 yes Figure 1b X-ray energy dispersive spectroscopy (EDS) analysis diagram. From Figure 2 It can be seen that some of the upper channel structure comes into contact with the lower channel structure that should not be connected due to alignment misalignment. This will cause charge leakage and reduce the function of the storage device.

[0044] This application proposes a semiconductor device and a method for manufacturing the same, which can at least partially improve or solve the above-mentioned problems, and can achieve the effect of significantly increasing the landing window of the upper channel hole on the lower channel hole without increasing the cost too much.

[0045] It should be noted that the semiconductor device described in the context of this application may be a three-dimensional memory or a part of a three-dimensional memory.

[0046] Figure 3 This is a flowchart of a semiconductor device fabrication method 1000 according to an embodiment of this application. For example... Figure 3 As shown, this application provides a method 1000 for fabricating a semiconductor device, comprising:

[0047] Step S1100: A first stacked structure is formed, the first stacked structure including a core region and a cutting region;

[0048] Step S1200: A dielectric isolation layer is formed on the first stacked structure, and an enlarged groove is formed in the portion of the dielectric isolation layer corresponding to the core region.

[0049] Step S1300: Forming a first channel hole penetrating the first stacked structure, wherein the projection of the first channel hole onto the dielectric isolation layer is at least partially aligned with the projection of the enlarged groove onto the dielectric isolation layer; and

[0050] In step S1400, a second stacked structure is formed on the dielectric isolation layer, and a second channel hole is formed through the second stacked structure, wherein the projection of the second channel hole on the dielectric isolation layer is located within the projection range jointly formed by the enlarged groove and the first channel hole on the dielectric isolation layer.

[0051] It should be understood that the steps shown in method 1000 are not exclusive, and other steps may be performed before, after, or between any of the steps shown. Furthermore, some of the steps shown may be performed simultaneously or in a sequence different from the steps described. Figure 3 The execution is performed in the order shown.

[0052] Figures 4 to 11 This is a schematic diagram of the process for fabricating a semiconductor device according to an embodiment of this application. The following is in conjunction with... Figures 4 to 11 The above steps S1100 to S1400 are further described.

[0053] Step S1100: A first stacked structure is formed, which includes a core region and a cutting region.

[0054] Figure 4 This is a schematic diagram illustrating the process of forming a first stacked structure of a semiconductor device according to an embodiment of this application. Figure 4 As shown, a first stacked structure 100 can be formed on a substrate 110. The first stacked structure 100 includes a core region 10 and a dicing region 20. In some embodiments, the first stacked structure 100 further includes a step region 30, and a step structure 140 is located within the step region 30, between the core region 10 and the dicing region 20. Exemplarily, a dielectric layer 120 and a sacrificial layer 130 can be alternately stacked on the substrate 110 first, and then a portion of the dielectric layer 120 and the sacrificial layer 130 can be removed to form a step structure 140. A step dielectric layer 150 is then covered on the step structure 140 (along the z-direction) and within the dicing region 20 (the region on one side of the step structure 140 along the x-opposite direction). The core region 10, the step region 30, and the dicing region 20 are arranged sequentially along the x-opposite direction.

[0055] In some embodiments, the material of the substrate 110 may include, for example, silicon (e.g., single-crystal silicon, polycrystalline silicon), silicon-germanium (SiGe), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), gallium arsenide (GaAs), gallium nitride (GaN), silicon carbide (SiC), or any combination thereof. The first stacked structure 100 may include a plurality of dielectric layers 120 and a plurality of sacrificial layers 130 alternately stacked in a direction perpendicular or substantially perpendicular to the substrate 110 (z-direction). Under the same etching conditions, the sacrificial layer 130 may have a high etch selectivity ratio with the dielectric layer 120 so that the dielectric layer 120 is hardly removed when the sacrificial layer 130 is removed in a subsequent process. In some examples, the material for the sacrificial layer 130 includes, for example, silicon nitride, and the material for the dielectric layer 120 and the step dielectric layer 150 includes, for example, silicon oxide.

[0056] For example, multiple dielectric layers 120 and sacrificial layers 130 can be alternately formed on substrate 110 using thin film deposition processes such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. A stepped structure 140 can be formed using a combination of photolithography and etching processes, and a stepped dielectric layer 150 can be formed on the stepped structure 140 and within the diced region 20 using the aforementioned thin film deposition processes.

[0057] It should be understood that the number of layers in the first stacked structure 100 is not limited to the number of layers shown in the figure. Rather, the number of stacked layers and the stacking height of the first stacked structure 100 can be designed according to actual needs. This application does not make any specific limitations in this regard.

[0058] Step S1200: A dielectric isolation layer is formed on the first stacked structure, and a dielectric isolation layer corresponding to the core region is formed thereon. Enlarged grooves are formed in the part.

[0059] Continue to refer to Figure 4 A dielectric isolation layer 160 and a first photoresist layer 170 can be sequentially formed on the first stacked structure 100. Exemplarily, the dielectric isolation layer 160 covers the core region 10, the step region 30, and the dicing region 20, and the first photoresist layer 170 covers the dielectric isolation layer 160. A first photolithographic pattern 171 and a second photolithographic pattern 172 can be formed on the first photoresist layer 170 through processes such as exposure and development. The first photolithographic pattern 171 is located above the dicing region 20 and corresponds to it; the second photolithographic pattern 172 is located above the core region 10 and corresponds to it. In subsequent processes, using the patterned first photoresist layer 170 as a mask, the portions of the first stacked structure 100 located within the core region 10 and the portions located within the dicing region 20 can be etched, respectively.

[0060] Figure 5 This is a schematic diagram illustrating the process of forming an initial enlarged via groove in a semiconductor device according to an embodiment of this application. Figure 5As shown, the dielectric isolation layer 160 and the first stacked structure 100 can be etched in the same process via the first photolithography pattern 171 and the second photolithography pattern 172 to form a marking groove 181 and an initial enlargement groove 180, respectively. The marking groove 181 is located within the cutting area 20, penetrates the dielectric isolation layer 160, and extends to the stepped dielectric layer 150 located within the cutting area 20. The initial enlargement groove 180 extends into the dielectric isolation layer 160. Exemplarily, the dimensions of the marking groove 181 in both the x and z directions are larger than the dimensions of the initial enlargement groove 180 in the same directions. There can be multiple initial enlargement grooves 180, which can be arranged in, for example, the x-direction within the dielectric isolation layer 160. In some embodiments, the initial enlargement groove 180 only extends into the dielectric isolation layer 160 without penetrating the dielectric isolation layer 160.

[0061] In some embodiments, the dielectric isolation layer 160 is larger in the z-direction than the dielectric layer 120 in the same direction to ensure that the dielectric isolation layer 160 is not etched through during the process step of forming the initial enlarged recess 180, thereby facilitating the subsequent machining of the first channel hole. In some embodiments, the initial enlarged recess 180 located within the dielectric isolation layer 160 is also larger in the z-direction than the dielectric layer 120.

[0062] Exemplarily, the dielectric isolation layer 160 can be formed on the first stacked structure 100 by a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. The material of the dielectric isolation layer 160 may be the same as that of the stepped dielectric layer 150, for example, silicon oxide. The material of the first photoresist layer 170 includes epoxy resin, which may consist of multiple layers with different dielectric constants.

[0063] Figure 6 This is a schematic diagram illustrating the process of forming a first hard mask layer in a semiconductor device according to an embodiment of this application. Figure 6 As shown, a first hard mask layer 190 can be formed on the marking groove 181, the initial via groove 180, and the dielectric isolation layer 160, and a second photoresist layer 210 can be formed on the first hard mask layer 190. In some embodiments, the second photoresist layer 210 has a third photolithographic pattern 211, which corresponds to the position of the initial via groove 180. Exemplarily, the first hard mask layer 190 can be formed by, for example, thin film deposition processes (including CVD / PVD, atomic layer deposition, ALD, or any combination thereof).

[0064] Figure 7 This is a schematic diagram of the process for forming a via groove in a semiconductor device according to an embodiment of this application. Figure 7As shown, a via 219 exposing the dielectric isolation layer 160 can be formed by etching away the first hard mask layer 190 located above the initial via 180 via the third photolithography pattern 211, and the dielectric isolation layer 160 can be etched through the via 219 to form the via 212. In some embodiments, the process of removing the first hard mask layer 190 located within the initial via 180 also includes removing a portion of the dielectric isolation layer 160 through the initial via 180 to form the via 212. The critical dimension of the via 212 is larger than the critical dimension of the via 219. It should be noted that in semiconductor structures, critical dimensions are used to describe structural features. The critical dimensions of the via 212 and the via 219 can refer to their dimensions along the x-direction, respectively. The via 212 can be formed by processes such as wet etching.

[0065] Step S1300, A first channel hole is formed that penetrates the first stacked structure, wherein the projection of the first channel hole on the dielectric isolation layer is at least partially aligned with the projection of the enlarged groove on the dielectric isolation layer.

[0066] Figure 8 This is a schematic diagram illustrating the process of forming a first channel via in a semiconductor device according to an embodiment of this application. Figure 8 As shown, the portion of the first hard mask layer 190 located above the dielectric isolation layer 160 can be removed, while the portion of the first hard mask layer 190 located within the marking groove 181 is retained and forms alignment marks 191. In some embodiments, a first channel hole 213 extending through the first stacked structure 100 and into the substrate 110 can be formed via the via reaming groove 212. The critical dimension of the first channel hole 213 is smaller than the critical dimension of the via reaming groove 212. It should be noted that the critical dimension of the first channel hole 213 may refer to the dimension of its top in the x-direction, and the critical dimension of the via reaming groove 212 may refer to the dimension of its bottom in the x-direction. In some of the embodiments described, after the via reaming groove 212 is formed, the first stacked structure 100 can be etched via the via reaming groove 212 by processes such as dry etching to form... Figure 8 The case shown is where the maximum dimension of the first channel hole 213 along the x-direction is smaller than the minimum dimension of the enlarged groove 212 along the x-direction.

[0067] In some embodiments, the critical dimension of the first channel hole 213 is also smaller than the critical dimension of the second photolithographic pattern 172. The first channel hole 213 is located within the core region 10 and is at least partially aligned with the enlarged recess 212. Exemplarily, the alignment of the first channel hole 213 with the enlarged recess 212 can be as follows: Figures 9a to 9b As shown. Reference Figure 9a As shown, the projection of the first channel hole 213 onto the dielectric isolation layer 160 can fall completely within the projection range of the enlarged groove 212 onto the dielectric isolation layer 160; Reference Figure 9bAs shown, only a portion of the projection of the first channel hole 213 onto the dielectric isolation layer 160 falls within the projection range of the enlarged groove 212 onto the dielectric isolation layer 160. Figures 9a to 9b The alignment of the second channel hole 221 formed by subsequent processes with the first channel hole 213 and the enlarged groove 212 is also shown. (Continue to refer to...) Figure 9a The projection of the second channel hole 221 onto the dielectric isolation layer 160 falls within the projection range of the enlarged groove 212 onto the dielectric isolation layer 160; Reference Figure 9b As shown, the projection of the second channel hole 221 on the dielectric isolation layer 160 falls within the projection range jointly formed by the enlarged groove 212 and the first channel hole 213 on the dielectric isolation layer 160.

[0068] It should be noted that the two-dimensional projection shape of the first channel hole 213 on the substrate 110 includes a circle, a square, or other arbitrary shapes, and this application does not limit it. The three-dimensional configuration of the first channel hole 213 can be a columnar hole with equal top and bottom sizes, or a conical hole with unequal top and bottom sizes, and this application does not limit it either.

[0069] Exemplarily, the first stacked structure 100 can be etched using, for example, a combination of photolithography and etching processes. In the context of this invention, the method for fabricating the first channel hole 213 omits some steps, such as planarization, surface cleaning, and slag removal. These are not the focus of this invention and will not be described in detail here. Those skilled in the art can add or omit steps in the fabrication method of this invention as needed.

[0070] Step S1400: A second stacked structure is formed on the dielectric isolation layer, and a second [structure] is formed penetrating the second stacked structure. The second channel hole, wherein its projection onto the dielectric isolation layer is located at the enlarged groove and the first channel hole in the dielectric isolation layer. Within the projection range formed by the layers together.

[0071] Figure 10 This is a schematic diagram illustrating the process of forming a second stacked structure in a semiconductor device according to an embodiment of this application. Figure 10 As shown, after the first channel hole 213 is formed, a filling structure 214 can be formed within the first channel hole 213 and the enlarged groove 212. Exemplarily, the filling structure 214 can fill the first channel structure 213 and the enlarged groove 212, and the upper surface of the dielectric isolation layer 160 can be smoothed by processes such as chemical mechanical polishing (CMP). A second stacked structure 200 can then be formed on the upper surface of the dielectric isolation layer 160.

[0072] In some embodiments, the second stacked structure 200 includes a core region 10, a step region 30, and a dicing region 20. The process steps for forming the second stacked structure 200 are similar to those for the first stacked structure 100. Specifically, a sacrificial layer 130 and a dielectric layer 120 may be alternately stacked on the dielectric isolation layer 160, and then a portion of the sacrificial layer 130 and the dielectric layer 120 may be removed to form a stepped structure 140', and a stepped dielectric layer 150 may be covered on the stepped structure 140' and within the dicing region 20. The stepped structure 140 in the first stacked structure 100 and the stepped structure 140' in the second stacked structure 200 together constitute the stepped structure 141 of the semiconductor device.

[0073] For example, multiple dielectric layers 120 and sacrificial layers 130 can be alternately formed on the dielectric isolation layer 160 by thin film deposition processes such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. A stepped structure 140' can be formed by a combination of photolithography and etching processes, and a stepped dielectric layer 150 can be formed on the stepped structure 140' using the aforementioned thin film deposition processes.

[0074] In some embodiments, a second hard mask layer 192 and a third photoresist layer 220 may be sequentially formed on the second stacked structure 200. The third photoresist layer 220 has a fourth photolithographic pattern 221. Alignment can be performed using alignment marks 191, and the second stacked structure 200 can be etched via the fourth photolithographic pattern 221 to form a structure as shown below. Figure 11 The second channel hole 221 shown penetrates the second stacked structure 200 and extends to the enlarged groove 212.

[0075] In some embodiments, the projection of the first channel hole 213 on the dielectric isolation layer 160 is located within the projection range of the enlarged groove 212 on the dielectric isolation layer 160; the projection of the second channel hole 221 on the dielectric isolation layer 180 is also located within the projection range of the enlarged groove 212 on the dielectric isolation layer 180.

[0076] In other embodiments, the projections of the first channel hole 213 and the second channel hole 221 onto the dielectric isolation layer 160 can both be located outside the projection range of the enlarged groove 212 onto the dielectric isolation layer 160, and the portion of the first channel hole 213 outside the projection range of the enlarged groove 212 is at least partially aligned with the portion of the second channel hole 221 outside the projection range of the enlarged groove 212. During the machining of the second channel hole 221, because the critical dimension of the enlarged groove 212 is larger than the critical dimension of the first channel hole 213, the landing window of the second channel hole 221 is increased, which helps to reduce the machining difficulty of aligning the first channel hole 213 and the second channel hole 221. Similarly, the critical dimension of the enlarged groove 212 can also be larger than the critical dimension of the second channel hole 221.

[0077] In some embodiments, after the second channel hole 221 is formed, the filling structure 214 located in the enlarged groove 212 and the first channel hole 213 can be removed through the second channel structure 221 to form a channel hole that penetrates the second stacked structure 200 and the first stacked structure 100 and extends to the substrate 110.

[0078] Another aspect of this application provides a semiconductor device. This semiconductor device can be fabricated using the fabrication methods described in any of the above embodiments.

[0079] refer to Figure 12 As shown, the semiconductor device 300 includes a first stacked structure 100', a second stacked structure 200', and a dielectric isolation layer 160. The dielectric isolation layer 160 is located on the first stacked structure 100' (along the z-direction) and has a via channel structure 313, which may be located only on the upper side of the dielectric isolation layer 160. The second stacked structure 200' is located on the dielectric isolation layer 160. A second channel structure 312 extends through the second stacked structure 200', and the second channel structure 312 is at least partially aligned with the via channel structure 200. A first channel structure 311 extends through the first stacked structure 100', and the first channel structure 311 is at least partially aligned with and connected to the via channel structure 313.

[0080] In some embodiments, the critical dimension of the enlarged channel structure 313 is larger than the critical dimensions of the first channel structure 311 and / or the second channel structure 312. It should be noted that the critical dimension of the first channel structure 311 and the second channel structure 312 can both refer to the dimension in the x-direction of the side closest to the enlarged channel structure 312.

[0081] In some embodiments, the first stacked structure 100' includes a core region 10, a step region 30, and a dicing region 20. A first channel structure 311 is located within the core region 10, a step structure 140 is located within the step region 30, and a step dielectric layer 150 is located within the step region 30 and the dicing region 20. Exemplarily, the step structure 140 consists of alternately stacked dielectric layers 120 and gate layers 130'. The portion of the first stacked structure 100' located within the core region 10 also consists of dielectric layers 120 and gate layers 130'. The dielectric layers 120 and the step dielectric layers 150 can be made of the same material, such as silicon oxide; the gate layer 130' is made of, for example, tungsten metal. In some embodiments, the semiconductor device 300 further includes an alignment mark 191 that extends from the upper surface of the dielectric isolation layer 160 through the dielectric isolation layer 160 and to the step dielectric layer 150.

[0082] In some embodiments, the dimension of the enlarged via structure 313 along the z-direction is larger than the dimension of the dielectric layer 120 in the same direction. The enlarged via structure 313 may penetrate only one side of the dielectric isolation layer 160, such as... Figure 12 As shown, the enlarged via structure 313 does not penetrate the lower side of the dielectric isolation layer 160. In other embodiments, the enlarged via structure 313 also penetrates the lower side of the dielectric isolation layer 160, forming a structure that contacts both the first stack structure 100' and the second stack structure 200'.

[0083] In some embodiments, the upper end of the first channel structure 311 is connected to the enlarged-hole channel structure 313, and the lower end of the second channel structure 312 is connected to the enlarged-hole channel structure 313, wherein the critical dimension of the enlarged-hole channel structure 313 is larger than the critical dimension of the first channel structure 311. For example, the enlarged-hole channel structure 313... Figure 12 The two-dimensional projection shape in the xz plane shown can be a rectangle with equal top and bottom dimensions, or a trapezoid with unequal top and bottom dimensions, or other shapes. The minimum dimension of the enlarged channel structure 313 along the x-direction is greater than the maximum dimension of the first channel structure 311 in the same direction.

[0084] In some embodiments, the semiconductor device 300 further includes a semiconductor layer 310, with a first stacked structure 100' located on the semiconductor layer 300 (along the z-direction). A first channel structure 311 extends through the first stacked structure 100' and into the semiconductor layer 300 in a direction perpendicular or approximately perpendicular to the semiconductor layer 310. The dielectric layer 120 and the gate layer 130' are alternately stacked in a direction perpendicular or substantially perpendicular to the semiconductor layer 310. Exemplarily, the material of the semiconductor layer 310 may include, for example, silicon (e.g., single-crystal silicon, polycrystalline silicon), silicon-germanium (SiGe), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), gallium arsenide (GaAs), gallium nitride (GaN), silicon carbide (SiC), or any combination thereof.

[0085] Another aspect of this application provides a semiconductor device system, such as Figure 13 As shown, the three-dimensional storage system includes a semiconductor device 300 and a controller 302 as described in any embodiment of this application. The semiconductor device 300 includes a plurality of storage strings with storage functions, each storage string being composed of a plurality of storage cells. The controller 302 is electrically connected to the semiconductor device 300 via peripheral circuitry and is configured to control the operation of the storage strings.

[0086] In some embodiments, the semiconductor device 300 is electrically connected to and controlled by the controller 302. The controller 302 may, for example, control the application of different voltage signals to the memory cells (not shown) in the semiconductor device 300 to control the semiconductor device 300 to perform at least one of, for example, read operations, programming operations, and erase operations.

[0087] In some implementations, controller 302 may be configured to control the operation of semiconductor device 300, such as read, program, and erase operations. Controller 302 may also be configured to manage various functions related to data stored or to be stored in semiconductor device 300, including but not limited to bad block management, garbage collection, logic-to-physical address translation, and wear leveling.

[0088] In some embodiments, the semiconductor device 300 includes a 3D NAND memory, which comprises a plurality of memory cells arranged in a three-dimensional stacked manner. In some embodiments, the semiconductor device system also includes a connector 301, which can be connected to a device such as a host computer for transmitting data.

[0089] In some embodiments, the semiconductor device system includes a solid-state drive (SSD), a memory card, or any combination thereof. In some embodiments, the controller 302 and the semiconductor device 300 may be integrated onto the SSD to form a semiconductor device system. The storage capacity and / or operating speed of the SSD may be higher than that of the memory card. The semiconductor device 300 of any embodiment of this application can be used in storage devices or memory cards such as memory sticks, PC cards, compact flash (CF) cards, smart media (SM) cards, multimedia cards, SD cards, and universal flash memory (UFS).

[0090] The above description is merely an illustration of the embodiments of this application and the technical principles employed. Those skilled in the art should understand that the scope of protection involved in this application is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the technical concept. For example, technical solutions formed by substituting the above features with (but not limited to) technical features with similar functions disclosed in this application.

Claims

1. A method for fabricating a semiconductor device, characterized in that, The method includes: A first stacked structure is formed, the first stacked structure including a core region and a cutting region; A dielectric isolation layer is formed on the first stacked structure, and an enlarged groove is formed in the portion of the dielectric isolation layer corresponding to the core region; A first channel hole is formed through the enlarged groove, penetrating the first stacked structure, wherein the projection of the first channel hole on the dielectric isolation layer is at least partially aligned with the projection of the enlarged groove on the dielectric isolation layer; and A second stacked structure is formed on the dielectric isolation layer, and a second channel hole is formed through the second stacked structure, wherein the projection of the second channel hole on the dielectric isolation layer is located within the projection range jointly formed by the enlarged groove and the first channel hole on the dielectric isolation layer.

2. The method according to claim 1, wherein, Before forming the enlarged groove, the method further includes: A first photoresist layer having a first photolithographic pattern and a second photolithographic pattern is formed on the side of the dielectric isolation layer away from the first stacked structure, wherein the first photolithographic pattern corresponds to the dicing region, and the second photolithographic pattern corresponds to the core region; and A marking groove is formed through the first photolithographic pattern, penetrating the dielectric isolation layer and extending into the first stacked structure, and an initial enlarged-hole groove is formed through the second photolithographic pattern, extending into the dielectric isolation layer.

3. The method according to claim 2, wherein, The marking groove and the initial enlarged hole groove are formed in one process.

4. The method according to claim 3, wherein, The step of forming the enlarged groove includes: A hard mask layer is formed within the marking groove, the initial enlargement groove, and on the dielectric isolation layer; and The hard mask layer inside the initial enlarged groove is removed to form the enlarged groove.

5. The method according to claim 4, wherein, The step of forming the enlarged aperture groove during the removal of the hard mask layer further includes: The enlarged groove is formed by removing a portion of the dielectric isolation layer via the initial enlarged groove, wherein the critical dimension of the initial enlarged groove is larger than the critical dimension of the first channel hole.

6. The method according to claim 4, wherein, The step of removing the hard mask layer within the initial enlarged groove includes: A second photoresist layer having a third photolithographic pattern is formed on the hard mask layer; and The hard mask layer within the initial enlarged groove is removed via the third photolithography pattern.

7. The method according to claim 6, wherein, The method further includes: The portion of the hard mask layer located on the dielectric isolation layer is removed, while the portion of the hard mask layer located within the marking groove is retained and forms an alignment mark.

8. The method according to claim 7, wherein, After forming the second stacked structure, the method further includes: A third photoresist layer with a fourth photolithographic pattern is formed on the second stacked structure; and The alignment is performed using the alignment marks, and the second channel hole through the second stacked structure is formed via the fourth photolithographic pattern.

9. The method according to claim 3, wherein, The steps for forming the first stacked structure include: This forms alternating stacked dielectric and sacrificial layers; Removing a portion of the dielectric layer and the sacrificial layer to form a stepped structure; and A stepped medium layer is formed on the stepped structure and within the cutting area. The step structure is located in the step area, which is adjacent to the cutting area.

10. The method according to claim 9, wherein, In the stacking direction of the first and second stacked structures, the size of the dielectric layer is smaller than the size of the dielectric isolation layer.

11. The method according to claim 1, wherein, Before forming the second stacked structure, the method further includes: A filling structure is formed within the first channel hole and the enlarged groove; and After forming the second channel hole, the method further includes: The filling structure is removed via the second channel hole.

12. A semiconductor device, characterized in that, include: A first stacked structure includes a core region and a step region. The portion of the first stacked structure located in the core region includes a dielectric layer, and the portion of the first stacked structure located in the step region includes a dielectric layer. A dielectric isolation layer is located on the first stacked structure and has an enlarged channel structure, wherein the enlarged channel structure penetrates at least one side of the dielectric isolation layer; A first channel structure extends through the first stacked structure and is at least partially aligned with and connected to the enlarged channel structure; A second stacked structure is located on the dielectric isolation layer; and A second channel structure extends through the second stacked structure and is at least partially aligned with and connected to the enlarged channel structure; In the stacking direction of the first stacked structure and the second stacked structure, the size of the dielectric isolation layer is larger than the size of the dielectric layer.

13. The semiconductor device according to claim 12, wherein, The critical dimension of the enlarged channel structure is greater than the critical dimension of the first channel structure, and / or the critical dimension of the enlarged channel structure is greater than the critical dimension of the second channel structure.

14. The semiconductor device according to claim 12, wherein, The first stacked junction includes a core region, a stepped region, and a cut region, wherein the stepped region is adjacent to the cut region, and the first channel structure is located in the core region. The semiconductor device further includes: Alignment marks are located in the cutting area and penetrate the medium isolation layer.

15. A semiconductor device system, characterized in that, include: The semiconductor device as described in any one of claims 12-14; as well as A controller, electrically connected to the semiconductor device, is configured to control the semiconductor device to perform at least one of a read operation, a program operation, and an erase operation.

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