Redistribution plate

Abstract

A single layer redistribution board used as a spatial transformer between a device under test ("DUT") and a test PCB can include a hard ceramic board. The DUT side of the board can have pads configured to connect with the device under test. Both sides of the board can include traces, vias, and pads to fan out the DUT pad pattern so that the side of the board opposite the DUT side has spatially transformed pads configured to connect with pads on the test PCB. Manufacturing the redistribution board can include calibration and alignment, laser milling vias, laser milling trenches and pads, copper plating, polishing and buffing, removing excess copper, and coating the copper surface.

Description

TECHNICAL FIELD

[0001] The present invention relates generally to an apparatus, system and method for a space transformer for use in manufacturing electronic devices and printed circuit boards to adapt the spatially dense pads on a device under test (DUT) to the less dense probe pads on a test printed circuit board. BACKGROUND

[0002] Space transformers are used in integrated circuit testing as adapters, or as a transition between spatially dense test pads on a device under test (DUT) and less dense probe pads on a test PCB. In layman's terms, a space transformer "fans out" the spatially dense test output from a DUT into a manageable and less spatially dense set of test pads for input into a test PCB. Or, in other words, a space transformer converts wafer level pad pitch and features to a larger pad pitch and / or features - typically the pad pitch and / or features of a test PCB. Prior available space transformer manufacturing processes are too complex, require too many steps, and are too expensive.

[0003] There is a need for an improved solution for a space transformer. The improvement can be a smaller pitch and / or geometry; or fewer layers required; or a less complex, cheaper or less error prone manufacturing process. SUMMARY

[0004] An improved redistribution board (also referred to as a "space transformer" or "space converter") system and method for testing circuit devices is disclosed. The present disclosure refers to the device being tested as a "device under test" or "DUT".

[0005] The improved redistribution board can fan out (i.e., spatially redistribute) the small pads on a DUT by fanning out a first portion of the DUT pads on the DUT side of the redistribution board, and fanning out a second portion of the DUT pads on a second side (test PCB side) of the redistribution board, resulting in a less spatially dense pattern of pads on the test PCB side of the redistribution board. BRIEF DESCRIPTION OF DRAWINGS

[0006] The features and advantages of the present invention will become more apparent from the detailed description in conjunction with the accompanying drawings, in which:

[0007] FIG. 1a illustrates an exemplary DUT with pads.

[0008] FIG. 1b illustrates a top view of the pads on the DUT of FIG. 1a.

[0009] FIG. 2 illustrates an exemplary test PCB and pads on the exemplary test PCB.

[0010] Figure 3 shows a feature arrangement on the DUT side of an exemplary redistribution board for four rows of pads on the top of the DUT in Figures la and lb.

[0011] Figure 4 shows a feature arrangement on the test PCB side of an exemplary redistribution board for four rows of pads on the top of the DUT in Figures la and lb.

[0012] Figure 5 shows a feature arrangement on the DUT side of an exemplary redistribution board for all of the pads shown in the DUT of Figures la and lb.

[0013] Figure 6 shows a feature arrangement on the test PCB side of an exemplary redistribution board for all of the pads shown in the DUT of Figures la and lb.

[0014] Figure 7 shows an exemplary DUT with pads for describing a multi-layer implementation.

[0015] Figure 8 shows a feature arrangement on the DUT side of an exemplary redistribution board for the pads on the DUT in Figure 7.

[0016] Figure 9 shows a feature arrangement on the test PCB side of an exemplary redistribution board for the pads on the DUT in Figure 7.

[0017] Figure 10 shows a feature arrangement on the DUT side of an exemplary second layer redistribution board for the pads on the test PCB side of the redistribution board in Figure 9.

[0018] Figure 11 shows a feature arrangement on the test PCB side of an exemplary second layer redistribution board for the pads on the test PCB side of the redistribution board in Figure 9.

[0019] Figure 12 shows an exemplary test PCB and exemplary pads on the test PCB for use in conjunction with the multi-layer configurations shown in Figures 7-12.

[0020] Figure 13 shows a simplified cross-sectional view of an exemplary multi-layer configuration with three redistribution boards.

[0021] Figure 14 shows a flowchart of an exemplary process for manufacturing a redistribution board as described herein. DETAILED DESCRIPTION

[0022] This application claims priority to U.S. Non-Provisional Application 17 / 144,087, filed January 7, 2021, which is incorporated by reference herein.

[0023] A system and method for a redistribution board or space transformer is disclosed.

[0024] As used herein, the unit of measurement “um” means micrometers, or one millionth of a meter.

[0025] Legend of the drawings:

[0026] The following table is for convenience only and shall not be construed to limit any inconsistent disclosure herein.

[0027]

[0028]

[0029]

[0030] A system and method for testing electrical circuit devices is disclosed that improves the redistribution board (also referred to as a "space transformer" or "space converter"). The disclosure refers to the device being tested as the "device under test" or "DUT".

[0031] In the disclosure herein, "redistribution board" refers to a space transformer, generally used to refer to the space transformer disclosed herein.

[0032] A DUT is an electronic device, such as a microchip or other electronic circuit. A DUT includes pads that can be used to connect with another device (e.g., a DUT can eventually be mounted on a larger circuit board, and can be connected with such a larger circuit board through one or more pads) and / or for testing.

[0033] A DUT can have a variety of shapes, sizes, designs, and / or pad patterns. In one embodiment, a DUT can be a square that is about 60 mm on each side. DUT sizes can vary, for example, from a square that is 10 mm on each side to a square that is 100 mm on each side. DUTs can have other shapes and sizes.

[0034] The drawings contained in this disclosure and referenced herein are not intended to be to scale, to the exact dimensions, and relative component sizes as described below, but rather to show the general arrangement, size, and relative size in an understandable manner (although some components are very small). Adjustments to the arrangement, pattern, size, density / pitch, and form factor of components can be within the skill of one of ordinary skill in the art. Such adjustments, which can and inevitably will be needed for the specific implementation of the technology and invention disclosed herein, are within the scope of this disclosure.

[0035] Apparatus

[0036] Figure la shows an exemplary DUT 100 having pads 110a-n, 112a-n, 114a-n, and 116a-n.

[0037] FIG. lb illustrates a pad pattern of an exemplary DUT 100. As shown in FIG. lb, the DUT 100 includes pads 110a-n, 112a-n, 114a-n, and 116a-n, which can be arranged or patterned in eight rows of sixteen pads each, the arrangement shown in FIG. lb. The pattern and arrangement of the pads 110a-n, 112a-n, 114a-n, and 116a-n can vary widely. Those of ordinary skill will appreciate that the disclosure herein can be modified or adapted to apply to a wide variety of DUT pad arrangements, patterns, sizes, footprints, and pitches. In one exemplary embodiment, the DUT pads 110a-n, 112a-n, 114a-n, and 116a-n can have a diameter of 30 um and a pitch of 100 um.

[0038] While many variants are known in the art, DUTs are typically tested by electrically connecting the DUT pads directly or indirectly to a test PCB. When the DUT pads are connected to the test PCB, the test PCB runs test programs and test schemes by sending electrical signals to the DUT and receiving electrical signals from the DUT. The redistribution board disclosed herein is an adapter between the DUT pads and the interconnect pads on the test PCB.

[0039] FIG. 2 illustrates a test probe arrangement on an exemplary test PCB 200. In one embodiment, as shown in FIG. 2, the test interconnect pads 210a-n, 220a-n, 230a-n, and 240a-n on the test PCB 200 can be arranged as shown in FIG. 2, which can be made of copper with a protective coating of nickel and gold, which can be circular with a diameter of about 420 um, and which can have a pitch of 650 um. As those of ordinary skill will appreciate, other materials can also be used for the test interconnect pads.

[0040] The redistribution board 300 can include a pre-fabricated hard ceramic board made at least partially of silicon nitride or other ceramic, a polymeric material such as FR4, quartz, or a similar material suitable for substrates known in the art.

[0041] As shown in FIGS. 3 and 4, the redistribution board 300 can have two sides: a DUT side 330, and a test PCB side 360. FIG. 3 illustrates the arrangement and pattern of features on the DUT side 330. FIG. 4 illustrates the arrangement and pattern of features on the test PCB side 360.

[0042] The DUT side 330 of the redistribution board 300 can have pads 335a-n and vias 340a-n, which are configured to match the pads 110a-n and 112a-n on the DUT 100, respectively. The test PCB side 360 of the redistribution board 300 can have vias 365a-n, which correspond to the vias 340a-n on the DUT side 330 of the redistribution board 300.

[0043] The pads on the test PCB 200 and redistribution board 300, as well as the pads on other test PCBs and redistribution boards disclosed herein, can be BGA (ball grid array), wire bonds, or any other connection solution or method known in the art.

[0044] As shown in FIG. 3, the DUT side 330 of the redistribution board 300 can include traces 345a-n for connecting the pads 335a-n to vias 350a-n. The vias 350a-n pass through the redistribution board 300 and connect to pads 385a-n on the test PCB side 360 of the redistribution board 300. Because the features on the DUT side 330 and the corresponding features on the test PCB side 360 are on opposite sides of the same redistribution board 300, the features on the test PCB side 360 that correspond to features on the DUT side 330 are reflected about a vertical axis, e.g., the pad 385n on the test PCB side 360 appears in the upper left corner of FIG. 4, but the corresponding feature on the DUT side 330 that is connected by a via appears in the upper right corner of FIG. 3.

[0045] FIG. 3 also shows vias 340a-n that are configured to connect with the pads 112a-n on the DUT 100. The vias 340a-n pass through the redistribution board 300 and connect to vias 365a-n on the test PCB side 360 of the redistribution board 300.

[0046] As shown in FIG. 4, the vias 365a-n pass through the redistribution board 300 to the vias 340a-n on the DUT side 330 of the redistribution board 300, and the vias 365a-n are connected to pads 380a-n by traces 375a-n. FIG. 4 also shows pads 385a-n that are connected to the vias 350a-n on the DUT side 330 of the redistribution board 300.

[0047] The size of the trace width can vary depending on the limitations related to the size, pitch, pattern, and density of other features and traces. In some embodiments, some traces or segments of some traces can be 15um. As is well known in the art, the resistance properties of a trace vary with the width of the trace, so it is generally desirable for the traces to be as wide as possible to reduce resistance and also to facilitate manufacturing. Depending on the particular implementation or application, the trace width can be configured to be as wide as possible, unless other features need to be avoided. Further, in some embodiments, it can be beneficial to use narrow trace width segments only on shorter traces, thereby avoiding undesirable resistance properties.

[0048] Using a "fan-out" scheme as shown in FIGS. 3 and 4, the large density pattern of small pads 110a-n and 112a-n on the DUT 100 can be spatially distributed to larger and less dense pads 385a-n and 380a-n that match the pads 210a-n and 220a-n on the test PCB 200. This enables a conversion or reallocation of the spatial and dimensional characteristics of the pads 110a-n and 112a-n on the DUT 100 to the spatial and dimensional characteristics of the pads 210a-n and 220a-n on the test PCB 200. The conversion can include feature size, density, feature shape, and / or spatial pattern / arrangement. The use of the redistribution board 300 facilitates a cheaper and more complex design and manufacture of the test PCB 200. Moreover, the designs disclosed herein are simpler and have a lower overall thickness.

[0049] FIGS. 5 and 6 are similar to FIGS. 3 and 4, respectively, and show exemplary fan-out designs for all of the pads 110a-n, 112a-n, 114a-n, and 116a-n in the DUT 100 of FIGS. 1a-1b, while FIGS. 3 and 4 show exemplary fan-out designs for only the pads 110a-n and 112a-n in the DUT 100 of FIGS. 1a-1b. FIG. 5 shows an exemplary DUT side 500 of the redistribution board 300 for the pads 110a-n, 112a-n, 114a-n, and 116a-n in the DUT 100. FIG. 6 shows an exemplary test PCB side 600 of the redistribution board 300 for the pads 110a-n, 112a-n, 114a-n, and 116a-n in the DUT 100.

[0050] In many space transformer applications, a single layer redistribution board as described herein will be sufficient to replace, for example, an MLO or MLC space transformer. In rare cases where a single layer redistribution board cannot replace an MLO or MLC space transformer, a sequence or stack of single layer redistribution boards can be used. For example, a first redistribution board can be designed to have probe pads on the DUT side that match the test probes of the DUT, and bond pads on the test PCB side that match the input probes of a second redistribution board. The second redistribution board can have probe pads on the DUT side that match the bond pads on the test PCB side of the first redistribution board, and output bond pads on the test PCB side that match the pads on the test PCB.

[0051] For example, as shown in FIGS. 7-12, two redistribution boards can be stacked as an interface between a DUT and a test PCB. Any number of redistribution boards can be stacked. FIGS. 7-12 show an embodiment using two redistribution boards.

[0052] FIG. 7 shows an exemplary DUT 700 with pads 750. The feature sizes, form factors, and densities in the multi-layer examples in FIGS. 7-12 can be similar to the sizes, form factors, and densities described herein for the single-layer examples.

[0053] FIG. 8 shows the arrangement of features on the DUT side 830 of a first redistribution board 800. The redistribution board 800 and the redistribution board 300 have similar features and characteristics, except that the first redistribution board 800 has fewer features than the redistribution board 300. The redistribution board 800 includes a DUT side 830 and a test PCB side 860, the features of which can be understood by reference to the detailed description of the redistribution board 300 herein. FIG. 9 shows the arrangement of features on the test PCB side 860 of the first redistribution board 800. The test PCB side 860 is configured to interface with a second redistribution board 1000, and not with a test PCB.

[0054] FIGS. 10 and 11 show the arrangement of features on the DUT side 1030 and the test PCB side 1060 of the second redistribution board 1000. FIG. 10 shows the arrangement of features on the DUT side 1030, and FIG. 11 shows the arrangement of features on the test PCB side 1060. The redistribution board 1000 is configured to interface between the first redistribution board 800 and a test PCB 1100 (shown in FIG. 12) and act as an adapter.

[0055] The DUT side 1030 is configured to connect with the test PCB side 860 of the first redistribution board 800. The pads 1035a-n and 1040a-n on the DUT side 1030 match the pads 885a-n and 880a-n on the test PCB side 860 of the first redistribution board 800.

[0056] The test PCB side 1060 is configured to connect with the test PCB 1100. The pads 1080a-n and 1085a-n on the test PCB side 1060 match the pads 1150a-n on the test PCB 1100.

[0057] The design of the redistribution board 1000 is similar to the redistribution board 800 in that both use a two-sided configuration to space and reposition pads. As shown in FIG. 10, the DUT side 1030 is configured such that the pads 1035a-n are connected to pads 1050a-n by traces 1045a-n. The pads 1050a-n can have different densities, spatial patterns, and / or other characteristics relative to the pads 1035a-n, as shown in FIG. 10. The pads (or vias) 1050a-n can be connected to vias that reach the pads 1085a-n on the test PCB side 1060 through the redistribution board 1000.

[0058] Pads 1040a-n on the DUT side 1030 of redistribution board 1000 can be connected to vias that pass through redistribution board 1000 to pads (or vias) 1065a-n on the test PCB side 1060. Pads 1065a-n on the test PCB side 1060 are connected to pads 1080a-n by traces 1075a-n. As shown in FIG. 11, pads 1050a-n can have different densities, spatial patterns, and / or other characteristics relative to pads 1065a-n.

[0059] As shown in FIGS. 11 and 12, pads 1085a-n and 1080a-n on the test PCB side 1060 of redistribution board 1000 can match pads 1150a-n on test PCB 1100, allowing stacked redistribution boards 800 and 1000 to function as a spatial transformer or redistributor between DUT pads 750a-n and test PCB pads 150a-n.

[0060] In one multi-layer embodiment using multiple redistribution boards, gold stud bumps can be used to connect multiple redistribution boards and for communication between multiple redistribution boards.

[0061] FIG. 13 is a cross-section of a very simple exemplary multi-layer assembly as disclosed herein. FIG. 13 shows a DUT 1302 with two pads 1303 and 1304 and three redistribution boards 1310, 1330, and 1350. Pads 1311 and 1312 on redistribution board 1310 are configured to connect with pads 1303 and 1304 on DUT 1302. Via 1313 and trace 1315 connect pad 1317 to pad 1313. Via 1314 and trace 1316 connect pad 1318 to pad 1312. Gold bumps 1319 and 1320 connect redistribution board 1310 to redistribution board 1330 at pads 1321 and 1322.

[0062] Trace 1331 and via 1333 connect pad 1321 to pad 1335. Trace 1332 and via 1334 connect pad 1322 to pad 1336. Gold bumps 1337 and 1337 connect redistribution board 1330 to redistribution board 1350 at pads 1339 and 1340. At redistribution board 1350, via 1351 and trace 1353 connect pad 1339 to pad 1355. Via 1352 and trace 1354 connect pad 1340 to pad 1356. A ball grid array including balls 1357 and 1358 allows redistribution board 1350 to be connected to a test PCB.

[0063] A person of ordinary skill will appreciate that the basic redistribution invention disclosed herein can be applied and / or implemented in many designs that vary in feature size, feature shape, density, and pitch, as well as other characteristics of the DUTs, redistribution board, and test PCB.

[0064] Manufacturing process

[0065] FIG. 14 shows an exemplary process for manufacturing a redistribution board (e.g., redistribution board 300 in FIGS. 13 and 14). Although multiple steps are disclosed, and some steps are described as having multiple sub-steps, alternative steps, and / or optional steps, the following process disclosure should not be interpreted as requiring any of the steps, sub-steps, alternative steps, and / or optional steps unless explicitly stated.

[0066] As described above, the redistribution board substrate can comprise a pre-fabricated hard ceramic board made at least in part of silicon nitride or other ceramic, a polymer material such as FR4, quartz, or similar materials suitable for substrates known in the art.

[0067] At step 1410, the substrate orientation and through-attaches are defined and marked on both sides of the redistribution board substrate. This enables the top side pattern to be aligned with the bottom side pattern. In general, it does not matter which side is marked first. Other techniques can be used to align and synchronize features on one side of the redistribution board with features on the other side of the redistribution board.

[0068] At step 1420, vias can be manufactured on the redistribution board. In one embodiment, the vias can be laser milled at the probe pad locations (e.g., 340a-n in FIG. 3) and test PCB (e.g., BGA) attachment locations (e.g., 350a-n in FIG. 3). In one embodiment, the following parameters can be used to laser mill the vias: UV laser at 355 nm wavelength, 5 W at 30%, spot size of 5 um, scan speed of 50 mm / s. A person of ordinary skill will appreciate that these parameters can be adjusted and still successfully achieve laser milling of the vias. After milling the vias, it can be important to verify the geometry and taper of the vias, the accuracy of the via placement with respect to their nominal locations, and to remove any fumes and / or debris from the substrate that was removed during the milling process.

[0069] The via can be circular, rectangular, or other shape. For example, in some embodiments, the via can be a circle with a diameter of 30um, or a square of 30um x 30um, or a rectangle of 30um x 50um. One consideration for the via shape can be the amount of fill material. Generally, the conductive properties of the via increase with increasing fill material, so a square of 30um x 30um can be more desirable than a circle with a diameter of 30um. The size, shape, orientation, and location of the via are generally dictated, limited, and / or influenced by the characteristics of the location, form factor, density, and / or other features.

[0070] At step 1430, trenches are fabricated on the redistribution board substrate. Generally, the trenches are fabricated on one side of the redistribution board, the redistribution board is flipped over, and then the trenches are fabricated on the other side using through- fiducials or other techniques / features for alignment and placement relative to the features on the opposite side. Although the trenches can be fabricated in different orders, it is generally more efficient to fabricate all of the trenches on the first side, flip the redistribution board, and then fabricate all of the trenches on the second side. As shown in FIGS. 3 and 4, after the copper is filled in, the trenches will become traces 345a-n and 375a-n.

[0071] In one embodiment, laser milling can be used to fabricate the trenches. Laser milling parameters for trench fabrication can include: a UV laser at 355nm wavelength, 20W varying between 30-40%, spot size varying between 12-15um, scan speed between 20-55mm / s. Those of ordinary skill will understand that these parameters can be adjusted and still successfully achieve laser milling of the trenches.

[0072] In addition, the pads (e.g., 335a-n, 385a-n, and 380a-n in FIGS. 3 and 4) can also be fabricated in this step using the same or similar techniques as used for the trenches.

[0073] Alternatively, a fluorine-based plasma process can be used to fabricate the vias, trenches, and / or pads.

[0074] In one embodiment, the trench depth can be 25um, and the trench width can be 15-30um. Those of ordinary skill will understand the design, fabrication, and functional considerations in adjusting the trench depth and / or width.

[0075] Generally, the order in which the vias, trenches, and pads are milled / fabricated can be modified and can vary.

[0076] At step 1440, both sides of the redistribution board are coated with electroplated copper. Although copper is generally considered the most suitable conductor and is used as the most suitable conductor, it is possible to use alternative conductive materials. Prior to electroplating, the surface of the substrate is prepared by removing excess particles to ensure that the copper adheres to the substrate (redistribution board). There are several options available for this preparation step. In one embodiment, a solvent cleaner / activator pretreatment and a chemical copper seed layer can be used. In another embodiment, a surface pretreatment can be performed using oxygen plasma followed by argon plasma and copper sputtering of the seed layer. Typical conditions for the oxygen plasma can be: 13.56 Mz plasma, power of 100 W, oxygen flow of 50 seem, and duration of 30 seconds. Other seeding techniques can be known in the art.

[0077] After preparation / cleaning, both sides of the redistribution board are coated with electroplated copper. In one embodiment, both sides of the redistribution board are coated simultaneously. Although not required, simultaneous coating of both sides of the redistribution board can be faster and / or can improve via fill than non-simultaneous coating.

[0078] Adjustment and optimization of the surface preparation, seed layer deposition, and bulk copper plating processes are generally important to ensure that all vias, pads, and trenches (traces) are completely filled and void free. In some embodiments, it can be beneficial to plate the copper a little thicker than necessary to ensure complete fill of the features for good measurement. The ordinarily skilled artisan will appreciate that such adjustment and optimization is dependent on the particular design, materials, and / or manufacturing limitations and / or environment.

[0079] At step 1450, the copper on each side of the redistribution board is polished and / or buffed to be flush with the substrate (redistribution board). Care and caution are important in this step to avoid damaging the substrate surface. A combination of polishing and buffing steps using various materials and chemicals can achieve fine polishing / buffing. High selectivity between the polishing / buffing rate of the substrate relative to the copper is also beneficial. Most ceramics, including silicon nitride, have very high selectivity relative to copper.

[0080] In one embodiment, polishing can be accomplished using a rotary polishing tool, such as a rotary disk that can be fixed to polish or polish a surface. The optimal rotary speed can be 150-300 rpm, but other speeds can also be used. Polishing using a rotary tool can be accomplished by using: 400-1200 grit pads, slurry (0.5um diamond slurry (e.g., ULTRA-SOL STD 0.5um 50M)); aluminum oxide slurry (e.g., ACUPLANE™ LK393C4 NG3 slurry) for improved surface finish and removal of metal traces. The grit pads and slurry can be applied repeatedly as needed to achieve acceptable results. Other polishing / polishing techniques known in the art can also be used.

[0081] At step 1460, the unpatterned substrate surface on each side of the redistribution plate can be further cleaned in a chemical etching solution to remove residual metal traces. In one embodiment, the etching solution can be a dilute solution of ammonium persulfate.

[0082] At step 1470, the copper surface (traces, vias, pads) can be protected from oxidation and handling by coating with nickel and gold using the well-established ENIG process, where the copper is coated with approximately 4um of electroless nickel, followed by a thin layer of electroless gold. If desired, in some embodiments, hard gold can be applied using an electrolytic process for further protection.

[0083] At optional step 1480, if the redistribution plate is to be subsequently connected to a test PCB using BGA processing, it can be desirable to coat a layer of solder resist on the test PCB side (e.g., test PCB side 360 in FIG. 4) of the redistribution plate, which can provide an additional layer of protection from handling defects.

[0084] In an alternative photolithography method, plasma etching can be used in whole or in part to fabricate features including vias, trenches, and pads on one or both sides of the redistribution plate. In another alternative, dry etching of the substrate using proprietary fluorine-based etching conditions can be used in whole or in part to fabricate features including vias, trenches, and pads on one or both sides of the redistribution plate.

[0085] One of ordinary skill in the art will appreciate that the fine design of the features on the redistribution plate will facilitate void-free filling of the traces and vias.

[0086] The present invention differs from the prior art in several ways: (i) it is the first to demonstrate a single-stage, double-sided space transformer for 40um or smaller probe pad pitch; (ii) the processing of a single-stage, double-sided plate, where trenches are fabricated in the substrate on either side. Traces are not generated in subsequent additional layers; (iii) the use of off-the-shelf, inventory substrates; (iv) a single-step metallization process for simultaneously filling the traces (trenches) and vias on both sides.

[0087] In general, the disclosed single layer redistribution plate and its manufacturing process has many advantages over MLC or MLO space transformers: the single layer redistribution plate as disclosed herein can be less expensive to manufacture, can require fewer process steps (fewer layers), can be simpler, can use less expensive materials, can require less design and / or manufacturing time, and can result in a thinner, easier to use final product, and results in a reduced probe depth (which is often a limitation depending on the characteristics of the particular application).

[0088] Industrial Applicability

[0089] The present invention disclosed herein is applicable at least to testing electronic circuit boards and other electronic devices.

Claims

1. A redistribution board comprising a circuit board substrate having a first side and a second side, wherein: the first side comprises a DUT pad and a DUT via; a largest dimension of the DUT pad is less than 40 um; a largest dimension of the DUT via is less than 40 um; the DUT pad is conductively connected by a first trace on the first side of the circuit board to a first via through the circuit board, and the first via is conductively connected to a first test pad on the second side of the circuit board; the DUT via is conductively connected by a second trace on the second side of the circuit board to a second test pad on the second side of the circuit board; an area of the first test pad is at least twice an area of the DUT pad; and an area of the second test pad is at least twice an area of the DUT via.

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