Chip detection method, device, apparatus and storage medium

Abstract

The application provides a chip detection method, device and equipment and a storage medium. The chip detection method is based on a preset detection circuit. The preset detection circuit comprises a chip interface, an upper pull resistor and a power supply interface connected in sequence. The chip interface is used for accessing a chip to be detected. The chip interface and the power supply interface are connected to a single-chip microcomputer. The method comprises the following steps: based on the preset detection circuit, obtaining command reply data of the chip to be detected under different parameter conditions; determining whether the chip to be detected meets the performance parameters of a preset reference chip according to the command reply data and preset reference data; and the preset reference data at least comprises command reply data of the preset reference chip obtained under the same parameter conditions of the chip to be detected. The application can greatly improve the accuracy of distinguishing detection, and reduce the misjudgment and missed judgment phenomenon caused by the traditional method.

Description

TECHNICAL FIELD

[0001] The application belongs to the chip technical field, and particularly relates to a chip detection method, device, equipment and storage medium. BACKGROUND

[0002] With the development of chip technology, more and more manufacturers produce chips. For the same specification and model (size, electrical performance, etc.) of chips (which can be but are not limited to chips on a single-chip microcomputer), there are often multiple products from multiple manufacturers on the market. However, the performance of products produced by different manufacturers is often uneven, so before using a chip, the chip usually needs to be detected to identify whether it is the selected chip.

[0003] In the prior art, when a chip is detected, especially when the processes of two chips are similar, the data of the two chips at a specific point are often not much different, so it is easy to cause misjudgment and missed judgment, resulting in an inaccurate detection result. SUMMARY

[0004] The application provides a chip detection method, device, equipment and storage medium, which can greatly improve the accuracy of distinguishing detection and reduce the misjudgment and missed judgment phenomenon caused by the traditional method.

[0005] The first aspect of the application provides a chip detection method based on a preset detection circuit. The preset detection circuit includes a chip interface, an upper pull resistor and a power supply interface connected in sequence. The chip interface is used to access a to-be-detected chip, and the chip interface and the power supply interface are connected to a single-chip microcomputer. The method comprises the following steps.

[0006] Based on the preset detection circuit, command reply data of the to-be-detected chip under different parameter conditions is obtained.

[0007] According to the command reply data and preset reference data, it is determined whether the to-be-detected chip meets the performance parameters of the preset reference chip. The preset reference data at least includes command reply data of the preset reference chip obtained under the same parameter condition as the to-be-detected chip.

[0008] In some embodiments of the application, obtaining the command reply data of the to-be-detected chip under different parameter conditions comprises the following steps.

[0009] The shortest interval time of the to-be-detected chip for different commands is obtained.

[0010] In some embodiments of the application, according to the command reply data and the preset reference data, it is determined whether the to-be-detected chip meets the performance parameters of the preset reference chip, comprising the following steps.

[0011] According to the shortest interval time and preset reference data, a shortest interval time of the power chip to be tested under the same command is determined, and a reference interval time of a preset reference chip is determined.

[0012] According to the shortest interval time to be tested and the reference interval time, whether the performance parameter of the chip to be tested meets the performance parameter of the preset reference chip is determined.

[0013] In some embodiments of the present application, according to the shortest interval time to be tested and the reference interval time, whether the performance parameter of the chip to be tested meets the performance parameter of the preset reference chip is determined, comprising:

[0014] A first difference value of the shortest interval time to be tested and the reference interval time corresponding to each command is calculated.

[0015] Whether at least one of the first difference values is greater than a first preset threshold value is determined.

[0016] If yes, it is determined that the performance parameter of the chip to be tested meets the performance parameter of the preset reference chip; if no, it is determined that the performance parameter of the chip to be tested does not meet the performance parameter of the preset reference chip.

[0017] In some embodiments of the present application, before determining whether the performance parameter of the chip to be tested meets the performance parameter of the preset reference chip according to the shortest interval time to be tested and the reference interval time, further comprising:

[0018] A time setting step is arranged to set an interval time between command data read by the reference chip and output command data;

[0019] A command test step is arranged to start chip detection and check whether the reference chip performs command reply within the interval time;

[0020] A time determination step is arranged to, if yes, re-execute the time setting step, decrease the interval time, re-execute the command test step, until the reference chip does not perform command reply within the current interval time, and determine the interval time set last time as the reference interval time of the reference chip to the read command data; and,

[0021] If no, the time setting step is re-executed, the interval time is increased, the command test step is re-executed, until the reference chip does not perform command reply within the current interval time, and the interval time set last time is determined as the reference interval time of the reference chip to the read command data.

[0022] In some embodiments of the present application, the command reply data of the chip to be tested under different parameter conditions is obtained, comprising:

[0023] The shortest reply time of the to-be-tested chip receiving a command reply after power supply again under different power-off times is obtained.

[0024] In some embodiments of the present application, the determination of whether the to-be-tested chip meets the performance parameter of the preset reference chip according to the command reply data and preset reference data comprises:

[0025] The determination of the to-be-tested command reply time of the power chip and the reference command reply time of the preset reference chip under the same power-off time according to the shortest reply time and preset reference data;

[0026] The determination of whether the to-be-tested chip meets the performance parameter of the preset reference chip according to the to-be-tested command reply time and the reference command reply time.

[0027] In some embodiments of the present application, the determination of whether the to-be-tested chip meets the performance parameter of the preset reference chip according to the to-be-tested command reply time and the reference command reply time comprises:

[0028] The second difference value of the to-be-tested command reply time and the reference command reply time corresponding to each power-off time is calculated;

[0029] The determination of whether the to-be-tested chip meets the performance parameter of the preset reference chip according to the second difference value corresponding to all power-off times respectively.

[0030] In some embodiments of the present application, the determination of whether the to-be-tested chip meets the performance parameter of the preset reference chip according to the second difference value corresponding to all power-off times respectively comprises:

[0031] The calculation of the sum of difference squares according to the second difference value corresponding to all power-off times respectively;

[0032] The determination of whether the sum of second difference squares is less than or equal to a second preset threshold value;

[0033] If yes, it is determined that the to-be-tested chip meets the performance parameter of the preset reference chip; if no, it is determined that the to-be-tested chip does not meet the performance parameter of the preset reference chip.

[0034] In some embodiments of the present application, before the determination of whether the to-be-tested chip meets the performance parameter of the preset reference chip according to the to-be-tested command reply time and the reference command reply time, the method further comprises:

[0035] The time setting step sets the power-off time and command reply time of the reference chip, and supplies power to the reference chip again after the power-off time;

[0036] The command test step is to send command data to the single-chip microcomputer and determine whether the reference chip receives the reply data of the single-chip microcomputer after the power supply of the reference chip for the command reply time.

[0037] The time determination step is to re-execute the time setting step and reduce the command reply time if yes, and to re-execute the command test step until the reference chip receives the reply data of the single-chip microcomputer, and to determine the current set command reply time as the reference command reply time of the reference chip under the current power-off time.

[0038] The time determination step is to re-execute the time setting step and reduce the command reply time if yes, and to re-execute the command test step until the reference chip receives the reply data of the single-chip microcomputer, and to determine the current set command reply time as the reference command reply time of the reference chip under the current power-off time.

[0039] In some embodiments of the present application, the power supply interface includes a first interface, a second interface and a transistor, the first interface is used to connect the single-chip microcomputer; the second interface is connected with the collector of the transistor to provide power supply for the transistor; the base of the transistor is connected with the first interface, and the emitter of the transistor is connected with the pull-up resistor to control the power-off time of the to-be-tested power chip.

[0040] Embodiments of the second aspect of the present application provide a chip detection device based on a preset detection circuit, the preset detection circuit includes a chip interface, a pull-up resistor and a power supply interface connected in sequence, the chip interface is used to access a to-be-tested chip, and the chip interface and the power supply interface are both connected with a single-chip microcomputer; the device includes:

[0041] The data acquisition module is used to acquire command reply data of the to-be-tested chip under different parameter conditions based on the preset detection circuit.

[0042] The result determination module is used to determine whether the to-be-tested chip meets the performance parameters of the preset reference chip according to the command reply data and preset reference data; the preset reference data is command reply data of a preset reference chip under the same parameter conditions as the to-be-tested chip.

[0043] Embodiments of the third aspect of the present application provide an electronic device including a memory, a processor and a computer program stored in the memory and executable on the processor, and the processor executes the computer program to implement the steps of the first aspect.

[0044] The embodiment of the fourth aspect of the present application provides a computer readable storage medium, which stores a computer program, and the program is executed by a processor to realize the method of the first aspect.

[0045] The technical solutions provided in the embodiments of the present application have at least the following technical effects or advantages:

[0046] The chip detection method provided in the embodiments of the present application is based on the preset detection circuit. After the to-be-detected chip is connected to the preset detection circuit, the command reply data of the to-be-detected chip under different parameter conditions can be detected, and then whether the to-be-detected chip meets the performance parameters of the preset reference chip is determined according to the detected command reply data and corresponding reference data (i.e., the preset reference data described below) of the preset reference chip. The performance (including but not limited to power consumption performance and diode performance) of the to-be-detected chip can be detected, so as to improve the yield of products and perform anti-counterfeiting identification (a chip with the same characteristic description and the preset reference chip belongs to the same manufacturer, and a chip without the same characteristic description and the preset reference chip does not belong to the same manufacturer). BRIEF DESCRIPTION OF DRAWINGS

[0047] Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The accompanying drawings are included to provide a description of the preferred embodiments and are not intended to limit the scope of the present application. Moreover, the same reference numerals are used throughout the same figures to designate similar or equivalent components.

[0048] In the drawings:

[0049] Figure 1 A frame structure schematic diagram of a preset detection circuit provided by an embodiment of the present application is shown;

[0050] Figure 2 A principle structure schematic diagram of a preset detection circuit provided by an embodiment of the present application is shown;

[0051] Figure 3 A flowchart of a chip detection method provided by an embodiment of the present application is shown;

[0052] Figure 4 A waveform schematic diagram of the shortest interval time of a reaction chip A for a certain command in an embodiment of the present application is shown;

[0053] Figure 5 A waveform schematic diagram of the shortest interval time of a reaction chip B for a certain command in an embodiment of the present application is shown;

[0054] Figure 6 A scatter plot schematic diagram of the shortest interval time of a preset reference chip for different commands in an embodiment of the present application is shown;

[0055] Figure 7 A scatter plot diagram of the shortest interval time of the to-be-tested chip for different commands is shown in an embodiment of the present application;

[0056] Figure 8 A scatter plot fitting diagram of the shortest interval time of the to-be-tested chip and the preset reference chip for different commands is shown in an embodiment of the present application;

[0057] Figure 9 A flow diagram of another chip detection method provided by an embodiment of the present application is shown;

[0058] Figure 10 A framework structure diagram of another preset detection circuit provided by an embodiment of the present application is shown;

[0059] Figure 11 A waveform diagram of the case that the chip is in a power-off time of 1 ms and an interval time of 99 μs is shown in an embodiment of the present application;

[0060] Figure 12 A waveform diagram of the case that the chip is in a power-off time of 1 ms and an interval time of 158 μs is shown in an embodiment of the present application;

[0061] Figure 13 A waveform diagram of the case that the chip is in a power-off time of 5 ms and an interval time of 158 μs is shown in an embodiment of the present application;

[0062] Figure 14 A scatter plot diagram of the shortest command reply time of the preset reference chip for different power-off times is shown in an embodiment of the present application;

[0063] Figure 15 A scatter plot diagram of the shortest command reply time of the to-be-tested chip for different power-off times is shown in an embodiment of the present application;

[0064] Figure 16 A scatter plot fitting diagram of the shortest command reply time of the to-be-tested chip and the preset reference chip for different power-off times is shown in an embodiment of the present application;

[0065] Figure 17 A flow diagram of another chip detection method provided by an embodiment of the present application is shown;

[0066] Figure 18 A structure diagram of an electronic device provided by an embodiment of the present application is shown;

[0067] Figure 19 A diagram of a storage medium provided by an embodiment of the present application is shown. DETAILED DESCRIPTION

[0068] The exemplary embodiments of the present application will be described in greater detail below with reference to the accompanying drawings. Although exemplary embodiments of the present application are shown in the drawings, it is understood that the present application can be implemented in various forms and should not be limited by the embodiments set forth herein. Rather, these embodiments are provided so that this application will be thorough and complete, and will fully convey the scope of the application to those skilled in the art.

[0069] It should be noted that, unless otherwise specified, the technical terms or scientific terms used in the present application should be understood as the general meaning understood by those skilled in the art to which the present application belongs.

[0070] In the prior related art, the same chips from different manufacturers can be distinguished by testing multiple times whether the chip has received a command reply. However, this method only detects whether the chip has received a command reply, without considering the minimum reply time interval of each command. The minimum reply time interval of the command is related to the logic initialization, timing logic, and loop processing after the chip replies to the command, and the same chips from different manufacturers often have a relatively large difference in the minimum command reply interval. Therefore, only by the way of whether the chip has received a command reply, the same chips from different manufacturers cannot be effectively distinguished, which is easy to misjudge and cause inaccurate chip distinction.

[0071] The present embodiment research finds that, in order to solve the problem that only by the way of whether the chip has received a command reply, the same chips from different manufacturers cannot be effectively distinguished, the minimum time from starting to being able to stably reply to a command of the chip under a fixed voltage (i.e. the shortest reply time of the chip receiving a command reply) can be measured to distinguish the same chips from different manufacturers. This test feedback is the minimum starting time of the internal digital part of the chip, and the same chips from different manufacturers are distinguished by comparing the minimum starting time. However, this method has a single sampling point, and when the process of two chips is similar, a single voltage cannot accurately reflect the difference in starting time, which is easy to misjudge and cause inaccurate chip distinction.

[0072] Based on the above findings, the present embodiment proposes a chip detection method, device, equipment and storage medium. The chip in the present embodiment is usually a chip applied to a single-chip microcomputer, which can be an analog chip or a digital chip, and the present embodiment does not make specific limitation thereto.

[0073] The chip detection method is based on a preset detection circuit, as shown in Figure 1 The preset detection circuit includes a chip interface, an upper pull resistor and a power supply interface connected in sequence, the chip interface is used for accessing a chip to be tested, and the chip interface and the power supply interface are both connected to a single-chip microcomputer.

[0074] As shown in Figure 2As shown, the power supply interface can include a DAC (Digital-to-Analog Converter) interface connected with the single-chip microcomputer, receiving the power supply voltage provided by the single-chip microcomputer, and outputting a fixed voltage or a variable voltage. The chip interface is connected with the chip to be tested, and can communicate with the chip to be tested, send data to the chip to be tested, and receive data feedback from the chip to be tested, etc. The chip interface can include two pins, one pin V1 connected with a pull-up resistor for IO output, and the other pin LIGND grounded, which can pull down the voltage of the pin V1 to 0. The pin V1 can be an open-drain output (or a push-pull output according to technical needs), and its output voltage is pulled up to the voltage of the pull-up resistor under the action of the pull-up resistor. The pin V1 outputs command data, and is set to input after outputting the command data, so as to be able to send command data and receive command reply data.

[0075] Based on the above-mentioned preset detection circuit, after the chip to be tested is connected to the preset detection circuit, the command reply data of the chip to be tested under different parameter conditions can be detected, and then whether the chip to be tested meets the performance parameters of the preset reference chip is determined according to the detected command reply data and the corresponding reference data (i.e. the preset reference data described below) of the preset reference chip. The performance (including but not limited to power consumption performance and diode performance) of the chip to be tested can be detected, so as to improve the yield of products and perform anti-counterfeiting identification on the chip (chips with the same characteristic description belong to the same manufacturer, and chips without the same characteristic description do not belong to the same manufacturer).

[0076] The performance parameters of the preset reference chip can include any performance parameter of the chip, such as electrical performance, logic processing performance, etc. In specific implementation, one or more appropriate performance parameters can be selected according to the performance concerned, so as to determine whether the performance parameters of the chip to be tested and the preset reference chip are consistent (substantially the same, allowing a common error).

[0077] As described above, the embodiment can be applied to the testing of chip performance in the chip production process, so as to improve the yield of products. It can also be applied to the anti-counterfeiting identification of chips in the chip use process, so as to ensure that the chips used are good chips and protect the performance of products. Accordingly, when applied to the chip production process, the preset reference chip is usually a chip with ideal performance produced by a manufacturer itself, and the electrical performance, size, internal logic, etc. of the preset reference chip can be tested and recorded before the chip to be tested, and used to check whether the subsequent production chips meet the standards. When applied to the chip use process, the preset reference chip is usually a chip with ideal performance produced by a manufacturer (which can be itself or an upstream manufacturer) to be selected. Similarly, the electrical performance, size, internal logic, etc. of the preset reference chip can be tested and recorded before the chip to be tested, and used to check whether the subsequent production chips meet the standards.

[0078] Please refer toFigure 3 A flowchart of a chip detection method provided by an embodiment of the present application is shown in FIG. 1. As shown in FIG. 1, the method comprises the following steps: Figure 3

[0079] In step S1, based on a preset detection circuit, command reply data of a chip to be detected under different parameter conditions is obtained.

[0080] In step S2, based on the command reply data and reference data of a preset reference chip, it is determined whether the chip to be detected meets the performance parameters of the preset reference chip.

[0081] The command can be any command for interaction between the chip and the single-chip microcomputer, which is not limited in the embodiment. The parameter conditions can include at least one of power-off time and command type. The command reply data of the chip to be detected under different parameter conditions can include command reply time of the chip to be detected under different power-off time, and / or command reply time of the chip to be detected for different types of commands.

[0082] The preset reference data can include at least command reply data of the preset reference chip under the same parameter conditions as the chip to be detected. Generally, before detecting the chip to be detected, the preset reference chip can be detected based on the preset detection circuit to obtain the reference data of the preset reference chip. The reference data can include all performance parameters of the preset reference chip. The performance parameters can be selectively tested according to the specific detection method (as long as all performance data required by the detection method is included), or all testable performance parameters of the preset reference chip can be tested, and then the test data is taken as the reference data of the preset reference chip.

[0083] In some embodiments, the parameter conditions include different types of commands. The step S1 can include the following processing: obtaining the shortest interval time of the chip to be detected for different commands.

[0084] The (shortest) reply interval time of the chip for the command can be understood as the (shortest) interval duration from receiving the command data by the chip to successfully replying the command data by the chip. The interval duration is related to the processing logic of reading and replying the command in the chip, and the logic initialization, timing logic and loop processing logic after replying the command. Different chips have a relatively large difference in the shortest interval time, so by testing the shortest interval time of each command, the performance difference between different chips can be detected.

[0085] The embodiment can test the shortest interval time of the chip for different commands by adjusting (continuously or discontinuously) the shortest interval time between reading the command data and outputting the command data for multiple times, and checking whether the chip can reply the command. ​

[0086] For example, the reference chip's reference interval time (i.e. the shortest interval time) for a certain command, the process of determining the shortest interval time can include the following processes: a time setting step, setting the shortest interval time between the reference chip reading command data and outputting command data; a command testing step, starting chip detection, checking whether the reference chip replies to the command within the shortest interval time; a time determining step, if yes, re-executing the time setting step and reducing the interval time, and re-executing the command testing step until the reference chip does not reply to the command within the current interval time, and determining the interval time set last time as the reference chip's reference interval time for the read command data; and if no, re-executing the time setting step and increasing the interval time, and re-executing the command testing step until the reference chip does not reply to the command within the current interval time, and determining the interval time set last time as the reference chip's reference interval time for the read command data.

[0087] It can be understood that the shortest interval time for all the commands to be tested of the reference chip or the chip to be tested can be determined according to the above process of determining the shortest interval time, which will not be described here. For example, Figure 4 and Figure 5 As shown in the figures (the horizontal coordinate represents time / μs, and the vertical coordinate represents voltage / V), they are respectively the test graphs of the shortest interval time for command X determined by the two chips (A and B) according to the above process of determining the shortest interval time. As shown in Figure 4 , the shortest interval time for command X of chip A is 4μs. As shown in Figure 5 , the shortest interval time for command X of chip B is 22μs.

[0088] According to the above shortest interval time testing method, after obtaining the shortest interval time corresponding to all the required commands, the corresponding relation scatter plot of the command type and the shortest interval time can be drawn for subsequent data acquisition and use. As shown in Figure 6 and Figure 7 , they are respectively the scatter plot of the shortest interval time for different commands of the chip to be tested and the scatter plot of the shortest interval time (i.e. the reference interval time) for different commands of the reference chip tested in the embodiment. The shortest interval time of each command can be obtained by referring to the above testing method, which will not be described here.

[0089] Correspondingly, step S2 can include the following processes: determining the shortest interval time to be tested of the power chip and the reference interval time of the preset reference chip under the condition of the same command according to the shortest interval time and the preset reference data; and determining whether the chip to be tested meets the performance parameter of the preset reference chip according to the shortest interval time to be tested and the reference interval time.

[0090] In view of the fact that the step S1 obtains the minimum interval time of the to-be-tested chip for different commands, the preset reference data in the embodiment also includes at least the minimum interval time of the preset reference chip for different commands. The data can also refer to the above-mentioned minimum interval time of the to-be-tested chip.

[0091] Since there is a relatively large difference in the minimum command reply interval of different chips for the same command, and the embodiment compares the to-be-tested minimum interval time of the to-be-tested chip and the reference interval time of the reference chip under the same command, not only whether the to-be-tested chip performs command reply is considered, but also the shortest time interval of the command reply is investigated, and the shortest time interval of multiple command data is compared, so that whether the to-be-tested chip meets the performance parameter of the preset reference chip can be determined more accurately, thereby greatly improving the accuracy of distinguishing detection, and reducing the missed judgment and misjudgment of the traditional method and the like.

[0092] In some other embodiments, the above-mentioned determining whether the to-be-tested chip meets the performance parameter of the preset reference chip according to the to-be-tested minimum interval time and the reference interval time can include the following processing: calculating a first difference value of the to-be-tested minimum interval time and the reference interval time corresponding to each command; determining whether at least one first difference value is greater than a first preset threshold value; if yes, determining that the to-be-tested chip and the preset reference chip are chips of different types; and if no, determining that the to-be-tested chip and the preset reference chip are chips of the same type.

[0093] The first preset threshold value can be a specific time value, for example, 0.5 μs, 1 μs, etc., or a ratio or percentage of the reference interval time, for example, 30%, 20%, etc. The embodiment does not make a specific limitation thereon. Specifically, the first preset threshold value can be set according to actual conditions. For example, when performing chip detection, if a larger fault tolerance rate is to be set to improve the product shipment rate, the first preset threshold value can be set to be relatively large. If a smaller fault tolerance rate is to be set to strictly control product quality, the first preset threshold value can be set to be relatively small.

[0094] When determining whether the to-be-tested chip meets the performance parameter of the preset reference chip, the minimum interval time scatter plot of the to-be-tested chip for different commands and the minimum interval time scatter plot of the reference chip for different commands (i.e., the reference interval time) can be fitted to obtain a fitted scatter plot of the minimum interval time of the to-be-tested chip and the reference chip for different commands as shown in FIG. 6. Figure 8 Based on the fitted scatter plot, the difference in the minimum interval time of the two chips for different commands can be observed more intuitively, and the deviation of the minimum interval time of the two chips for the same command, i.e., the above-mentioned first difference value, can be calculated. Figure 8

[0095] The above-mentioned embodiment is described in combination with the accompanying drawings. Figure 9 ​Take the identification and detection of the A factory chip as an example, the process of detecting the chip based on the shortest interval time of different commands is introduced in detail. As shown in Figure 9 , the reference interval time (the shortest interval time) of the reference chip of the A factory for different commands can be tested first. Then the shortest interval time of the measured chip for different commands is tested, and the first difference value of the shortest interval time of the measured chip and the reference chip for the same command is calculated. If the first difference value corresponding to any command is within 30% (other values can be set according to needs, which are not specifically limited in this embodiment) of the reference interval time of the reference chip, it is judged that the measured chip belongs to the A factory chip, otherwise the measured chip does not belong to the A factory chip.

[0096] In other embodiments, the parameter condition includes different power-off times, and the above step S1 can include the following processing: obtaining the shortest reply time of the measured chip for the received command after power supply again under different power-off times.

[0097] In order to obtain the shortest reply time of the measured chip for the received command under different power-off times, as shown in Figure 10 , the power supply interface of the preset detection circuit in this embodiment includes a first interface (DAC), a second interface (VCC) and a transistor. The first interface can be used to connect a single-chip microcomputer; the second interface is connected with the collector of the transistor to provide power supply for the transistor; the base of the transistor is connected with the first interface, and the emitter of the transistor is connected with a pull-up resistor to control the power-off time of the measured power chip, so that the shortest reply time of the chip for the received command under different power-off times can be detected.

[0098] When determining the command reply time corresponding to different power-off times, a power-off time can be determined first, and a command reply time can be configured. Then the command reply time under the power-off time is adjusted multiple times (which can be continuous adjustment or non-continuous adjustment), and whether the reference chip receives the reply data of the single-chip microcomputer is checked to test the measured command reply time of the chip for different power-off times.

[0099] Taking the acquisition of the reference command response time of a reference chip for a certain power-down time as an example, the specific process of determining the shortest command response time may include the following steps: a time setting step, setting the power-down time and command response time of the reference chip, and then resupplying the reference chip after the power-down time; a command testing step, after supplying power to the reference chip for the command response time, the control chip sends command data to the microcontroller and determines whether the reference chip receives the response data from the microcontroller; a time determination step, if yes, then re-execute the time setting step, decrease the command response time, and execute the command testing step again until the reference chip receives the response data from the microcontroller, and determine the currently set command response time as the reference command response time of the reference chip under the current power-down time; and if no, then re-execute the time setting step, increase the command response time, and execute the command testing step again until the reference chip can no longer receive the response data from the microcontroller, and determine the previously set command response time as the reference command response time of the reference chip under the current power-down time.

[0100] It is understandable that the shortest command time for the reference chip or the chip under test under different power-down times can be determined using the process described above for determining the shortest command response time, and will not be repeated here. For example... Figure 11 and Figure 12 The image shows the command data waveforms of the chip at power-down times of 1ms, intervals of 99μs, and 158μs. Figure 13 The figure shows the command data waveform of the chip during a power-down time of 5ms and an interval of 158μs. Figure 11 and Figure 12 In the diagram, the upper waveform represents the command data waveform of the chip under test, and the lower waveform represents the power supply voltage waveform of the chip. The power-down and power-up processes of the chip can be observed from the diagrams. Figure 13 (The power supply voltage waveform of the chip is omitted in the diagram). The command waveform is sent after power-on. Figure 11 It is known that the chip's power-down time is 1ms, and the interval from power-on to command transmission (the set command response time) is 99μs. The lack of a command response indicates that 99μs is not the shortest command response time for the chip under the 1ms power-down condition. The command response time needs to be gradually increased according to the aforementioned process for determining the shortest command response time until a command is received. Figure 12 As shown, the chip's power-down time is 1ms, and the interval from power-on to command transmission (the set command response time) is 158μs. The command response (with a break in the waveform) indicates that this 158μs is the shortest command response time for the chip under the 1ms power-down condition. Figure 13As shown, the power-off time of the chip is 5 ms, the interval from power-on to sending a command (set command reply time) is 158 μs, the command is not replied, and it is indicated that the 158 μs is not the shortest command reply time of the chip in the case of power-off for 5 ms.

[0101] After the shortest command reply time of the test chip and the preset reference chip corresponding to different power-off times is obtained according to the shortest command reply time test method, a scatter plot of the corresponding relationship between the power-off time and the shortest command reply time can be drawn, so as to facilitate subsequent data acquisition and use. As shown in Figure 14 and Figure 15 As shown (the abscissa represents the power-off time, in ms; the ordinate represents the shortest command reply time, in μs), they are respectively the scatter plot of the corresponding relationship between the power-off time and the shortest command reply time of the test chip tested in the embodiment, and the scatter plot of the corresponding relationship between the power-off time and the shortest command reply time of the reference chip. The shortest command reply time corresponding to each power-off time can be obtained according to the above test method, and will not be described here.

[0102] Correspondingly, the above step S2 can include the following processing: determining the test command reply time of the power chip and the reference command reply time of the preset reference chip under the same power-off time according to the shortest reply time and the preset reference data; and determining whether the test chip meets the performance parameter of the preset reference chip according to the test command reply time and the reference command reply time.

[0103] Since the step S1 obtains the shortest command reply time of the test chip under different power-off times, the preset reference data in the embodiment also includes at least the shortest command reply time (reference command reply time) of the preset reference chip under different power-off times.

[0104] The minimum time from starting to being able to stably reply to a command of the chip (i.e., the shortest command reply time) can reflect the minimum starting time of the digital part inside the chip, and different chips of the same type produced by different manufacturers can be distinguished by the minimum starting time.

[0105] Specifically, determining whether the test chip meets the performance parameter of the preset reference chip according to the test command reply time and the reference command reply time can include the following processing: calculating a first difference value of the test command reply time and the reference command reply time corresponding to each power-off time; and determining whether the test chip meets the performance parameter of the preset reference chip according to the first difference value corresponding to all power-off times.

[0106] Since there is a relatively large difference in the shortest command reply time of different chips under the same power-off time, the embodiment compares the shortest command reply time of the to-be-tested chip under the same power-off time with the reference command reply time of the reference chip, and compares the shortest command reply time corresponding to multiple power-off times. Since the minimum time from starting to being able to stably reply to a command (i.e., the shortest command reply time) of a chip can reflect the minimum starting time of the digital part inside the chip, the embodiment can accurately determine whether the to-be-tested chip meets the performance parameter of the preset reference chip by distinguishing the minimum starting time, thereby greatly improving the accuracy of the distinguishing detection and reducing the missed judgment and misjudgment of the traditional method.

[0107] Further, the determination of whether the to-be-tested chip meets the performance parameter of the preset reference chip according to the first difference value corresponding to all power-off times can include the following processing: calculating the sum of squares of the difference values according to the first difference value corresponding to all power-off times; determining whether the sum of squares of the difference values is less than or equal to a second preset threshold value; if yes, determining that the to-be-tested chip meets the performance parameter of the preset reference chip; and if no, determining that the to-be-tested chip does not meet the performance parameter of the preset reference chip.

[0108] The second preset threshold value is usually a constant, which can be set according to actual conditions. For example, when detecting a chip, if a larger fault tolerance rate is required to improve the product shipment rate, the first preset threshold value can be set to be relatively large. If a smaller fault tolerance rate is required to strictly control the product quality, the first preset threshold value can be set to be relatively small.

[0109] When determining whether the to-be-tested chip meets the performance parameter of the preset reference chip, the shortest command reply time scatter plot of the to-be-tested chip under different power-off times and the shortest command reply time scatter plot of the reference chip under different power-off times can be fitted to obtain a fitted scatter plot of the shortest command reply time of the to-be-tested chip and the reference chip under different power-off times as shown in FIG. 6 (the horizontal axis represents the power-off time in ms, and the vertical axis represents the shortest command reply time in μs). Figure 16 Based on the fitted scatter plot, the difference between the shortest command reply time of the two chips under the same power-off time can be more intuitively observed, and the deviation of the shortest command reply time of the two chips under the same power-off time, i.e., the second difference value, can be specifically calculated. Figure 16

[0110] Since the second difference value has positive and negative values, for the purpose of comparison, the sum of squares of the second difference value can be calculated, and then the sum of squares is compared with the second preset threshold value to determine whether the to-be-tested chip and the preset reference chip are chips of different types. Moreover, the sum of squares of the second difference value corresponding to multiple power-off times can avoid the misjudgment caused by single-point test error, thereby further improving the accuracy of the chip detection.​

[0111] The following will be described in combination with Figure 16 and Figure 17 , taking the chip identification and detection of A manufacturer as an example, the process of detecting the chip based on the shortest command reply time of different power-off times will be described in detail. As shown in Figure 17 , the shortest command reply time (reference command reply time) of the reference chip of A manufacturer under different power-off times can be tested first. Then the shortest command reply time of the to-be-detected chip under different power-off times is tested, and the command reply time difference of the to-be-detected chip and the reference chip under multiple power-off times, that is, the second difference value, is calculated. Then the sum of the squares of the differences of multiple second difference values is calculated, for example, Figure 16 , the sum of the squares of the differences corresponding to each power-off time on the abscissa is obtained, that is, the sum of the squares of the differences. If the sum of the squares of the differences is less than or equal to the second preset threshold, it is determined that the to-be-detected chip belongs to the chip of A manufacturer, otherwise the to-be-detected chip does not belong to the chip of A manufacturer.

[0112] In summary, based on the above-mentioned preset detection circuit, after the to-be-detected chip is connected to the preset detection circuit, the command reply data of the to-be-detected chip under different parameter conditions can be detected, and then whether the to-be-detected chip meets the performance parameters of the preset reference chip is determined according to the detected command reply data and the corresponding reference data (that is, the preset reference data described below) of the preset reference chip. The performance (including but not limited to power consumption performance and diode performance) of the to-be-detected chip can be detected, so as to improve the yield of products and prevent the chip from being counterfeited (the chip with the same characteristic description and the preset reference chip belongs to the same manufacturer, and the chip without the same characteristic description and the preset reference chip does not belong to the same manufacturer).

[0113] Based on the same concept, the embodiment also provides a chip detection device based on a preset detection circuit, the preset detection circuit includes a chip interface, an upper pull resistor and a power supply interface connected in sequence, the chip interface is used to connect a to-be-detected chip, and the chip interface and the power supply interface are both connected to a single-chip microcomputer; the device includes:

[0114] a data acquisition module configured to acquire command reply data of the to-be-detected chip under different parameter conditions based on the preset detection circuit;

[0115] a result determination module configured to determine whether the to-be-detected chip meets performance parameters of a preset reference chip according to the command reply data and preset reference data; the preset reference data is command reply data of the preset reference chip obtained under the same parameter condition as the to-be-detected chip.

[0116] The chip detection device provided by the embodiment is based on the same concept as the chip detection method, so it can at least achieve the beneficial effects of the chip detection method, and any of the above embodiments can be applied to the chip detection device provided by the embodiment, and details are not repeated here.

[0117] The embodiments of the present application also provide an electronic device for executing the chip detection method described above. Please refer to Figure 18 which shows a schematic diagram of a power consuming device provided by some embodiments of the present application. As shown in Figure 18 the power consuming device 40 comprises a processor 400, a memory 401, a bus 402 and a communication interface 403, the processor 400, the communication interface 403 and the memory 401 are connected through the bus 402; the memory 401 stores a computer program which can be run on the processor 400, and the processor 400 executes the chip detection method provided by any of the preceding embodiments of the present application when running the computer program.

[0118] The memory 401 can include a high-speed random access memory (RAM: Random Access Memory) and can also include a non-volatile memory such as at least one disk memory. The communication connection between the device network element and at least one other network element is realized through at least one communication interface 403 (which can be wired or wireless), and the Internet, a wide area network, a local network, a metropolitan area network, etc. can be used.

[0119] The bus 402 can be an ISA bus, a PCI bus or an EISA bus, etc. The bus can be divided into an address bus, a data bus, a control bus, etc. The memory 401 is used to store programs, and the processor 400 executes the programs after receiving execution instructions. The chip detection method disclosed in any of the preceding embodiments of the present application can be applied to the processor 400 or realized by the processor 400.

[0120] The processor 400 can be an integrated circuit chip with a signal processing capability. In implementation, the steps of the above method can be completed by an integrated logic circuit or an instruction in the form of software in the processor 400. The processor 400 described above can be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), and the like; or can be a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components. The disclosed methods, steps and logic block diagrams in the embodiments of the present application can be implemented or executed. The general-purpose processor can be a microprocessor or the processor can also be any conventional processor. The steps of the method disclosed in combination with the embodiments of the present application can be directly embodied as a hardware code processor for execution, or a combination of hardware and software modules in the code processor for execution. The software module can be located in a random access memory, a flash memory, a read-only memory, a programmable read-only memory or an electrically erasable programmable memory, a register, and the like storage medium mature in the art. The storage medium is located in the memory 401, and the processor 400 reads the information in the memory 401, and combines the hardware to complete the steps of the above method.

[0121] The power consumption equipment provided by the embodiments of the present application and the chip detection method provided by the embodiments of the present application have the same beneficial effects as the method adopted, run or implemented.

[0122] The present application also provides a computer readable storage medium corresponding to the chip detection method provided by the preceding embodiments. Please refer to Figure 19 The computer readable storage medium shown is an optical disc 30, and a computer program (i.e. program product) is stored on the optical disc 30. When the computer program is run by a processor, the chip detection method provided by any of the preceding embodiments is executed.

[0123] It should be noted that examples of the computer readable storage medium can also include, but are not limited to, a phase change memory (PRAM), a static random access memory (SRAM), a dynamic random access memory (DRAM), other types of random access memory (RAM), a read-only memory (ROM), an electrically erasable programmable read-only memory (EEPROM), a flash memory or other optical, magnetic storage medium, which will not be described one by one here.

[0124] The computer readable storage medium provided by the above embodiments of the present application and the chip detection method provided by the embodiments of the present application have the same beneficial effects as the method adopted, run or implemented by the application program stored therein.

[0125] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, and are not intended to limit the present application; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that the technical solutions recorded in the foregoing embodiments can still be modified, or some or all of the technical features can be replaced by equivalents; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application, and they should be covered in the scope of the claims and the description of the present application. In particular, as long as there is no structural conflict, each technical feature mentioned in each embodiment can be combined in any way. The present application is not limited to the specific embodiments disclosed herein, but includes all technical solutions falling within the scope of the claims.

Claims

1. A chip detection method characterized by, The preset detection circuit comprises a chip interface, an upper pull resistor and a power supply interface connected in sequence, the chip interface is used for accessing a chip to be tested, and the chip interface and the power supply interface are connected with a single-chip microcomputer; the method comprises: Based on the preset detection circuit, the command reply data of the chip to be tested under different parameter conditions is obtained; According to the command reply data and preset reference data, it is determined whether the chip to be tested meets the performance parameters of the preset reference chip; the preset reference data at least comprises the command reply data of the preset reference chip under the same parameter conditions of the chip to be tested; The command reply data of the chip to be tested under different parameter conditions is obtained, comprising: The shortest interval time of the chip to be tested for different commands is obtained; According to the command reply data and preset reference data, it is determined whether the chip to be tested meets the performance parameters of the preset reference chip, comprising: According to the shortest interval time and preset reference data, the shortest interval time of the chip to be tested and the reference interval time of the preset reference chip under the condition of the same command are determined; According to the shortest interval time of the chip to be tested and the reference interval time, it is determined whether the chip to be tested meets the performance parameters of the preset reference chip; Before determining whether the chip to be tested meets the performance parameters of the preset reference chip according to the shortest interval time of the chip to be tested and the reference interval time, further comprising: A time setting step is arranged to set the interval time between the reading command data and the output command data of the preset reference chip; A command test step is arranged to start the chip detection and check whether the preset reference chip replies to the command within the interval time; A time determination step is arranged to, if yes, re-execute the time setting step, reduce the interval time, re-execute the command test step, until the preset reference chip does not reply to the command within the current interval time, and the interval time set last time is determined as the reference interval time of the preset reference chip for the reading command data; and If no, the time setting step is re-executed, the interval time is increased, the command test step is re-executed, until the preset reference chip replies to the command within the current interval time, and the interval time set last time is determined as the reference interval time of the preset reference chip for the reading command data.

2. The method of claim 1, wherein, According to the shortest interval time of the chip to be tested and the reference interval time, it is determined whether the chip to be tested meets the performance parameters of the preset reference chip, comprising: The first difference value of the shortest interval time of the chip to be tested and the reference interval time corresponding to each command is calculated; It is determined whether at least one first difference value is greater than a first preset threshold value; If no, it is determined that the chip to be tested meets the performance parameters of the preset reference chip; if yes, it is determined that the chip to be tested does not meet the performance parameters of the preset reference chip.

3. The method of claim 1, wherein, The command reply data of the chip to be tested under different parameter conditions is obtained, comprising: The shortest reply time of the to-be-tested chip receiving a command reply under different power-off times is obtained after the to-be-tested chip is powered on again.

4. The method of claim 3, wherein, According to the command reply data and preset reference data, whether the to-be-tested chip meets the performance parameter of the preset reference chip is determined, including: According to the shortest reply time and preset reference data, a to-be-tested command reply time of the to-be-tested chip and a reference command reply time of the preset reference chip under the same power-off time are determined. According to the to-be-tested command reply time and the reference command reply time, whether the to-be-tested chip meets the performance parameter of the preset reference chip is determined.

5. The method of claim 4, wherein, According to the to-be-tested command reply time and the reference command reply time, whether the to-be-tested chip meets the performance parameter of the preset reference chip is determined, including: A second difference value of the to-be-tested command reply time and the reference command reply time corresponding to each power-off time is calculated. According to the second difference value corresponding to each power-off time, whether the to-be-tested chip meets the performance parameter of the preset reference chip is determined.

6. The method of claim 5, wherein, According to the second difference value corresponding to each power-off time, whether the to-be-tested chip meets the performance parameter of the preset reference chip is determined, including: A difference value square sum is calculated according to the second difference value corresponding to each power-off time. Whether the difference value square sum is less than or equal to a second preset threshold value is determined. If yes, it is determined that the to-be-tested chip meets the performance parameter of the preset reference chip; if no, it is determined that the to-be-tested chip does not meet the performance parameter of the preset reference chip.

7. The method according to any one of claims 4-6, characterized in that, Before determining, according to the to-be-tested command reply time and the reference command reply time, whether the to-be-tested chip meets the performance parameter of the preset reference chip, the method further includes: A time setting step of setting a power-off time and a command reply time of a preset reference chip and powering the preset reference chip again after the power-off time; A command test step of controlling the chip to send command data to a single-chip microcomputer after the preset reference chip is powered for the command reply time, and determining whether the preset reference chip receives reply data of the single-chip microcomputer; A time determination step of, if yes, re-executing the time setting step, reducing the command reply time, re-executing the command test step, until the preset reference chip does not receive the reply data of the single-chip microcomputer, and determining the command reply time set last time as the reference command reply time of the preset reference chip under the current power-off time; and, If no, re-executing the time setting step, increasing the command reply time, re-executing the command test step, until the preset reference chip receives the reply data of the single-chip microcomputer, and determining the command reply time set currently as the reference command reply time of the preset reference chip under the current power-off time.

8. The method according to any one of claims 3-6, characterized in that, The power supply interface comprises a first interface, a second interface and a transistor, the first interface is used for connecting a single-chip microcomputer; the second interface is connected with a collector of the transistor, and a power supply is provided for the transistor; a base of the transistor is connected with the first interface, and an emitter of the transistor is connected with the pull-up resistor, so as to control the power-off time of the chip to be tested.

9. A chip testing apparatus characterized by comprising: Based on a preset detection circuit, the preset detection circuit comprises a chip interface, a pull-up resistor and a power supply interface connected in sequence, the chip interface is used for accessing a chip to be tested, and the chip interface and the power supply interface are both connected with a single-chip microcomputer; the device comprises: A data acquisition module is configured to acquire command reply data of the chip to be tested under different parameter conditions based on the preset detection circuit. The command reply data of the chip to be tested under different parameter conditions is acquired, including acquiring the shortest interval time of the chip to be tested for different commands. A result determination module is configured to determine whether the chip to be tested meets the performance parameters of the preset reference chip according to the command reply data and preset reference data; the preset reference data is command reply data of a preset reference chip obtained under the same parameter conditions as the chip to be tested. The command reply data and the preset reference data are used to determine whether the chip to be tested meets the performance parameters of the preset reference chip, including: determining the to-be-tested shortest interval time of the chip to be tested and the reference interval time of the preset reference chip under the same command according to the shortest interval time and the preset reference data; and determining whether the chip to be tested meets the performance parameters of the preset reference chip according to the to-be-tested shortest interval time and the reference interval time. Before determining whether the chip to be tested meets the performance parameters of the preset reference chip according to the to-be-tested shortest interval time and the reference interval time, the following steps are further included: A time setting step is configured to set an interval time between reading command data and outputting command data of the preset reference chip; a command test step is configured to start chip detection and check whether the preset reference chip performs command reply within the interval time; a time determination step is configured to, if yes, re-execute the time setting step, reduce the interval time, re-execute the command test step, until the preset reference chip does not perform command reply within the current interval time, and determine the interval time set last time as the reference interval time of the preset reference chip for the read command data; and, if no, re-execute the time setting step, increase the interval time, re-execute the command test step, until the preset reference chip performs command reply within the current interval time, and determine the interval time set currently as the reference interval time of the preset reference chip for the read command data.

10. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, The processor executes the computer program to implement the method of any one of claims 1-8.

11. A computer readable storage medium having stored thereon a computer program, characterized in that, The program is executed by the processor to implement the method of any one of claims 1-8.

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