SRAM in-memory computing chip based on capacitive coupling

Abstract

This invention provides a capacitively coupled SRAM in-memory computing chip, comprising: an input module, a bitwise multiplication module, a capacitor attenuation module, and an output module. The input module receives input data; the bitwise multiplication module performs multiplication operations between the input data and the stored data to obtain the multiplication result; and the capacitor attenuation module uses a hierarchical capacitor attenuator structure to accumulate the multiplication result layer by layer, which not only simplifies the structure but also shortens the computation time, allowing for rapid acquisition of the accumulated digital result, thus improving the energy efficiency and computational throughput of the multiplication and accumulation operation.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit design technology, and in particular to an SRAM in-memory computing chip based on capacitive coupling. Background Technology

[0002] Compute-In-Memory (CIM) technology refers to transforming the traditional compute-centric architecture into a data-centric architecture. It directly utilizes memory for data processing, thus integrating data storage and computation onto a single chip, forming a compute-in-memory chip. This can completely eliminate the bottleneck of the von Neumann architecture and reduce the additional power consumption and performance loss caused by data transmission. Static Random Access Memory (SRAM), due to its high speed, low power consumption, and high robustness, is widely used in constructing compute-in-memory chips.

[0003] Currently, in-memory computing chips can be used as hardware implementations of multiplication and accumulation operations in neural network models. However, existing in-memory computing chips typically employ charge-based CIM structures to achieve multi-bit data accumulation. In the analog domain, they use switch arrays and additional control signals to implement charge sharing circuits. This sharing control is complex and has a large delay, which greatly affects the computing performance of in-memory computing chips. Summary of the Invention

[0004] This invention provides an SRAM in-memory computing chip based on capacitive coupling to overcome the shortcomings of existing technologies.

[0005] This invention provides an SRAM in-memory computing chip based on capacitive coupling, comprising: an input module, a bitwise multiplication module, a capacitor attenuation module, and an output module, wherein the input module, the bitwise multiplication module, the capacitor attenuation module, and the output module are connected in sequence;

[0006] The input module is used to receive input data;

[0007] The bitwise multiplication module includes multiple bitwise multiplication units. Each bitwise multiplication unit is used to perform a multiplication operation on the input data and a bit of the stored data based on the capacitive coupling principle, so as to obtain the multiplication result corresponding to the bit of the stored data.

[0008] The capacitor attenuation module includes two layers of capacitor attenuator arrays. Each first-type capacitor attenuator in the first layer of the capacitor attenuator array is connected between two adjacent bit multiplication units, and each second-type capacitor attenuator in the second layer of the capacitor attenuator array is connected between two adjacent first-type capacitor attenuators. The capacitor attenuation module is used to accumulate the multiplication results corresponding to each bit of the stored data layer by layer to obtain a multi-bit data simulation accumulation result.

[0009] The output module is used to determine and output the digital accumulation result corresponding to the multi-bit data simulation accumulation result.

[0010] According to the present invention, an SRAM in-memory computing chip based on capacitive coupling is provided, wherein the input module includes an input sparsity sensing module and an input sparsity comparison module, and the input sparsity sensing module is connected to the bitwise multiplication module.

[0011] The output module includes a Flash analog-to-digital converter module, and the input sparsity sensing module, the input sparsity comparison module, and the Flash analog-to-digital converter module are connected in sequence.

[0012] The input sparse sensing module is used to convert the input data into analog voltage;

[0013] The input sparse comparison module is used to compare the analog voltage with the first reference voltage to obtain a first comparison result;

[0014] The Flash analog-to-digital converter module is used to compare the multi-bit data analog accumulation result with the second reference voltage based on the first comparison result to obtain a second comparison result, and use the second comparison result as the digital accumulation result.

[0015] According to the present invention, an SRAM in-memory computing chip based on capacitive coupling is provided, wherein the working modes of the SRAM in-memory computing chip include a storage operation mode and a computing operation mode.

[0016] In the storage operation mode, the input module and the output module are not working;

[0017] In the computing operation mode, the SRAM in-memory computing chip performs multiplication and accumulation operations on the input data and the stored data.

[0018] According to the present invention, an SRAM in-memory computing chip based on capacitive coupling is provided, wherein the input sparse comparison module includes a plurality of first comparators, the Flash analog-to-digital conversion module includes a plurality of Flash analog-to-digital conversion units, and each Flash analog-to-digital conversion unit includes a plurality of second comparators;

[0019] The first comparator and the second comparator are connected in a one-to-one correspondence, and the first reference voltage of each first comparator is the same as the second reference voltage of the corresponding connected second comparator.

[0020] According to the present invention, in a capacitor-coupled SRAM in-memory computing chip, the number of Flash analog-to-digital conversion units is the same as the number of the second type of capacitor attenuators.

[0021] According to the present invention, an SRAM in-memory computing chip based on capacitive coupling is provided, wherein the bit multiplication unit includes a column of 9T1C cell arrays, and the 9T1C cell array includes multiple 9T1C cells;

[0022] The SRAM in-memory computing chip also includes an external SRAM read / write structure, which is connected to the 9T1C unit.

[0023] According to the present invention, an SRAM in-memory computing chip based on capacitive coupling is provided, wherein the 9T1C unit includes six first-type transistors and three second-type transistors, and both the first-type transistors and the second-type transistors are connected to the external structure for reading and writing SRAM.

[0024] The six first-type transistors are used to store one bit of the stored data;

[0025] The three second-type transistors are used to perform a multiplication operation between one bit of the stored data stored in the six first-type transistors and the corresponding bit of the input data.

[0026] According to the present invention, an SRAM in-memory computing chip based on capacitive coupling is provided, wherein the SRAM read / write external structure includes an SRAM controller, SRAM peripheral circuits, and an address decoding driver.

[0027] The SRAM controller is connected to the SRAM peripheral circuit and the address decoding driver, respectively. The SRAM peripheral circuit and the address decoding driver are both connected to the 9T1C unit.

[0028] According to the present invention, an SRAM in-memory computing chip based on capacitive coupling is provided, the SRAM in-memory computing chip further includes an in-memory computing controller, the in-memory computing controller being connected to the input module and the output module respectively.

[0029] According to the present invention, an SRAM in-memory computing chip based on capacitive coupling is provided, wherein the stored data includes multiple 4-bit weight data in a neural network.

[0030] The present invention provides a capacitively coupled SRAM in-memory computing chip, comprising: an input module, a bitwise multiplication module, a capacitor attenuation module, and an output module. The input module receives input data; the bitwise multiplication module performs multiplication operations between the input data and the stored data to obtain the multiplication result; and the capacitor attenuation module uses a hierarchical capacitor attenuator structure to accumulate the multiplication result layer by layer, which not only simplifies the structure but also shortens the calculation time, allowing for rapid acquisition of the accumulated digital result, thus improving the energy efficiency and computational throughput of the multiplication and accumulation operation. Attached Figure Description

[0031] To more clearly illustrate the technical solutions in this invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, those skilled in the art can obtain other drawings based on the drawings described below without creative effort.

[0032] Figure 1 This is one of the structural schematic diagrams of the SRAM in-memory computing chip based on capacitive coupling provided by the present invention;

[0033] Figure 2 This is a schematic diagram of the 4b-DAC structure in the SRAM in-memory computing chip based on capacitive coupling provided by the present invention;

[0034] Figure 3 This is a schematic diagram showing the connection between the DAC array, the input sparse sensing module, and the bitwise multiplication module in the SRAM in-memory computing chip based on capacitive coupling provided by the present invention.

[0035] Figure 4 This is a schematic diagram of the structure of each bit multiplication unit in the SRAM in-memory computing chip based on capacitive coupling provided by the present invention;

[0036] Figure 5 This is the timing diagram of the multiplication operation of the 9T1C unit in the SRAM in-memory computing chip based on capacitive coupling provided by the present invention.

[0037] Figure 6 This is a schematic diagram showing the connection between the bit-multiplication module and the capacitor attenuation module in the bit-multiplication module of the capacitively coupled SRAM in-memory computing chip provided by this invention, where each bit multiplication unit includes a column of 9T1C unit arrays.

[0038] Figure 7 This is the layout of the 9T1C cell and HCA column in the SRAM in-memory computing chip based on capacitive coupling provided by the present invention;

[0039] Figure 8 This is the second schematic diagram of the structure of the SRAM in-memory computing chip based on capacitive coupling provided by the present invention;

[0040] Figure 9 This is the timing diagram of the MAC operation with input sparsity awareness of the SRAM in-memory computing chip based on capacitive coupling provided by the present invention.

[0041] Figure 10 This is a Monte Carlo simulation diagram of the transfer function, linear fitting results, and process fluctuations of the capacitively coupled SRAM in-memory computing chip provided by this invention under different temperatures and process angles. Detailed Implementation

[0042] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.

[0043] Neural networks have been widely applied and achieved excellent performance in fields such as pattern recognition, automatic control, financial analysis, and biomedicine. Convolutional neural networks (CNNs), as the most widely used type of artificial neural network, are particularly outstanding in image processing. However, as the complexity of tasks increases, the size of neural networks continues to grow, and the number of parameters and computational loads in the network also increase. This means that the resources and power consumption of neural networks on hardware are increasing day by day. The most critical and largest operation in CNNs is the multiply-accumulate (MAC) operation. Therefore, the key to implementing a low-power CNN lies in the design of a low-power MAC operation unit.

[0044] Compute-In-Memory (CIM) technology aims to transform the traditional compute-centric architecture into a data-centric architecture. It directly utilizes memory for data processing, thus integrating data storage and computation onto a single chip. This completely eliminates the bottlenecks of the von Neumann architecture and is particularly suitable for large-scale parallel applications such as Deep Convolution Neural Networks (DCNNs). Because the storage and computation units are integrated, this system architecture not only retains the storage and read / write functions of the storage circuitry itself but also supports different logical or multiply-accumulate operations. This significantly reduces frequent bus interactions between the CPU and memory circuitry, further reducing the amount of data movement. It enables massively parallel computation with ultra-low power consumption, greatly improving system energy efficiency and representing a highly promising research direction for achieving high-energy-efficiency computing in artificial intelligence applications.

[0045] Previous CIM architectures offered significant advantages in energy efficiency and throughput compared to traditional von Neumann architectures. Existing SRAM-CIMs implement MAC operations via transistor current. However, current-based computation suffers from poor nonlinearity and fluctuations, leading to a significant decrease in the accuracy of DCNNs. Charge-domain-based CIMs, on the other hand, exhibit better nonlinearity and accuracy due to smaller capacitor mismatches and process variations. Nevertheless, charge-domain-based CIMs still face several challenges, including:

[0046] First, the design of storage and computing units for dot product needs to make trade-offs between the number of transistors, their size, and the dynamic range of computation. For example, using an 8T1C unit results in fewer transistors, but there will be a threshold loss in the dynamic range. On the other hand, using a 10T1C unit can achieve rail-to-rail dynamic range, but its storage and computing units are larger.

[0047] Second, in order to achieve multi-bit weight accumulation, charge domain-based CIM uses a switch array and additional control signals to implement a charge sharing circuit in the analog domain, or uses shifter groups and adder groups in the digital domain. The former has complex shared control and large delay, while the latter has high power consumption and large area.

[0048] Third, the analog-to-digital converter (ADC) that converts the results of analog MAC operations into digital codes consumes a lot of energy, which seriously affects the overall energy efficiency.

[0049] In other words, existing in-memory computing chips, when implementing multi-bit data accumulation, suffer from problems such as complex shared control, large latency, reduced computing performance, and decreased energy efficiency due to the use of switch arrays and additional control signals in the analog domain to achieve charge sharing circuitry. Therefore, there is an urgent need to provide a capacitively coupled SRAM-based in-memory computing chip to solve the problems encountered during multi-bit data accumulation.

[0050] Figure 1 This is a schematic diagram of the structure of an SRAM-based in-memory computing chip provided in an embodiment of the present invention, as shown below. Figure 1 As shown, the chip includes: an input module 1, a bitwise multiplication module 2, a capacitor attenuation module 3, and an output module 4;

[0051] The input module 1, the bitwise multiplication module 2, the capacitor attenuation module 3, and the output module 4 are connected in sequence;

[0052] The input module 1 is used to receive input data;

[0053] The bitwise multiplication module 2 includes multiple bitwise multiplication units 21. Each bitwise multiplication unit is used to perform a multiplication operation on the input data and a bit of the stored data based on the capacitive coupling principle, so as to obtain the multiplication result corresponding to the bit of the stored data.

[0054] The capacitor attenuation module 3 includes two layers of capacitor attenuator arrays. Each first type of capacitor attenuator 311 in the first layer of capacitor attenuator array 31 is connected between two adjacent bit multiplication units 21. Each second type of capacitor attenuator 321 in the second layer of capacitor attenuator array 32 is connected between two adjacent first type of capacitor attenuators 311.

[0055] The capacitor attenuation module 3 is used to accumulate the multiplication results corresponding to each bit of the stored data layer by layer to obtain a multi-bit data simulation accumulation result.

[0056] The output module 4 is used to determine and output the digital accumulation result corresponding to the multi-bit data simulation accumulation result.

[0057] Specifically, the SRAM in-memory computing chip based on capacitive coupling provided in this embodiment of the invention includes an input module 1 that can include a digital-to-analog converter (DAC) array to receive input data. The DAC array can include multiple DACs, and the number of bits in each DAC can be determined based on the number of bits of a single stored data in each bit multiplication unit and the number of bits of a single input data. These three can be consistent, for example, all can be 4 bits (i.e., 4b). In this case, the DAC array can include multiple 4b-DACs, each of which can be used to receive one 4b of input data. The number of 4b-DACs included in the DAC array can be set as needed, for example, it can be set to 128.

[0058] Each 4b-DAC structure can be like this: Figure 2 As shown, each 4-bit DAC is driven by an off-chip external bias. Considering the difficulty and accuracy of voltage reference design in chip design, for ease of design, the off-chip bias in this embodiment provides 16 driving voltages for each 4-bit DAC, with a gradient from GND to 1 / 16 of VDD. On the chip, this primarily implements a 4-to-16 decoder function. A 4-bit input data (4-bit Input) is input into a 4-bit DAC to obtain the decoded result (DAC-OUT).

[0059] The bitwise multiplication module 2 may include multiple bitwise multiplication units 21. The number of bitwise multiplication units 21 in the bitwise multiplication module 2 can be set as needed, for example, it can be set to 64, that is, the bitwise multiplication module 2 can perform bitwise multiplication operations between 64 4-bit stored data and input data. Each bitwise multiplication unit 21 may include a calculation unit with the same number of DACs in the DAC array, so that the DACs and calculation units are connected in a one-to-one correspondence. Each calculation unit can store the corresponding bit of stored data (i.e., 1-bit stored data).

[0060] Each computing unit includes a capacitor, which, through capacitive coupling, enables multiplication between the decoded result of the connected DAC output and the corresponding stored bit data. Each bit multiplication unit can perform multiplication of all input data with one bit of stored data, obtaining the multiplication result corresponding to that one bit of stored data. Therefore, four adjacent bit multiplication units can jointly perform multiplication of all input data with a 4-bit stored data.

[0061] In this embodiment of the invention, the capacitor attenuation module 3 includes two layers of capacitor attenuator (CA) arrays. Each first type of capacitor attenuator 311 in the first layer of capacitor attenuator array 31 is connected between two adjacent bit multiplication units 21, and each second type of capacitor attenuator 321 in the second layer of capacitor attenuator array 32 is connected between two adjacent first type of capacitor attenuators 311.

[0062] The attenuation coefficients of the first type of capacitor attenuator 311 and the second type of capacitor attenuator 321 can be determined according to the proportion of each bit of stored data. For example, the attenuation coefficient of the first type of capacitor attenuator 311 can be AC ​​= 0.5, in which case the first type of capacitor attenuator 311 is 1 / 2CA. The attenuation coefficient of the second type of capacitor attenuator 321 can be AC ​​= 0.25, in which case the second type of capacitor attenuator 321 is 1 / 4CA.

[0063] Through the structure of capacitor attenuation module 3, the multiplication results corresponding to each bit of stored data can be accumulated layer by layer to obtain the multi-bit data simulation accumulation result of each stored data.

[0064] The two first-type capacitor attenuators 311 and one second-type capacitor attenuator 321 corresponding to the four adjacent bit-multiplication units can form a hierarchical capacitor attenuator (HCA) structure. Therefore, the capacitor attenuator module 3 connected to the bit-multiplication module 2 can include a total of 64 HCA structures, realizing the accumulation of the bit-multiplication results of 64 4-bit stored data and input data.

[0065] Compared to the accumulation method based on capacitor sharing using weighted capacitor arrays and compensation capacitor arrays, the HCA structure does not employ a switch array for temporary storage of analog data and charge sharing. Therefore, the HCA structure is simpler.

[0066] Furthermore, in this embodiment of the invention, the capacitor attenuation module 3 can be driven by a strong external voltage to achieve stable voltage output. Compared with the weight accumulation mode based on capacitor sharing, which achieves steady-state voltage output through weak internal voltage rebalancing, the calculation time for obtaining the multi-bit data simulation accumulation result is shorter.

[0067] The output module 4 in the chip may include multiple analog-to-digital converters (ADCs). The number of bits in each ADC can be determined based on the number of bits of a single stored data in each bit multiplication unit, for example, all of them can be 4 bits. In this case, the output module 4 may include multiple 4-bit ADCs, each of which is connected to an HCA structure to convert the analog accumulation result of the multi-bit data corresponding to each stored data into a digital accumulation result, and then output the digital accumulation result.

[0068] The SRAM in-memory computing chip based on capacitive coupling provided in this embodiment of the invention includes: an input module, a bitwise multiplication module, a capacitor attenuation module, and an output module. The input module receives input data; the bitwise multiplication module performs multiplication operations between the input data and the stored data to obtain the multiplication result; and the capacitor attenuation module uses a hierarchical capacitor attenuator structure to accumulate the multiplication result layer by layer, which not only simplifies the structure but also shortens the calculation time, allowing for rapid acquisition of the numerical accumulation result, thus improving the energy efficiency and computational throughput of the multiplication accumulation operation.

[0069] Based on the above embodiments, the SRAM in-memory computing chip based on capacitive coupling provided in this embodiment of the invention includes an input sparsity sensing module and an input sparsity comparison module, wherein the input sparsity sensing module is connected to the bitwise multiplication module.

[0070] The output module includes a Flash analog-to-digital converter module, and the input sparsity sensing module, the input sparsity comparison module, and the Flash analog-to-digital converter module are connected in sequence.

[0071] The input sparse sensing module is used to convert the input data into analog voltage;

[0072] The input sparse comparison module is used to compare the analog voltage with the first reference voltage to obtain a first comparison result;

[0073] The Flash analog-to-digital converter module is used to compare the multi-bit data analog accumulation result with the second reference voltage based on the first comparison result to obtain a second comparison result, and use the second comparison result as the digital accumulation result.

[0074] Specifically, in this embodiment of the invention, the input module may include, in addition to the DAC array, an input sparsity sensing module and an input sparsity comparison module, and the DAC array, the input sparsity sensing module, and the bitwise multiplication module are connected. For example... Figure 3As shown, the decoding result obtained by each DAC in the DAC array can be represented as IA[i], 0≤i≤N-1, where N is the number of DACs in the DAC array, which can be 128. It can be understood that regardless of whether the input module contains an input sparsity sensing module and an input sparsity comparison module, IA[i] can be input to the bit multiplication unit for multiplication operations.

[0075] The input sparse sensing module can be an IS-DAC (Input Sparsity Sensing DAC), which can include an NMOS11 and multiple sensing branches. The sensing branches are connected one-to-one with the DACs in the DAC array. The IS-DAC can include one NMOS and 128 sensing branches. The NMOS is responsible for discharging. The source of the NMOS can be grounded, and the gate of the NMOS can receive an external reset signal (RST_IS).

[0076] Each sensing branch includes a switch 12 and a capacitor 13. The DAC, switch 12, and capacitor 13 are connected sequentially. The IS-DAC can include a switch array consisting of 128 switches and a capacitor array consisting of 128 capacitors. The other plate of all capacitors is connected to the collector of the NMOS and the input sparsity comparator module, respectively. The switch array can receive an external gate connection control signal (IS-Eval). The IS-DAC combines the control signal of the switch array and converts all IA[i] into an analog voltage V representing the input sparsity through capacitive coupling via the capacitor array. IS .

[0077] The input sparse comparison module may include an input sparse comparator array (IS-CA), comprising multiple first comparators. The number of first comparators can be set as needed, for example, it may include 15. The IS-CA is controlled by an external enable signal (IS_SA_EN). The inverting terminal of each first comparator is connected to a first reference voltage Vref[j], 0≤j≤M-1, where M is the number of comparators in the IS-CA, which can be 15.

[0078] In IS-CA, each first comparator can simulate voltage V. IS The first comparison result is obtained by comparing it with the first reference voltage Vref[j], which is the 1b thermometer code DR[j]. The IS-CA can then output the 15b thermometer code DR<0:14>.

[0079] The output module may include a Flash analog-to-digital converter (ADC) module, which may contain multiple Flash analog-to-digital converter units (Flash-ADs). Each Flash-AD can be a 4-bit ADC, therefore the Flash ADC module can be viewed as a 4-bit Flash-AD array. The number of Flash-ADs in the Flash ADC module can be the same as the amount of data stored; that is, the Flash ADC module may contain a total of 64 Flash-ADs, which can be denoted as Flash-AD. <k>, 0≤k≤K-1, where K is the number of Flash-ADs in the Flash analog-to-digital converter module, which can be 64.

[0080] Each Flash-AD can include multiple second comparators, and each second comparator in the Flash-AD is connected to a first comparator in the IS-CA in a one-to-one correspondence. Therefore, each Flash-AD can have up to 15 comparators. Each second comparator in the Flash-AD has a second reference voltage. Based on the first comparison result of the corresponding first comparator, the second comparator in the Flash-AD can compare the multi-bit data analog accumulation result with the second reference voltage to obtain a second comparison result, and output the second comparison result as the digital accumulation result corresponding to the multi-bit data analog accumulation result.

[0081] Both the first comparator in the IS-CA and the second comparator in the Flash-AD are strong-arm comparators. In the IS-CA, the first comparator's first reference voltage increases from low to high, arranged in order of increasing distance from the IS-DAC. Similarly, in the Flash-AD, the second comparator's second reference voltage increases from low to high, arranged in order of increasing distance from the IS-DAC to the first comparator in the connected IS-CA.

[0082] Therefore, in each Flash-AD, the first second comparator can be represented as L-Comp. <0> The corresponding second reference voltage ranges from 0 to 400mV. The last second comparator can be represented as H-Comp. <14> The corresponding second reference voltage ranges from 400 to 900 mV.

[0083] In this embodiment of the invention, a combination of an input sparsity sensing module, an input sparsity comparison module, and a Flash analog-to-digital converter module can achieve high throughput for the chip. The Flash analog-to-digital converter module has a rail-to-rail decoding range. Since the entire dynamic range is rarely reached in MAC operations, especially when the input data is sparse, an input sparsity sensing strategy based on the real-time sensing of input sparsity characteristics by the input sparsity sensing module is used for decoding in the Flash analog-to-digital converter module to reduce the number of comparisons, thereby reducing energy consumption. This strategy estimates and quantizes the sum of 128 4-bit input data without considering stored data, and based on the quantization result, allows redundant comparator operations to be skipped.

[0084] Based on the above embodiments, the SRAM in-memory computing chip based on capacitive coupling provided in the embodiments of the present invention includes a storage operation mode and a computing operation mode.

[0085] In the storage operation mode, the input module and the output module are not working;

[0086] In the computing operation mode, the SRAM in-memory computing chip performs multiplication and accumulation operations on the input data and the stored data.

[0087] Specifically, in this embodiment of the invention, the SRAM in-memory computing chip can have two operating modes: Storage Operation (SRAM) mode and Computation Operation (CIM) mode. Storage Operation mode refers to the operation mode of storing data bit by bit into the SRAM in-memory computing chip, and the storage location can be a bit multiplication unit. Computation Operation mode refers to the operation mode of performing calculations between the input data and the stored data.

[0088] In storage operation mode, neither the input module nor the output module works.

[0089] In computational operation mode, all modules in the SRAM in-memory computing chip are working, performing multiplication and accumulation operations on the input data and the stored data.

[0090] Based on the above embodiments, the SRAM in-memory computing chip based on capacitive coupling provided in this embodiment of the invention includes an input sparse comparison module comprising multiple first comparators, a Flash analog-to-digital conversion module comprising multiple Flash analog-to-digital conversion units, and each Flash analog-to-digital conversion unit comprising multiple second comparators;

[0091] The first comparator and the second comparator are connected in a one-to-one correspondence, and the first reference voltage of each first comparator is the same as the second reference voltage of the corresponding connected second comparator.

[0092] Specifically, in this embodiment of the invention, the first reference voltage of the first comparator and the second reference voltage of the connected second comparator can be the same. This ensures that the working state of the second comparator can be accurately determined by the input sparsity, thereby improving the accuracy of the output result while reducing the number of working second comparators.

[0093] Based on the above embodiments, the SRAM in-memory computing chip based on capacitive coupling provided in this embodiment of the invention has the same number of Flash analog-to-digital conversion units as the second type of capacitor attenuators.

[0094] Specifically, in this embodiment of the invention, the number of Flash-ADs is the same as the number of second-type capacitor attenuators, and they can be connected one-to-one. This ensures that each Flash analog-to-digital conversion unit can determine and output the digital accumulation result corresponding to a 4-bit stored data.

[0095] Based on the above embodiments, the SRAM in-memory computing chip based on capacitive coupling provided in this embodiment of the invention allows the input sparsity sensing module to convert 128 4-bit input data into an analog voltage V representing the input sparsity through capacitive coupling. IS Then IS-CA will V IS The first comparison is performed with the first reference voltage of the first comparator. The first comparison result is a 15-bit thermometer code DR[0:14], representing the quantized input sparsity. The thermometer code DR[0:14] determines the operating state of the 15 second comparators and the second comparison result in each Flash-AD during the readout phase.

[0096] The control logic of the second comparator is as follows: when the thermometer code DR[i] = 0, the corresponding second comparator Comp... The comparison will be skipped, and its result will be set to 0. When the thermometer code DR[i] = 1, its corresponding second comparator Comp... It will work normally and produce output.

[0097] Based on the above embodiments, the SRAM in-memory computing chip based on capacitive coupling provided in this embodiment of the invention includes a bit multiplication unit comprising a column of 9T1C unit arrays, wherein the 9T1C unit array comprises multiple 9T1C units.

[0098] The SRAM in-memory computing chip also includes an external SRAM read / write structure, which is connected to the 9T1C unit.

[0099] Specifically, in this embodiment of the invention, each bit multiplication unit may include a column of 9T1C unit arrays, and each 9T1C unit array includes multiple 9T1C units. Each 9T1C unit is a computing unit, containing 9 transistors T and 1 capacitor (C). bitcell Storage and multiplication operations are achieved through 9T, and the multiplication results are accumulated on the upper plate of the capacitor through the capacitive coupling principle of the capacitor.

[0100] The SRAM in-memory computing chip may also include an external SRAM read / write structure, which can be connected to each 9T1C cell via word line WL and bit line BL / BLB to drive and control each 9T1C.

[0101] In this embodiment of the invention, a 9T1C cell array is used as a bit multiplication unit to realize the multiplication operation between the stored data bit and the input data. Compared with the 8T1C and 10T1C in the prior art, it balances the number of transistors and the dynamic range, and improves the chip performance.

[0102] Based on the above embodiments, the SRAM in-memory computing chip based on capacitive coupling provided in this embodiment of the invention includes a 9T1C unit comprising six first-type transistors and three second-type transistors, wherein both the first-type transistors and the second-type transistors are connected to the external structure for reading and writing SRAM.

[0103] The six first-type transistors are used to store one bit of the stored data;

[0104] The three second-type transistors are used to perform a multiplication operation between one bit of the stored data stored in the six first-type transistors and the corresponding bit of the input data.

[0105] Specifically, such as Figure 4 As shown, each bit multiplication unit may include a column of 9T1C cell arrays, each 9T1C cell array comprising multiple 9T1C cells, each 9T1C cell being used to store one bit of data. The number of 9T1C cells in each 9T1C cell array may be the same as the number of input data, for example, both may be 128.

[0106] The input to each 9T1C unit is IA[i]. Within each 9T1C unit, the input line IA[i] divides the nine transistors T into an upper 6T and a lower 3T. The upper 6T can be first-type transistors, mainly used for storing one bit of data. The lower 3T can be second-type transistors, used for multiplication operations between the input data and the one bit of data stored in the upper 6T.

[0107] In 6T, there are nodes Q and QB, and the input data is stored in node Q in the form of voltage. In 3T, the first T and the second T are connected in parallel and then in series with the third T. QB[i] and Q[i] are the voltages on the lines connected to the gates of the first T and the second T, respectively. In each 9T1C cell, the capacitor C is connected in parallel with the third T. The voltage on the upper plate of capacitor C can be represented as Mult[i], which can be used to characterize the product of IA[i] and one bit of data stored at point Q.

[0108] Figure 4 In this architecture, each 9T1C cell is connected to a word line WL[i] and bit lines BL and BLB. Each 9T1C cell also contains a compute line CL. A reset switch is connected to the compute line CL. When the switch is turned on, the corresponding compute line can receive a reset signal (RST_MAC).

[0109] The truth table for each 9T1C unit is shown in Table 1, and the correspondence between 4b Input and IA is shown in Table 2.

[0110] Table 1. Truth table of operation for the 9T1C unit.

[0111]

[0112] Table 2.4b Correspondence between Input and IA

[0113] 4b Input IA 4b Input IA 0000 GND 1000 8 / 15 VDD 0001 1 / 15 VDD 1001 9 / 15 VDD 0010 2 / 15 VDD 1010 10 / 15 VDD 0011 3 / 15 VDD 1011 11 / 15 VDD 0100 4 / 15 VDD 1100 12 / 15 VDD 0101 5 / 15 VDD 1101 13 / 15 VDD 0110 6 / 15 VDD 1110 14 / 15 VDD 0111 7 / 15 VDD 1111 VDD

[0114] As can be seen from Tables 1 and 2, the 9T1C unit has a rail-to-rail dynamic range greater than that of the 8T1C design. The capacitors used are ~1.33f MOM capacitors, which can be placed above the 9T transistors during chip fabrication with a small area overhead. 1b of the 4b stored data is stored in each 9T1C unit, and the 4b input data is applied as an analog voltage generated by the 4b-DAC on the input line IA[0:127] to drive the upper plate Mult[i] of all capacitors with a data value of 1 in the corresponding row.

[0115] The multiplication operation of the 9T1C unit can include two stages: reset and output evaluation, such as... Figure 5 As shown. The multiplication operation of the 9T1C cell begins by resetting the upper base plate of capacitor C to GND. There are two reset methods here. If Q=0, the transistor T connected to QB turns on and pulls the computation line (CL) low to GND. If Q=1, the transmission gate turns on and pulls CL low to IA, i.e., GND during the reset phase. After reset, an analog voltage is applied to IA. The analog voltage can only be transmitted to node Mult if and only if Q=1. Multiple stored data are stored in multiple 9T1C cells in the 9T1C cell array. Multiple 9T1C cells perform multiplication operations in parallel, and multiple input data are applied as driving voltages to IA during the evaluation phase. Based on the capacitive coupling principle, the generated voltage V_CL is proportional to the bitwise MAC operation result of the 1b data and 4b input data of the stored data.

[0116] Based on the above embodiments, the SRAM in-memory computing chip based on capacitive coupling provided in this embodiment of the invention... Figure 6 This diagram illustrates the connection between the bit-multiplication module and the capacitor attenuation module when each bit-multiplication unit in the bit-multiplication module comprises a column of 9T1C unit arrays.

[0117] Figure 6 The diagram shows only the four adjacent bit multiplication units corresponding to a 4b storage data and two first-class capacitor attenuators in the first-layer capacitor attenuator array and one second-class capacitor attenuator in the second-layer capacitor attenuator array of an HCA structure. The four bits of the 4b storage data are represented as W[0], W[1], W[2], and W[3], and each bit corresponds to a calculation line, which are CL[0], CL[1], CL[2], and CL[3], respectively.

[0118] The two first-class capacitor attenuators are Cw01 and Cw02, and the second-class capacitor attenuator is Cw01 / 23. Cw01 is connected to CL[0] and CL[1] respectively, Cw02 is connected to CL[2] and CL[3] respectively, and Cw01 / 23 is connected to CL[1] and CL[3] respectively.

[0119] like Figure 6 As shown, the results of multiplication of 128 4b IAs with 4 1b data points stored in one data storage unit are stored in CL[3], CL[2], CL[1], and CL[0], respectively. The attenuation coefficient AC = 0.5 for the two first-class capacitor attenuators in the HCA result can be determined by calculating the sum of the data pairs W[0] (W[2]) and W[1] (W[3]), and the attenuation coefficient AC = 0.25 for one second-class capacitor attenuator can be determined by calculating the sum of the data pairs W[0:1] and W[2:3]. The above calculation process determines the attenuation coefficient AC of each capacitor attenuator according to the proportion of one bit of data, and this process is hierarchical.

[0120] By calculating the capacitance contribution of each branch CL[0], CL[1], CL[2], and CL[3] as seen from the output point, which satisfies a ratio of 1:2:4:8, the relevant capacitance values ​​can be determined as follows:

[0121] C w01 =C w23 =128C bitcell

[0122] C w01 / 23 =64C bitcell

[0123] The multiplication operation of the 9T1C unit can include a reset phase and an evaluation phase. In the reset phase, the upper and lower plates of the first type of capacitor attenuator and the second type of capacitor attenuator are discharged to GND. In the evaluation phase, all 4-bit input data are input to the 9T1C unit array via a 4-bit DAC, clamping the upper plates of the capacitors in the 9T1C units to a fixed voltage generated by the 4-bit DAC. Then, when the coupled capacitor array consisting of all the capacitors in the 9T1C units in the four-bit multiplication units and the capacitor attenuators in the HCA structure reaches a steady state again, the output voltage V of the HCA structure, representing the calculation result, is... HCA And so it was produced. V HCA It will be quantized by the 4-bit Flash analog-to-digital converter module, outputting a 4-bit calculation result. Ideally, without considering parasitic capacitance, V HCA It can be calculated using the following formula:

[0124]

[0125] Among them, IA i This is the input on the i-th line, w i,j It is a single bit of data stored in the i-th row and j-th column, which is either 0 or 1. max,i For the maximum input value, IA is 4 bits of input data. max,i It is 15.

[0126] Based on the above embodiments, the SRAM in-memory computing chip based on capacitive coupling provided in this embodiment of the invention has a transistor area of ​​0.7um × 1.42um for the 9T1C unit and an MOM capacitor area of ​​0.55um × 1.42um for the 1.33fF.

[0127] Figure 7 The layout for 9T1C cells and HCA columns, including four 9T1C cells and one HCA structure, shows the implementation layout of a multiplication and accumulation of 4b weighted data. Considering layout symmetry and matching, the following three improvements are made: First, the C in the HCA structure... w0 / C w23 and C w0 / 23 The capacitors were divided into 128 and 64 unit capacitors C at the 9T1C unit level, respectively. bitcell These small unit capacitors are distributed throughout the layout of the bitwise multiplication module while maintaining a preset ratio. Therefore, for each row, the seven small capacitors of the 9T1C unit level with different functions are distributed in the layout of the transistor level of the four 9T1C units. Second, the positions of columns W[2] and W[3] are swapped, so that the column layout from left to right becomes W[0], W[1], W[3] and W[2], realizing a centrally symmetrical layout, so that the simulation calculation mismatch between W[0:1] and W[2:3] can be minimized. Third, 64 virtual capacitors and 64 C are introduced. w01 / 23 The small capacitors are arranged in an interwoven pattern, which can maximize the symmetry of the capacitor array layout and minimize the impact of random mismatch.

[0128] Figure 7 In the above, A represents a unit capacitance C. bitcell B are all type I capacitor attenuators, C are all virtual capacitors, and D are all type II capacitor attenuators.

[0129] Based on the above embodiments, the SRAM in-memory computing chip based on capacitive coupling provided in this embodiment of the invention may include an SRAM controller, SRAM peripheral circuits, and an address decoder and driver.

[0130] The SRAM read / write external structure allows the SRAM controller to be connected to both the SRAM peripheral circuitry and the address decoding driver, enabling global control of the chip's storage function. Both the SRAM peripheral circuitry and the address decoding driver are connected to the 9T1C cells to ensure that data is stored bit-by-bit in each 9T1C cell.

[0131] In this embodiment of the invention, the chip storage function can be automated through an SRAM controller.

[0132] Based on the above embodiments, the SRAM in-memory computing chip provided in this embodiment of the invention may further include an in-memory computing controller (CIM Controller), which can be connected to both the input module and the output module. The in-memory computing controller enables global control of the chip's computing functions.

[0133] Based on the above embodiments, the SRAM in-memory computing chip based on capacitive coupling provided in this embodiment of the invention stores multiple 4-bit weight data from a neural network.

[0134] Specifically, in this embodiment of the invention, the neural network typically includes a large amount of 4-bit weight data, which can be stored bit by bit in the bit multiplication unit of the chip as storage data, and then multiplied and accumulated with the input data of the neural network, thereby realizing the function of the convolution kernel in the neural network.

[0135] Figure 8 This is a complete structural diagram of the capacitively coupled SRAM in-memory computing chip provided in this embodiment of the invention. This chip can meet the requirement of 128 operations per convolutional kernel in a neural network. The chip includes a 128×256 9T1C cell array, an SRAM controller, SRAM peripheral circuitry, an address decoder driver, a CIM controller, 128 4b-DACs, IS-DACs, IS-CAs, a capacitor attenuation module containing 1×64 HCAs, and a Flash analog-to-digital converter module containing 1×64 4b-ADCs. The 9T1C cell array has a size of 128×256, and the chip's storage capacity is 32kb. The 256 columns of the 9T1C cell array are divided into 64 groups, with each group containing 4 columns, used to store 4b weight data.

[0136] In SRAM mode, the 4b-DAC, IS-DAC, IS-CA, and 4b-ADC are all inactive. At this time, the chip acts as a 6T-SRAM memory, performing normal read and write operations. In this mode, the weight data of the neural network is written into the SRAM. In CIM mode, the chip performs 4b MAC operations in complete parallel. Within a single cycle, all rows receive 4b input data. The chip can support a total of 128 4b input data, which can be represented as IN[0][0:3], IN[1][0:3], ..., IN

[127] [0:3]. The input data, after passing through the corresponding 4b-DAC, yields the corresponding decoding results IA[0], IA[1], ..., IA

[127] .

[0137] The MAC operation is performed in the analog domain using capacitive coupling, involving 128 input data points and 64 vector matrix multiplications with 128×4b weights. A Flash analog-to-digital converter (ADC) module converts the analog voltage representing the MAC operation result into a 4b digital code output. Alternatively, for calculations with even higher bit widths, serial input computation combined with a shift accumulator can be used.

[0138] The SRAM peripheral circuitry provides bit lines BL / BLB for each 9T1C cell in the 9T1C cell array, and the address decoding driver provides word lines WL for each 9T1C cell.

[0139] A switch controlled by the CIM controller is also connected between the 9T1C unit array and the capacitor attenuation module. This switch can be grounded to achieve the reset (RST) of the corresponding calculation line CL[i].

[0140] like Figure 9 The diagram shows the timing sequence of a MAC operation with input sparsity awareness, where the input module includes an input sparsity awareness module and an input sparsity comparison module, and the output module includes a Flash analog-to-digital converter module. Figure 9 As can be seen, the timing of MAC operation with input sparsity sensing is divided into two independent processes, Input Sparsity Sensing (IS) and MAC operation, which are interconnected through the thermometer code DR[0:14]. The IS process is divided into two processes: Reset (Reset_IS) and Output Evaluation (Evaluation_IS). The MAC operation process is also divided into two processes: Reset (Reset_MAC) and Output Evaluation (Evaluation_MAC). CLK is the chip's operating clock, which generates RST_IS and EVAL_IS (i.e., ...) through the timing control module. Figure 2 IS-Eval in (i.e., SA_EN_IS) Figure 3 The signals in the IS-DAC are: IS_SA_EN, RST_MAC, EVAL_MAC (representing the gate connection control signal of the switch in the sensing branch during MAC operation), and SA_EN_MAC (representing the enable signal of IS-DAC during MAC operation). RST_IS and EVAL_IS, and RST_MAC and EVAL_MAC are two inverted signals. SA_EN_IS and SA_EN_MAC are both used for reading in the Evaluation stage. Throughout the process, the RST_IS signal is brought forward before the RST_MAC signal, so that DR[0:14] can be generated before the MAC operation stage, thereby controlling the working state and output of the second type comparator in the Flash analog-to-digital converter module. Before the input data is input to the chip, the IS-DAC is reset by the RST_IS signal. Then, after the input data is input to the chip, the IS-DAC immediately evaluates the input sparsity in the analog domain and generates V. IS Then prepare to start V via IS-CA IS The quantization is performed. Meanwhile, the Reset_MAC process of the MAC operation is underway. When the Evaluation_MAC process begins, IS-CA has already generated DR[0:14]. This timing ensures that the addition of the input sparsity-aware strategy does not reduce the chip's computational throughput.

[0141] In summary, the SRAM in-memory computing chip based on capacitive coupling provided in this embodiment of the invention employs a 9T1C unit, which performs multiplication operations in the capacitive domain using capacitive coupling. It achieves the accumulation of 4 bits of stored data through a hierarchical attenuation capacitor structure. This structure eliminates the additional switches, complex control, and long sharing time of traditional charge-sharing structures, significantly improving the computational throughput of the multi-bit weighted data computing system. The use of a Flash analog-to-digital converter module based on an input sparsity sensing strategy reduces the number of AD comparisons and improves system energy efficiency. This chip can support 8192 4b×4b MAC operations.

[0142] Based on the above, the transfer function of a capacitively coupled SRAM in-memory computing chip was simulated under nine conditions: three temperature combinations (-40 / 27 / 85℃) and three process angle combinations (TT / SS / FF). During the simulation, all 9T1C cells in the bitwise multiplication module were written with 1, and then the corresponding input patterns were entered in ascending and equal gradients. The voltage V output by the HCA structure was then recorded. HCA The magnitude of the voltage V can be used to obtain the voltage V. HCA The relationship curve between the result of MAC operation and the result of MAC operation, such as Figure 10 As shown. Figure 10 The horizontal axis represents the MAC calculation result, and the vertical axis represents the voltage V. HCA The unit is V. The curve can be represented as:

[0143] y = 0.4676x - 1.6388, R 2 =1

[0144] The simulated transfer function showed no significant difference under different combinations of temperature and process angle. Linear fitting of the TT angle at 27℃ revealed a goodness of fit Rt. 2 The value of 1 indicates that the chip can achieve good linear MAC operations, and also shows that temperature and process-related non-ideals have little impact on its stability. Furthermore, three points were selected on the curve at MAC = 360, 960, and 1560, respectively, to present the process fluctuation variations based on 500 Monte Carlo simulations. The maximum standard deviation of the fluctuations at these three points is 0.297mV. Therefore, due to the good linear fit of the transfer function and the small temperature and process variations, this chip can provide efficient computation for convolutional neural network applications.

[0145] In addition, simulations were performed on the chip structure to calculate the voltage settling time. During the simulation, all memory locations in the 9T1C cell were first written with 1s, and then the corresponding input patterns were applied in ascending, equal-gradient manner, causing the MAC operation result to gradually increase. The average settling time of the simulated voltage for the MAC operation of 128 4-bit input data and 4-bit weighted data was 0.2 ns. Compared with the traditional multi-bit weight accumulation scheme based on a weighted capacitor array and charge sharing, this chip reduces the simulated voltage settling time by 90%, resulting in a 50% improvement in computational throughput compared to the charge-sharing scheme. The reduction in simulated voltage settling time and the increase in throughput are mainly due to the fact that the simulated voltage in this chip is established under a strong and defined externally applied voltage, while in the charge-sharing structure, the simulated voltage is established through potential rebalancing under a weak and fluctuating internal voltage.

[0146] In this embodiment of the invention, the energy efficiency of the chip under different input sparsity conditions with and without an input sparsity-aware strategy was also compared. In both cases, the chip's energy efficiency increased with increasing input sparsity, and the increment became increasingly larger. The presence of the increment without an input sparsity-aware strategy indicates that the 9T1C cell saves on the driver cost of capacitors with sparse dot product results. At lower sparsity (<30%), the result with an input sparsity-aware strategy is lower than the result without one due to the cost of IS-DAC and IS-CA. When the input sparsity is higher (>30%), the result with an input sparsity-aware strategy is significantly greater than the result without one, thanks to the large number of skipped Type II comparators in the Flash analog-to-digital converter module during computation. The input sparsity-aware strategy introduced in this chip achieves high energy efficiency of 460–2264.4 TOPS / W at input sparsity of 5% to 95%. In terms of average energy efficiency, the results of the input sparse sensing strategy show an improvement of 12.8%, achieving a high energy efficiency of 666 TOPS / W.

[0147] Table 3 shows a performance comparison between the chip structure provided in this embodiment and existing chip structures. The chip structure provided in this embodiment achieves higher energy efficiency and throughput, improving by 10 times and 1.84 times respectively compared to existing chip structures. Furthermore, behavioral simulation results show that the classification accuracy on the CIFAR-10 dataset is comparable to other works. Existing chip structures in Table 3 are represented by the publication sources of their respective structures.

[0148] Table 3 shows a performance comparison between the chip structure provided in the embodiments of the present invention and existing chip structures.

[0149]

[0150]

[0151]

[0152] The meanings of the endnotes in Table 3 are as follows: 1 This represents the average area considered by the local computing cell. 2 This refers to the current computation for 1b weight MAC and charge-sharing for multi-bit weight accumulation. 3 This means that the estimate was obtained based on the description. 4 This indicates that the result was estimated from the proposed structure using NMOS as the transmission gate. 5 This indicates that the value was estimated from the graph. 6 This indicates normalization to a 4b / 4b input / weight operation. 7 This means that one MAC operation is counted as two operations (multiplication and addition). 8 This represents the behavioral simulation result considering the comparator offset voltage.

[0153] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention. < / k>

Claims

1. A capacitively coupled SRAM in-memory computing chip, characterized in that, include: The system comprises an input module, a bitwise multiplication module, a capacitor attenuation module, and an output module, which are connected in sequence. The input module is used to receive input data; The bitwise multiplication module includes multiple bitwise multiplication units. Each bitwise multiplication unit is used to perform a multiplication operation on the input data and a bit of the stored data based on the capacitive coupling principle, so as to obtain the multiplication result corresponding to the bit of the stored data. The capacitor attenuation module includes two layers of capacitor attenuator arrays. Each first-type capacitor attenuator in the first layer of the capacitor attenuator array is connected between two adjacent bit multiplication units, and each second-type capacitor attenuator in the second layer of the capacitor attenuator array is connected between two adjacent first-type capacitor attenuators. The capacitor attenuation module is used to accumulate the multiplication results corresponding to each bit of the stored data layer by layer to obtain a multi-bit data simulation accumulation result. The output module is used to determine and output the digital accumulation result corresponding to the multi-bit data simulation accumulation result.

2. The SRAM in-memory computing chip based on capacitive coupling according to claim 1, characterized in that, The input module includes an input sparsity sensing module and an input sparsity comparison module, and the input sparsity sensing module is connected to the bitwise multiplication module. The output module includes a Flash analog-to-digital converter module, and the input sparsity sensing module, the input sparsity comparison module, and the Flash analog-to-digital converter module are connected in sequence. The input sparse sensing module is used to convert the input data into analog voltage; The input sparse comparison module is used to compare the analog voltage with the first reference voltage to obtain a first comparison result; The Flash analog-to-digital converter module is used to compare the multi-bit data analog accumulation result with the second reference voltage based on the first comparison result to obtain a second comparison result, and use the second comparison result as the digital accumulation result.

3. The SRAM in-memory computing chip based on capacitive coupling according to claim 2, characterized in that, The SRAM in-memory computing chip has two operating modes: a storage operation mode and a computing operation mode. In the storage operation mode, the input module and the output module are not working; In the computing operation mode, the SRAM in-memory computing chip performs multiplication and accumulation operations on the input data and the stored data.

4. The SRAM in-memory computing chip based on capacitive coupling according to claim 2, characterized in that, The input sparse comparison module includes multiple first comparators, and the Flash analog-to-digital conversion module includes multiple Flash analog-to-digital conversion units, each of which includes multiple second comparators; The first comparator and the second comparator are connected in a one-to-one correspondence, and the first reference voltage of each first comparator is the same as the second reference voltage of the corresponding connected second comparator.

5. The SRAM in-memory computing chip based on capacitive coupling according to claim 4, characterized in that, The number of Flash analog-to-digital conversion units is the same as the number of the second type of capacitor attenuators.

6. The SRAM in-memory computing chip based on capacitive coupling according to claim 1, characterized in that, The bit multiplication unit includes a column of 9T1C unit arrays, and the 9T1C unit array includes multiple 9T1C units; The SRAM in-memory computing chip also includes an external SRAM read / write structure, which is connected to the 9T1C unit.

7. The SRAM in-memory computing chip based on capacitive coupling according to claim 6, characterized in that, The 9T1C unit includes six first-type transistors and three second-type transistors, and both the first-type transistors and the second-type transistors are connected to the SRAM read / write external structure. The six first-type transistors are used to store one bit of the stored data; The three second-type transistors are used to perform a multiplication operation between one bit of the stored data stored in the six first-type transistors and the corresponding bit of the input data.

8. The SRAM in-memory computing chip based on capacitive coupling according to claim 6, characterized in that, The external structure for SRAM read / write includes an SRAM controller, SRAM peripheral circuitry, and an address decoding driver. The SRAM controller is connected to the SRAM peripheral circuit and the address decoding driver, respectively. The SRAM peripheral circuit and the address decoding driver are both connected to the 9T1C unit.

9. The SRAM in-memory computing chip based on capacitive coupling according to any one of claims 1-8, characterized in that, The SRAM in-memory computing chip also includes an in-memory computing controller, which is connected to both the input module and the output module.

10. The SRAM in-memory computing chip based on capacitive coupling according to any one of claims 1-8, characterized in that, The stored data includes multiple 4-bit weight data from the neural network.

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