Semiconductor Structure and Method for Forming the Same

Abstract

A semiconductor structure and a method for forming the same. The forming method includes: forming a stacked structure on a substrate, the stacked structure including a plurality of first functional layers and second functional layers alternately stacked from bottom to top in sequence; forming a protective sidewall on the sidewalls of the second stacked structure; removing the first functional layers in the first stacked structure, and using the second functional layers in the first stacked structure as a first channel layer; forming a bottom gate surrounding the first channel layer; removing the protective sidewall; removing the second functional layers in the second stacked structure, and using the first functional layers in the second stacked structure as a second channel layer; forming a top gate surrounding the second channel layer. In the embodiments of the present invention, the second functional layers in the first stacked structure are respectively retained as the first channel layer, and the first functional layers in the second stacked structure are retained as the second channel layer, so as to form different channel layers for the first device structure and the second device structure, and it is beneficial to reduce the probability of damage to the first channel layer and the second channel layer, thereby improving the performance of the CFET.

Description

Technical Field

[0001] Embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular, to a semiconductor structure and a method for forming the same. Background Art

[0002] In semiconductor manufacturing, with the development trend of very large scale integrated circuits, the feature size of integrated circuits continues to decrease. To adapt to the reduction of the feature size, the channel length of MOSFETs is also continuously shortened accordingly. However, as the channel length of the device is shortened, the distance between the source and drain of the device is also shortened, so the gate's control ability over the channel becomes worse, and it becomes more and more difficult for the gate voltage to pinch off the channel, making the subthreshold leakage phenomenon, namely the so-called short-channel effects (SCE), more likely to occur.

[0003] Therefore, to better adapt to the reduction of the feature size, the semiconductor process has gradually started to transition from planar MOSFETs to three-dimensional transistors with higher efficiency.

[0004] Among them, complementary FET (CFET) composed of vertical stacking is a revolutionary three-dimensional transistor. In the CFET structure, PMOS transistors and NMOS transistors vertically stacked with each other form complementary devices, which can save area, increase the transistor integration density, and is beneficial to reducing power consumption and improving cost performance.

[0005] However, the current process for forming CFET devices still has great challenges. Summary of the Invention

[0006] The problem solved by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, which form different channel layers for the first device structure and the second device structure respectively, and are beneficial to reducing the probability of damage to the first channel layer and the second channel layer, and improving the performance of the complementary field effect transistor (CFET).

[0007] To solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate; forming a stacked structure on the substrate, including a plurality of first functional layers and second functional layers alternately stacked from bottom to top in sequence, one of the second functional layers and the first functional layer located on the second functional layer are used to form a channel stack, the first functional layer closest to the substrate is used as the bottom functional layer, and the second functional layer farthest from the substrate is used as the top functional layer; the bottom functional layer and one or more of the channel stacks located on the bottom functional layer are used to form a first stacked structure, and the remaining channel stacks located on the first stacked structure and the top functional layer are used to form a second stacked structure; forming a protective sidewall on the sidewall of the second stacked structure; after forming the protective sidewall, removing the first functional layer in the first stacked structure, so that the second functional layer in the first stacked structure is used as the first channel layer; forming a bottom gate surrounding the first channel layer, and the bottom gate and the first channel layer are used to form a first device structure; after forming the bottom gate, removing the protective sidewall to expose the top surface and sidewall of the second stacked structure; removing the second functional layer in the second stacked structure, so that the first functional layer in the second stacked structure is used as the second channel layer; forming a top gate surrounding the second channel layer on the bottom gate, and the top gate and the second channel layer are used to form a second device structure.

[0008] Correspondingly, an embodiment of the present invention further provides a semiconductor structure, including: a substrate; a first device structure located on the substrate, the first device structure including: a first channel structure layer located on the substrate and spaced apart from the substrate, the first channel structure layer including one or more first channel layers spaced apart; a bottom gate surrounding the first channel layer; a second device structure located on the first device structure, including: a second channel structure layer located on the first channel structure layer and spaced apart from the first channel structure layer, the second channel structure layer including one or more second channel layers spaced apart, the material of the second channel layer is different from that of the first channel layer, the first channel layer and the second channel layer extend laterally, and the direction parallel to the substrate and perpendicular to the lateral direction is the longitudinal direction; a top gate located on the bottom gate and surrounding the second channel layer.

[0009] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:

[0010] In the method for forming a semiconductor structure provided by an embodiment of the present invention, the first functional layer in the first stacked structure and the second functional layer in the second stacked structure are removed in different steps respectively. During the process of removing the first functional layer in the first stacked structure and the second functional layer in the second stacked structure, only an etching selectivity ratio is required between the first functional layer and the second functional layer, which is beneficial to reducing the process difficulty of removing the first functional layer in the first stacked structure and the second functional layer in the second stacked structure. Moreover, before removing the first functional layer in the first stacked structure, a protective sidewall is formed on the sidewall of the second stacked structure. The protective sidewall can protect the second stacked structure during the process of removing the first functional layer in the first stacked structure, reducing the probability of damage to the second stacked structure. Furthermore, after forming the bottom gate, the second functional layer in the second stacked structure is removed. Since the bottom gate surrounds the first channel layer, it is beneficial to prevent the first channel layer from being damaged during the process of removing the second functional layer in the second stacked structure, correspondingly ensuring the integrity and formation quality of the first channel layer and the second channel layer. In summary, in the embodiment of the present invention, the second functional layer in the first stacked structure is respectively retained as the first channel layer, and the first functional layer in the second stacked structure is retained as the second channel layer, so that different channel layers can be formed for the first device structure and the second device structure, and it is beneficial to reduce the probability of damage to the first channel layer and the second channel layer and ensure the formation quality of the first channel layer and the second channel layer, thereby improving the performance of the complementary field effect transistor (CFET). Description of the Drawings

[0011] Figure 1 are schematic structural diagrams corresponding to each step in a method for forming a semiconductor structure;

[0012] Figures 2 to 21 are schematic structural diagrams corresponding to each step in an embodiment of the method for forming a semiconductor structure of the present invention. Detailed Embodiments

[0013] As can be seen from the background art, the current process for forming CFET devices still poses great challenges.

[0014] Specifically, during the formation of current fully surrounding gate transistors (GAA nanosheet or GAA nanowire), generally, a stack of SiGe / Si needs to be formed first. SiGe is used as a sacrificial layer, and Si is used as a channel layer, which will be removed in subsequent processes. The Si layer is left as channel material to form a fully surrounding structure of the metal gate for the channel layer.

[0015] Based on the SiGe / Ge stack, multiple transistors can be sequentially stacked vertically to form a structure called CFET, thereby increasing the transistor density per unit area. For a CFET device formed based on the SiGe / Ge stack, since generally only SiGe can be used as the sacrificial layer, the channel materials of both NMOS and PMOS are Si.

[0016] However, NMOS and PMOS have different requirements for channel stress, and special requirements for the materials and processes of the NMOS and PMOS channels are needed. Currently, in CFET devices, it is quite difficult to form channels of different materials for NMOS and PMOS respectively. Now, in combination with a method for forming a semiconductor structure, the reasons for the great difficulty in forming channels of different materials for NMOS and PMOS in CFET devices are described. Figure 1 It is a schematic structural diagram corresponding to each step in a method for forming a semiconductor structure.

[0017] Reference Figure 1 (a), Provide a substrate 10, on which one or more first channel stacks 30 are sequentially stacked from bottom to top, and one or more second channel stacks 40 are stacked on the first channel stack 30. The first channel stack 30 includes a sacrificial layer 20 and a first channel layer 21 located on the sacrificial layer 20. The second channel stack 40 includes a sacrificial layer 20 and a second channel layer 22 located on the sacrificial layer 20. The sacrificial layer 20 is also formed on the top of the second channel stack 40.

[0018] Among them, the first channel stack 30 is used to form an NMOS device, the second channel stack 40 is used to form a PMOS device, the material of the first channel layer 21 is Si, the material of the second channel layer 22 is SiGe, and the material of the sacrificial layer 20 is doped Si.

[0019] Reference Figure 1 (b), Remove the sacrificial layer 20, so that the first channel layer 21 and the second channel layer 22 are spaced and suspended on the substrate 10.

[0020] Reference Figure 1 (c), Form a metal gate structure 50 surrounding the first channel layer 21 and the second channel layer 22.

[0021] In the formation method, an Si channel is used for NMOS, and an SiGe channel is used for PMOS. Moreover, doped Si is used as the material of the sacrificial layer 20, so that in the step of removing the sacrificial layer 20 by an etching process, the etching process has a high etching selectivity between the sacrificial layer 20 and the first channel layer 21, and between the sacrificial layer 20 and the second channel layer 22, thereby retaining the first channel layer 21 and the second channel layer 22, and arranging the first channel layer 21 and the second channel layer 22 to be spaced and suspended, so as to form a metal gate structure 50 surrounding the first channel layer 21 and the second channel layer 22.

[0022] However, the sacrificial layer 20 is made of doped Si material, and doped Si is still a material based on Si atoms. In the process of removing the sacrificial layer 20 by an etching process, it is difficult for the etching process to achieve the desired high etching selectivity between doped Si and Si, and between doped Si and SiGe. In the same step of removing the sacrificial layer 20 by the method, it is easy to damage the first channel layer 21 and the second channel layer 22, thereby resulting in poor performance of the semiconductor structure.

[0023] To solve the above technical problems, an embodiment of the present invention provides a method for forming a semiconductor structure, removing the first functional layer in the first stacked structure and removing the second functional layer in the second stacked structure in different steps respectively. In the process of removing the first functional layer in the first stacked structure and removing the second functional layer in the second stacked structure, only an etching selectivity between the first functional layer and the second functional layer is required, which is beneficial to reducing the process difficulty of removing the first functional layer in the first stacked structure and removing the second functional layer in the second stacked structure; moreover, before removing the first functional layer in the first stacked structure, a protective sidewall is formed on the sidewall of the second stacked structure, and the protective sidewall can protect the second stacked structure in the process of removing the first functional layer in the first stacked structure, reducing the probability of damage to the second stacked structure; furthermore, after forming the bottom gate, the second functional layer in the second stacked structure is removed. Since the bottom gate surrounds the first channel layer, it is beneficial to prevent the first channel layer from being damaged in the process of removing the second functional layer in the second stacked structure; in summary, in the embodiment of the present invention, the second functional layer in the first stacked structure is retained as the first channel layer, and the first functional layer in the second stacked structure is retained as the second channel layer, so that different channel layers can be formed for the first device structure and the second device structure, and it is beneficial to reduce the probability of damage to the first channel layer and the second channel layer, ensure the formation quality of the first channel layer and the second channel layer, and improve the performance of the CFET.

[0024] To make the above objects, features, and advantages of the embodiments of the present invention more obvious and understandable, the following detailed description of the specific embodiments of the present invention will be given with reference to the accompanying drawings.Figures 2 to 21 It is a schematic structural diagram corresponding to each step in an embodiment of the method for forming a semiconductor structure of the present invention.

[0025] Referring to Figure 2 , Figure 2 (b) is Figure 2 a cross-sectional view of (a) along the x2-x2 direction, providing a substrate 100.

[0026] The substrate 100 is used to provide a process platform for subsequent processes. In this embodiment, the substrate 100 is a silicon substrate.

[0027] Continuing to refer to Figure 2 , Figure 2 (a) is a cross-sectional view along a direction perpendicular to the extension direction of the stacked structure at the stacked structure, Figure 2 (b) is Figure 2 a cross-sectional view of (a) along the x2-x2 direction. A stacked structure is formed on the substrate 100, including a plurality of first functional layers 110 and second functional layers 120 alternately stacked from bottom to top. One second functional layer 120 and the first functional layer 110 located on the second functional layer 120 are used to form a channel stack 200. The first functional layer 110 closest to the substrate 100 serves as the bottom functional layer 110(1), and the second functional layer 120 farthest from the substrate 100 serves as the top functional layer 120(1); the bottom functional layer 110(1) and one or more of the channel stacks 200 located on the bottom functional layer 110(1) are used to form a first stacked structure 210, and the remaining channel stacks 210 located on the first stacked structure 300 and the top functional layer 120(1) are used to form a second stacked structure 220.

[0028] The plurality of first functional layers 110 and second functional layers 120 are alternately stacked from bottom to top, so that after removing the first functional layer 110 in the first stacked structure 210 subsequently, the second functional layer 120 in the first stacked structure 210 can be spaced and suspended, and after removing the second functional layer 120 in the second stacked structure 220 subsequently, the first functional layer 110 in the second stacked structure 220 can be spaced and suspended; moreover, in this embodiment, during the process of forming the stacked structure, by only forming the first functional layer 110 and the second functional layer 120 of two materials, different channel layers can be formed for different device structures subsequently, and it is also beneficial to be compatible with the existing process of the gate-all-around (GAA) transistor, improving the process compatibility.

[0029] In this embodiment, the first stacked structure 210 is used to form the first device structure subsequently, and the second stacked structure 220 is used to form the second device structure subsequently. The first device structure and the second device structure are stacked on the substrate 100 to form a complementary field-effect transistor (CFET), which can save area, improve the transistor integration density, and is beneficial to reducing power consumption and improving cost performance.

[0030] Correspondingly, in this embodiment, in the first stacked structure 210, the first functional layer 110 is used as a sacrificial layer, and the second functional layer 120 is used as the first channel layer of the subsequent first device structure; in the second stacked structure 220, the second functional layer 120 is used as a sacrificial layer, and the first functional layer 110 is used as the second channel layer of the subsequent second device structure.

[0031] In this embodiment, the material of the first functional layer 110 is SiGe, the material of the second functional layer 120 is Si, the first device structure is used to form an NMOS transistor, and the second device structure is used to form a PMOS transistor. Correspondingly, the second functional layer 120 in the subsequent first stacked structure 210 is used as the channel layer of the NMOS transistor, and the first functional layer 110 in the subsequent second stacked structure 220 is used as the channel layer of the PMOS transistor. Therefore, an Si channel is used for the NMOS and an SiGe channel is used for the PMOS, which is beneficial to improving the performance of the NMOS transistor and the PMOS transistor, and correspondingly improving the performance of the CFET device.

[0032] In other embodiments, the material of the first functional layer is Si, the material of the second functional layer is SiGe, the first device structure is used to form a PMOS transistor, and the second device structure is used to form an NMOS transistor. Correspondingly, an Si channel can also be used for the NMOS and an SiGe channel can be used for the PMOS, which is beneficial to improving the performance of the NMOS transistor and the PMOS transistor.

[0033] As an example, the first stacked structure 210 includes the bottom functional layer 110(1) and a channel stack 200 located on the bottom functional layer 110(1), and the second stacked structure 220 includes two channel stacks 200 stacked in sequence and the top functional layer 120(1). In other embodiments, the number of channel stacks in the first stacked structure and the second stacked structure can also be other numbers.

[0034] In this embodiment, the stacked structure is a fin-type thin film structure, and there are multiple stacked structures, which are separated on the substrate 100. In this embodiment, the stacked structure extends in a lateral direction, and the direction parallel to the substrate 100 and perpendicular to the lateral direction is the longitudinal direction.

[0035] In this embodiment, the step of forming the stacking structure includes: forming an initial stacking structure (not shown) covering the substrate 100, including a plurality of first functional material layers (not shown) and second functional material layers (not shown) alternately stacked from bottom to top; graphing the initial stacking structure, with the remaining first functional material layers serving as the first functional layers 110, and the remaining second functional material layers serving as the second functional layers 120, and the alternately stacked first functional layers 110 and second functional layers 120 constituting the stacking structure.

[0036] In this embodiment, the formation method further includes: forming a trench isolation structure 105 in the substrate 100 exposed from the stacked structure. The trench isolation structure 105 is used to achieve electrical isolation between the substrate 100 and a subsequent dummy gate or bottom gate, and is also used to isolate adjacent stacked structures. In this embodiment, the trench isolation structure 105 is a shallow trench isolation structure (STI), and the material of the trench isolation structure 105 is silicon oxide.

[0037] refer to Figure 3 , Figure 3 (a) is a cross-sectional view along the longitudinal direction of the stacking structure. Figure 3 (b) Yes Figure 3 (a) Cross-sectional view along the x1-x1 direction, Figure 3 (c) Yes Figure 3 (a) A cross-sectional view along the x2-x2 direction. In this embodiment, after forming the stacked structure, the forming method further includes: forming a dummy gate 130 across the stacked structure, wherein the dummy gate 130 covers a portion of the top and a portion of the sidewall of the stacked structure. The dummy gate 130 also exposes a portion of the top and a portion of the sidewall of the stacked structure on both sides.

[0038] The dummy gate 130 is used to occupy part of the space for subsequently forming a bottom gate and a top gate.

[0039] In this embodiment, the dummy gate 130 includes a dummy gate layer, and the material of the dummy gate layer includes polysilicon.

[0040] In this embodiment, the dummy gate 130 is located on the trench isolation structure 105 .

[0041] In this embodiment, the steps of forming the dummy gate 130 include: forming a dummy gate material layer (not shown in the figure) covering the top surface and sidewalls of the stacked structure on the trench isolation structure 105; patterning the dummy gate material layer to retain a portion of the dummy gate material layer across the stacked structure to serve as the dummy gate 130.

[0042] In this embodiment, the forming method further includes: forming a gate sidewall 135 on the sidewalls of the dummy gate 130. The gate sidewall 135 is used to protect the sidewalls of the dummy gate 130 and the sidewalls of the subsequent bottom gate and top gate, and the gate sidewall 135 is also used to define the formation position of the subsequent second source / drain doping layer.

[0043] As an example, the gate sidewall 135 is a single-layer structure, and the material of the gate sidewall 135 is silicon nitride.

[0044] The subsequent steps further include: removing the dummy gate 130 above the top surface of the first stacked structure 210 to form a top gate opening, exposing the top surface and sidewalls of the second stacked structure 220.

[0045] Reference Figures 4 to 12 , in this embodiment, after forming the dummy gate 130 and before removing the dummy gate 130 above the top surface of the first stacked structure 210, the forming method further includes: forming a first source / drain doping layer 310 in the first stacked structure 210 on both sides of the dummy gate 130, a bottom dielectric layer 320 on the first source / drain doping layer 310, a second source / drain doping layer 410 in the second stacked structure 220 on both sides of the dummy gate 130, and a top dielectric layer 420 on the second source / drain doping layer 410. The bottom dielectric layer 320 covers a portion of the sidewalls of the dummy gate 130, and the top dielectric layer 420 is located on the bottom dielectric layer 320 and covers the sidewalls of the dummy gate 130 exposed by the bottom dielectric layer 320.

[0046] Subsequently, remove the first functional layer 110 in the first stacked structure 210, make the second functional layer 120 in the first stacked structure 210 serve as the first channel layer, and form a bottom gate surrounding the first channel layer; remove the second functional layer 120 in the second stacked structure 220, make the first functional layer 110 in the second stacked structure 220 serve as the second channel layer, and form a top gate surrounding the second channel layer.

[0047] The first source / drain doping layer 310 and the bottom dielectric layer 320 are used to form a first device structure together with the subsequent bottom gate and the first channel layer, and the second source / drain doping layer 410 and the top dielectric layer 320 are used to form a second device structure together with the subsequent top gate and the second channel layer, thereby realizing the vertical stacking of the first device structure and the second device structure.

[0048] Specifically, the first source / drain doping layer 310 is used as the source region or drain region of the first device structure, and the second source / drain doping layer 410 is used as the source region or drain region of the second device structure.

[0049] In this embodiment, the first device structure is used to form an NMOS transistor, and the second device structure is used to form a PMOS transistor. Correspondingly, the first source / drain doping layer 310 is N-type doped, and the second source / drain doping layer 410 is P-type doped.

[0050] Specifically, the first source / drain doping layer 310 includes a stress layer doped with N-type ions, and the stress layer is used to provide tensile stress for the channel of the NMOS transistor to improve the mobility of electrons; the second source / drain doping layer 410 includes a stress layer doped with P-type ions, and the stress layer is used to provide compressive stress for the channel of the PMOS transistor to improve the mobility of holes.

[0051] In other embodiments, when the first device structure is used to form a PMOS transistor and the second device structure is used to form an NMOS transistor, the first source / drain doping layer is P-type doped, and the second source / drain doping layer is N-type doped. Specifically, the first source / drain doping layer includes a stress layer doped with P-type ions, and the second source / drain doping layer includes a stress layer doped with N-type ions.

[0052] In this embodiment, as an example, the first source / drain doping layer 310 covers the substrate 100 along the transverse direction. In other embodiments, a part of the substrate may also be exposed along the transverse first source / drain doping layer.

[0053] The bottom dielectric layer 320 is used to isolate adjacent first device structures, and the bottom dielectric layer 320 is also used to isolate the first device structure from the second device structure in the direction perpendicular to the substrate 100. The top dielectric layer 420 is used to isolate adjacent second device structures.

[0054] Both the bottom dielectric layer 320 and the top dielectric layer 420 are interlayer dielectric layers (ILDs). In this embodiment, the materials of the bottom dielectric layer 320 and the top dielectric layer 420 are silicon oxide.

[0055] The following will describe in detail the steps of forming the first source / drain doping layer 310, the bottom dielectric layer 320, the second source / drain doping layer 410, and the top dielectric layer 420 in this embodiment with reference to the accompanying drawings.

[0056] Refer to Figure 4 , Figure 4 (a) is a longitudinal sectional view at the dummy gate 130, Figure 4 (b) is Figure 4 (a) a cross-sectional view along the x1 - x1 direction,Figure 4 (c) is Figure 4 (a) A cross-sectional view along the x2 - x2 direction, in which a top groove 140 is formed in the second stacked structure 220 on both sides of the dummy gate 130.

[0057] The top groove 140 is used to provide a spatial position for forming the second source / drain doping layer.

[0058] Specifically, using the dummy gate 130 and the gate sidewall 135 as masks, the second stacked structure 220 is etched to form the top groove 140. Correspondingly, the top surface of the first stacked structure 210 located on both sides of the dummy gate 130 is exposed at the bottom of the top groove 140.

[0059] Refer to Figure 5 , Figure 5 (a) is a longitudinal cross-sectional view at the dummy gate 130, Figure 5 (b) is Figure 5 (a) A cross-sectional view along the x1 - x1 direction, Figure 5 (c) is Figure 5 (a) A cross-sectional view along the x2 - x2 direction, in which a mask sidewall 150 is formed on the sidewall of the second stacked structure 220 exposed by the top groove 140.

[0060] The mask sidewall 150 is used as a mask for subsequent etching of the first stacked structure 210, and the mask sidewall 150 is also used to protect the first stacked structure 210 during the subsequent formation of the first source / drain doping layer. The material of the mask sidewall 150 can be silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, or silicon carbon oxynitride. In this embodiment, the material of the mask sidewall 150 is silicon carbide.

[0061] In this embodiment, the mask sidewall 150 is also formed on the sidewall of the dummy gate 130.

[0062] Refer to Figures 6 to 9 , the first source / drain doping layer 310 is formed in the first stacked structure 210 on both sides of the dummy gate 130 and the mask sidewall 150 (as Figure 9 shown).

[0063] In this embodiment, the steps of forming the first source / drain doping layer 310 include: as Figure 6 shown, Figure 6 (a) is a longitudinal cross-sectional view at the dummy gate 130, Figure 6 (b) is Figure 6 (a) A cross-sectional view along the x1 - x1 direction, Figure 6 (c) is Figure 6(a) Cross-sectional view along the x2 - x2 direction, a bottom groove 160 is formed in the first stacked structure 210 on both sides of the dummy gate 130 and the mask sidewall 150, communicating with the top groove 140; as Figure 9 shown, Figure 9 (a) is a longitudinal cross-sectional view at the dummy gate 130, Figure 9 (b) is Figure 9 (a) cross-sectional view along the x1 - x1 direction, Figure 9 (c) is Figure 9 (a) cross-sectional view along the x2 - x2 direction, a first source / drain doping layer 310 is formed in the bottom groove 160.

[0064] Specifically, using the dummy gate 130, the gate sidewall 135, and the mask sidewall 150 as masks, the first stacked structure 210 is etched to form the bottom groove 160.

[0065] Therefore, after the bottom groove 160 is formed, along the transverse direction, the second functional layer 120 in the first stacked structure 210 protrudes relative to the end of the first functional layer 110 in the second stacked structure 220. Thus, after the first channel layer and the second channel layer are subsequently formed, the end of the first channel layer protrudes from the end of the second channel layer along the transverse direction. Specifically, relative to the end of the first functional layer 110 on the same side in the second stacked structure 220, the size of the single - side end of the second functional layer 120 in the first stacked structure 210 that protrudes is the thickness of the mask sidewall 150.

[0066] In this embodiment, an epitaxial process is used to form a stress layer, and in - situ self - doped ions are formed during the formation of the stress layer to form the first source / drain doping layer 310.

[0067] It should be noted that in this embodiment, the forming method further includes: as Figure 7 shown, Figure 7 (a) is a longitudinal cross - sectional view at the dummy gate 130, Figure 7 (b) is Figure 7 (a) cross - sectional view along the x1 - x1 direction, Figure 7 (c) is Figure 7 (a) cross - sectional view along the x2 - x2 direction, after the bottom groove 160 is formed and before the first source / drain doping layer 310 is formed, along the extending direction of the first functional layer 110, the first functional layer 110 in the first stacked structure 210 is etched so that the first functional layer 110 of the first stacked structure 210 and the adjacent second functional layer 120 enclose a first trench 170; as Figure 8 shown, Figure 8 (a) is a longitudinal cross - sectional view at the dummy gate 130, Figure 8 (b) is Figure 8(a) Cross-sectional view along the x1-x1 direction, Figure 8 (c) is Figure 8 (a) Cross-sectional view along the x2-x2 direction, and a first inner sidewall 180 is formed in the first trench 170.

[0068] The first trench 170 is used to provide a spatial position for forming the first inner sidewall 180.

[0069] In this embodiment, an isotropic etching process is adopted to etch the first functional layer 110 in the first stacked structure 210 along the extending direction of the first functional layer 110. The isotropic etching process has isotropic etching characteristics, so that the first functional layer 110 exposed on the sidewall of the bottom groove 160 can be etched along the extending direction of the first functional layer 110.

[0070] As an example, a wet etching process is adopted to etch the first functional layer 110 in the first stacked structure 210 along the extending direction of the first functional layer 110. The wet etching process is easy to achieve a large etching selectivity. Specifically, the material of the first functional layer 110 is SiGe, the material of the second functional layer 120 is Si, and the first functional layer 110 in the first stacked structure 210 is etched with HCl vapor. The etching rate of HCl vapor for the SiGe material is much greater than that for the Si material, which can effectively reduce the probability of the second functional layer 120 being damaged and is beneficial to improving the performance of the first device structure.

[0071] Subsequently, a first part of the bottom gate is formed at the position of the first functional layer 110 in the first stacked structure 210, and the first inner sidewall 180 is used to isolate the first part of the bottom gate from the first source / drain doping layer 310. The material of the first inner sidewall 180 is a low-k dielectric material or an ultra-low-k dielectric material, which is beneficial to reducing the coupling capacitance between the first part of the bottom gate and the first source / drain doping layer 310.

[0072] Continue to refer to Figure 9 , the bottom dielectric layer 320 is formed on the first source / drain doping layer 310, exposing the mask sidewall 150 on the sidewall of the second stacked structure 220. In this embodiment, the bottom dielectric layer 320 also covers the mask sidewall 150 on a part of the sidewall of the dummy gate 130.

[0073] In this embodiment, the step of forming the bottom dielectric layer 320 includes: forming a dielectric material layer (not shown in the figure) on the substrate 100, the dielectric material layer covering the top of the first source / drain doping layer 310, the top of the dummy gate 130, and the sidewalls of the mask sidewall 150; adopting a planarization process to remove the dielectric material layer higher than the top surface of the dummy gate 130; and back-etching to remove the dielectric material layer higher than the top surface of the first stacked structure 210.

[0074] Reference Figure 10 , Figure 10 (a) is a longitudinal cross-sectional view at the dummy gate 130, Figure 10 (b) is Figure 10 (a) a cross-sectional view along the x1-x1 direction, Figure 10 (c) is Figure 10 (a) a cross-sectional view along the x2-x2 direction. After forming the bottom dielectric layer 320, the mask sidewall 150 located on the sidewall of the second stacked structure 220 is removed. Removing the mask sidewall 150 located on the sidewall of the second stacked structure 220 exposes the sidewall of the second stacked structure 220, so that a second source / drain doping layer can be formed in the top groove 140 subsequently.

[0075] In this embodiment, an isotropic etching process is used to remove the mask sidewall 150 located on the sidewall of the second stacked structure 220. Specifically, the isotropic etching process is a wet etching process or an isotropic dry etching process.

[0076] It should be noted that in the step of removing the mask sidewall 150 located on the sidewall of the second stacked structure 220, the mask sidewall 150 on the sidewall of the dummy gate 130 exposed by the bottom dielectric layer 320 is also removed, wherein the mask sidewall 150 on a part of the sidewall of the dummy gate 130 is retained under the coverage of the bottom dielectric layer 320.

[0077] Reference Figure 11 , Figure 11 (a) is a longitudinal cross-sectional view at the dummy gate 130, Figure 11 (b) is Figure 11 (a) a cross-sectional view along the x1-x1 direction, Figure 11 (c) is Figure 11 (a) a cross-sectional view along the x2-x2 direction. The forming method further includes: after removing the mask sidewall 150 located on the sidewall of the second stacked structure 220 and before forming the second source / drain doping layer, etching the second functional layer 120 in the second stacked structure 220 along the extending direction of the second functional layer 120, so that the second functional layer 120 in the second stacked structure 220 and the adjacent first functional layer 110 enclose a second trench (not shown in the figure); forming a second inner sidewall 190 in the second trench.

[0078] The second trench is used to provide a spatial position for forming the second inner sidewall.

[0079] In this embodiment, an isotropic etching process is used to etch the second functional layer 120 exposed on the sidewall of the top groove 140 along the extending direction of the second functional layer 120. As an example, the isotropic etching process is a wet etching process.

[0080] Specifically, the material of the first functional layer 110 is SiGe, the material of the second functional layer 120 is Si, and the etching solution for the wet etching process is a tetramethylammonium hydroxide (TMAH) solution. The difference in the etching rate of the TMAH solution for the Si material and the SiGe material is relatively large, which can effectively reduce the probability of the first functional layer 110 being damaged and is beneficial to improving the performance of the device.

[0081] Subsequently, a first part of the top gate is formed at the position of the first functional layer 110 in the second stacked structure 220, and the second inner sidewall 190 is used to isolate the first part of the top gate from the second source / drain doping layer. The material of the second inner sidewall 190 is a low-k dielectric material or an ultra-low-k dielectric material to reduce the coupling capacitance between the first part of the top gate and the second source / drain doping layer.

[0082] Reference Figure 12 , Figure 12 (a) is a longitudinal sectional view at the pseudo-gate 130, Figure 12 (b) is Figure 12 a sectional view of (a) along the x1-x1 direction, Figure 12 (c) is Figure 12 a sectional view of (a) along the x2-x2 direction, and the second source / drain doping layer 410 is formed in the top groove 140.

[0083] In this embodiment, the step of forming the second source / drain doping layer 410 includes: using an epitaxial process to form a stress layer in the top groove 140, and in-situ self-doping ions during the formation of the stress layer to form the second source / drain doping layer 410.

[0084] As an example, along the transverse direction, the top surface of the bottom dielectric layer 320 above the first source / drain doping layer 310 is also exposed on both sides of the second source / drain doping layer 410, and the sidewall of the second source / drain doping layer 410 along the transverse direction is indented relative to the sidewall on the same side of the first source / drain doping layer 310. In other embodiments, the second source / drain doping layer may also cover the bottom dielectric layer located above the first source / drain doping layer.

[0085] Continue to refer to Figure 12 , and a top dielectric layer 420 is formed on the second source / drain doping layer 410.

[0086] In this embodiment, the step of forming the top dielectric layer 420 includes: forming a dielectric material layer on the bottom dielectric layer 320 to cover the second source / drain doping layer 410, the top of the pseudo-gate 130, and the sidewalls of the gate sidewall 135; using a planarization process to remove the dielectric material layer higher than the pseudo-gate 130.

[0087] Correspondingly, the top medium layer 420 exposes the top of the dummy gate 130, facilitating the subsequent removal of the dummy gate 130 through the exposed top of the dummy gate 130.

[0088] Reference Figure 13 , Figure 13 (a) is a longitudinal sectional view at the dummy gate 130, Figure 13 (b) is Figure 13 a sectional view of (a) along the x1 - x1 direction, Figure 13 (c) is Figure 13 a sectional view of (a) along the x2 - x2 direction. The dummy gate 130 above the top surface of the first stacked structure 210 is removed to form a top gate opening 230, exposing the top surface and sidewalls of the second stacked structure 220.

[0089] The formation of the top gate opening 230 facilitates the subsequent formation of a protective sidewall on the exposed sidewalls of the second stacked structure 220, enabling the subsequent removal of the first functional layer 110 in the first stacked structure 210 and the second functional layer 120 in the second stacked structure 220 in different steps respectively. Moreover, it is also possible to form a bottom gate surrounding the first channel layer and a top gate surrounding the second channel layer in different steps respectively.

[0090] The process of removing the dummy gate 130 above the top surface of the first stacked structure 210 includes one or both of an isotropic etching process and an anisotropic etching process.

[0091] Reference Figure 14 , Figure 14 (a) is a longitudinal sectional view at the top gate opening 230, Figure 14 (b) is Figure 14 a sectional view of (a) along the x1 - x1 direction, Figure 14 (c) is Figure 14 a sectional view of (a) along the x2 - x2 direction, and a protective sidewall 240 is formed on the sidewalls of the second stacked structure 220.

[0092] The protective sidewall 240 can protect the second stacked structure 220 during the subsequent removal of the first functional layer 110 in the first stacked structure 210, thereby reducing the probability of damage to the second stacked structure 220 and further ensuring the integrity and formation quality of the first functional layer 110 in the second stacked structure 220.

[0093] In this embodiment, the protective sidewall 240 is formed on the sidewalls of the second stacked structure 220 exposed by the top gate opening 230. In this embodiment, the protective sidewall 240 is also formed on the gate sidewall 135 of the sidewalls of the top gate opening 230.

[0094] The protective sidewall 240 is made of a material that has an etching selectivity with respect to the first functional layer 110, the second functional layer 120, the dummy gate 130, the bottom dielectric layer 320, and the top dielectric layer 420. The material of the protective sidewall 240 includes silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, or silicon carbon oxynitride. In this embodiment, the material of the protective sidewall 240 is silicon nitride.

[0095] The thickness of the protective sidewall 240 should not be too small, otherwise it is likely to reduce the protection effect of the protective sidewall 240 on the second stacked structure 220; the thickness of the protective sidewall 240 should not be too large, otherwise it is likely to result in too small a remaining space in the top gate opening 230, which is likely to increase the difficulty of subsequent removal of the remaining dummy gate 130 and removal of the first functional layer 110 in the first stacked structure 210 through the top gate opening 230.

[0096] Therefore, in this embodiment, along the extending direction of the first functional layer 110 and the second functional layer 120, the width of the dummy gate 130 is a first width w1 (as shown in Figure 14 (b)), and the thickness of the protective sidewall 240 is 5% to 30% of the first width w1.

[0097] In this embodiment, the steps of forming the protective sidewall 240 include: forming a protective sidewall material layer (not shown in the figure) on the sidewalls and bottom of the top gate opening 230 and on the top of the top dielectric layer 420; removing the protective sidewall material layer on the bottom of the top gate opening 230 and on the top of the top dielectric layer 420, and the remaining protective sidewall material layer on the sidewalls of the top gate opening 230 is used as the protective sidewall 240.

[0098] In this embodiment, an atomic layer deposition process is used to form the protective sidewall material layer. Using the atomic layer deposition process is beneficial to improving the step coverage ability, thickness uniformity, and film formation quality of the protective material layer, and is also beneficial to precisely controlling the thickness of the protective material layer.

[0099] In this embodiment, an anisotropic etching process is used to etch the protective sidewall material layer to remove the protective sidewall material layer on the bottom of the top gate opening 230 and on the top of the top dielectric layer 420, while minimizing the loss of the protective sidewall material layer on the sidewalls of the top gate opening 230.

[0100] Refer to Figure 15 , Figure 15 (a) is a longitudinal sectional view at the top gate opening 230, Figure 15 (b) is a cross-sectional view of Figure 15 (a) along the x1-x1 direction, Figure 15 (c) is Figure 15(a) Cross-sectional view along the x2-x2 direction. After forming the protective sidewall 240, the forming method further includes: removing the remaining dummy gate 130, forming a bottom gate opening 250 below the top gate opening 230, and exposing the sidewalls of the first stacked structure 210.

[0101] Removing the remaining dummy gate 130 to expose the sidewalls of the first stacked structure 210, so as to facilitate the subsequent removal of the first functional layer 110 in the first stacked structure 210 through the exposed sidewalls of the first stacked structure 210.

[0102] The bottom gate opening 250 is used to provide a spatial position for forming the bottom gate subsequently.

[0103] In this embodiment, an isotropic etching process is used to remove the remaining dummy gate 130. The isotropic etching process has the characteristic of isotropic etching, which is easy to completely remove the remaining dummy gate 130 covering the sidewalls of the first stacked structure 210.

[0104] Reference Figure 16 , Figure 16 (a) is a longitudinal cross-sectional view at the top gate opening 230, Figure 16 (b) is Figure 16 (a) cross-sectional view along the x1-x1 direction, Figure 16 (c) is Figure 16 (a) cross-sectional view along the x2-x2 direction. After forming the protective sidewall 240, the first functional layer 110 in the first stacked structure 210 is removed, and the second functional layer 120 in the first stacked structure 210 is used as the first channel layer 330.

[0105] The first channel layer 330 is used to provide a conductive channel for the first device structure.

[0106] In this embodiment, since the protective sidewall 240 is formed on the sidewalls of the second stacked structure 220, the second stacked structure 220 is not easily damaged during the process of removing the first functional layer 110 in the first stacked structure 210.

[0107] In this embodiment, through the bottom gate opening 250, the first functional layer 110 in the first stacked structure 210 is removed. In this embodiment, an isotropic etching process is used to remove the first functional layer 110 in the first stacked structure 210. The isotropic etching process has the characteristic of isotropic etching, which is beneficial to completely remove the first functional layer 110 in the first stacked structure 210 and prevent residues from occurring in the first functional layer 110 in the first stacked structure 210.

[0108] Specifically, the isotropic etching process is a wet etching process, and the etching solution for the wet etching process is an HCl solution. The HCl solution has a high etching selectivity for SiGe and Si, and a fast etching rate, which can further reduce the probability of mis-etching the first channel layer 330. In other embodiments, the isotropic etching process may also use HCl vapor to remove the first functional layer in the first stacked structure.

[0109] In this embodiment, after removing the first functional layer 110 in the first stacked structure 210, along the transverse direction, first source / drain doping layers 310 are formed at both ends of the first channel layer 330, so that the first channel layer 330 can be spaced and suspended in the bottom gate opening 250, facilitating the subsequent formation of the bottom gate surrounding the first channel layer 330.

[0110] In this embodiment, after removing the first functional layer 110 in the first stacked structure 210, one or more first channel layers 330 arranged at intervals constitute a first channel structure layer, and the first channel structure layer is located on the substrate 100 and is spaced from the substrate 100.

[0111] Specifically, after removing the first functional layer 110 in the first stacked structure 210, a first through groove 260 is formed between adjacent first channel layers 330, or between the first channel layer 330 and the substrate 100, or between the first channel layer 330 and the second stacked structure 220, and is connected to the bottom gate opening 250.

[0112] Reference Figure 17 , Figure 17 (a) is a longitudinal sectional view at the top gate opening 230, Figure 17 (b) is Figure 17 (a) a sectional view along the x1 - x1 direction, Figure 17 (c) is Figure 17 (a) a sectional view along the x2 - x2 direction, forming a bottom gate 340 surrounding the first channel layer 330, and the bottom gate 340 and the first channel layer 330 are used to form a first device structure 300.

[0113] Specifically, the bottom gate 340, the first channel layer 330, the first source / drain doping layer 310, and the bottom dielectric layer 320 are used to form the first device structure 300.

[0114] The first device structure 300 is used to form a first-type MOS transistor. In this embodiment, the first device structure 300 is used to form an NMOS transistor. In other embodiments, the first device structure may also be used to form a PMOS transistor.

[0115] The bottom gate 340 is used to control the opening and closing of the conductive channel of the first-type MOS transistor.

[0116] In this embodiment, the bottom gate 340 is a metal gate structure, and the bottom gate 340 includes a first work function layer (not shown in the figure) and a first metal gate electrode layer located on the first work function layer.

[0117] The first work function layer is used to adjust the work function of the bottom gate 340. In this embodiment, the first device structure 300 is used to form an NMOS transistor, and the material of the first work function layer is an N-type work function material.

[0118] The first metal gate electrode layer is used as an electrode to lead out the electrical property of the bottom gate 340, so as to establish an electrical connection between the bottom gate 340 and an external circuit or other structures. The material of the first metal gate electrode layer is a metal material.

[0119] In this embodiment, the bottom gate 340 is formed in the bottom gate opening 250. Specifically, the bottom gate 340 fills the bottom gate opening 250 and the first through groove 260.

[0120] The part of the bottom gate 340 located between adjacent first channel layers 330, or between the first channel layer 330 and the substrate 100, or between the first channel layer 330 and the second stacked structure 220 is used as the first part 340(1) of the bottom gate. The bottom gate 340 located along the longitudinal direction on both sides of the first channel structure layer and covering the sidewalls of the first channel structure layer is used as the second part 340(2) of the bottom gate. Specifically, the first part 340(1) of the bottom gate is located in the first through groove 260, and the second part 340(2) of the bottom gate is located in the bottom gate opening 250.

[0121] In this embodiment, the steps of forming the bottom gate 340 include: forming an initial bottom gate (not shown in the figure) in the bottom gate opening 250 and the top gate opening 230, the initial bottom gate surrounding the first channel layer 330 and covering the sidewalls of the second stacked structure 220; removing the initial bottom gate located in the top gate opening 230.

[0122] Specifically, a bottom gate material layer is filled in the bottom gate opening 250, the top gate opening 230, and the first through groove 260, and the bottom gate material layer also covers the top dielectric layer 420; a planarization process is used to remove the bottom gate material layer higher than the top surface of the top dielectric layer 420 to form the initial bottom gate.

[0123] In this embodiment, a dry etching process is used to remove the initial bottom gate located in the top gate opening 230.

[0124] It should be noted that in this embodiment, before forming the initial bottom gate, the forming method further includes: forming a bottom gate dielectric layer 350 on the sidewalls of the top gate opening 230, as well as on the sidewalls and bottom of the bottom gate opening 250, and the bottom gate dielectric layer 350 also surrounds the first channel layer 330, the sidewalls and top of the second stacked structure 220 exposed by the top gate opening 230, and the bottom wall of the second stacked structure 220 exposed by the first through groove 260.

[0125] The bottom gate dielectric layer 350 is used to electrically isolate the bottom gate 340 from the first channel layer 330.

[0126] In this embodiment, the bottom gate dielectric layer 350 is a high-k gate dielectric layer, and the material of the bottom gate dielectric layer 340 is a high-k dielectric material.

[0127] After removing the initial bottom gate located in the top gate opening 230, it further includes: removing the bottom gate dielectric layer 350 located on the top, sidewalls and bottom wall of the second stacked structure 220, and the sidewalls of the top gate opening 230, so as to expose the second stacked structure 220, facilitating the subsequent removal of the second functional layer 120 in the second stacked structure 220.

[0128] Reference Figure 18 , Figure 18 (a) is a longitudinal sectional view at the top gate opening 230, Figure 18 (b) is Figure 18 (a) a cross-sectional view along the x1-x1 direction, Figure 18 (c) is Figure 18 (a) a cross-sectional view along the x2-x2 direction. After forming the bottom gate 340, the protective sidewall 240 is removed to expose the top surface and sidewalls of the second stacked structure 220. Exposing the top surface and sidewalls of the second stacked structure 220 facilitates the removal of the second functional layer 120 in the second stacked structure 220.

[0129] In this embodiment, an isotropic etching process is used to remove the protective sidewall 240.

[0130] Reference Figure 19 , Figure 19 (a) is a longitudinal sectional view at the top gate opening 230, Figure 19 (b) is Figure 19 (a) a cross-sectional view along the x1-x1 direction, Figure 19 (c) is Figure 19 (a) a cross-sectional view along the x2-x2 direction. After removing the second functional layer 120 in the second stacked structure 220, the first functional layer 110 in the second stacked structure 220 is used as the second channel layer 430.

[0131] The second channel layer 430 is used to provide a conductive channel for the second device structure.

[0132] In this embodiment, the first functional layer 110 in the first stacked structure 210 and the second functional layer 120 in the second stacked structure 220 are removed in different steps respectively. During the process of removing the first functional layer 110 in the first stacked structure 210 and the second functional layer 120 in the second stacked structure 220, only an etching selectivity is required between the first functional layer 110 and the second functional layer 120, which is beneficial to reducing the process difficulty of removing the first functional layer 110 in the first stacked structure 210 and removing the second functional layer 120 in the second stacked structure 220.

[0133] In addition, in this embodiment, after forming the bottom gate 340, the second functional layer 120 in the second stacked structure 220 is removed. Since the bottom gate 340 surrounds the first channel layer 330, it is beneficial to prevent the first channel layer 330 from being damaged during the process of removing the second functional layer 120 in the second stacked structure 220, and correspondingly ensure the integrity and formation quality of the second channel layer 430.

[0134] In summary, in this embodiment, the second functional layer 120 in the first stacked structure 210 is respectively retained as the first channel layer 330, and the first functional layer 110 in the second stacked structure 220 is retained as the second channel layer 430, so that different channel layers can be formed for the first device structure and the second device structure, and it is beneficial to reduce the probability of damage to the first channel layer 330 and the second channel layer 430, and ensure the formation quality of the first channel layer 330 and the second channel layer 430, thereby improving the performance of the complementary field effect transistor (CFET).

[0135] In this embodiment, an isotropic etching process is used to remove the second functional layer 120 in the second stacked structure 220. The isotropic etching process has the characteristics of isotropic etching, which is beneficial to removing the second functional layer 120 in the second stacked structure 220 completely and preventing residues from being generated during the removal of the second functional layer 120 in the second stacked structure 220.

[0136] Specifically, the isotropic etching process is a wet etching process, and the etching solution of the wet etching process is a TMAH solution. The TMAH solution has a high etching selectivity between Si and SiGe and a fast etching rate, which can further reduce the probability of mis-etching the second channel layer 430.

[0137] In this embodiment, after removing the second functional layer 120 from the second stacked structure 220, second source-drain doping layers 410 are formed at both ends of the second channel layer 430 along the transverse direction, so that the second channel layer 430 can be spaced and suspended in the top gate opening 230, facilitating the subsequent formation of a top gate surrounding the second channel layer 430.

[0138] In this embodiment, after removing the second functional layer 120 from the second stacked structure 220, one or more second channel layers 430 arranged at intervals form a second channel structure layer, and the second channel structure layer is located on the first channel structure layer and is spaced from the first channel structure layer.

[0139] Specifically, after removing the second functional layer 120 from the second stacked structure 220, second through grooves 270 are formed between adjacent second channel layers 430, or between the second channel layer 430 and the bottom gate 340, or at the top of the second channel layer 430, and the second through grooves 270 communicate with the top gate opening 230.

[0140] Reference Figure 20 , Figure 20 (a) is a longitudinal sectional view at the top gate 440, Figure 20 (b) is Figure 20 (a) a sectional view along the x1 - x1 direction, Figure 20 (c) is Figure 20 (a) a sectional view along the x2 - x2 direction. A top gate 440 surrounding the second channel layer 430 is formed on the bottom gate 340, and the top gate 440 and the second channel layer 430 are used to form a second device structure 400.

[0141] Specifically, the top gate 440, the second channel layer 430, the second source-drain doping layers 410, and the top dielectric layer 420 are used to form the second device structure 400.

[0142] The first device structure 300 and the second device structure 400 are sequentially stacked on the substrate 100 in a direction perpendicular to the substrate 100 to form a complementary field-effect transistor (CFET), which can save area, improve transistor integration density, and is beneficial to reducing power consumption and improving cost performance.

[0143] The second device structure 400 is used to form a second-type MOS transistor, and the channel conduction type of the second-type MOS transistor is different from that of the first-type MOS transistor. In this embodiment, the second device structure 400 is used to form a PMOS transistor. In other embodiments, when the first device structure is used to form a PMOS transistor, the second device structure is used to form an NMOS transistor.

[0144] The top gate 440 is used to control the opening and closing of the conductive channel of the type-II MOS transistor.

[0145] In this embodiment, the top gate 440 is a metal gate structure, and the top gate 440 includes a second work function layer (not shown in the figure) and a second metal gate electrode layer located on the second work function layer.

[0146] The second work function layer is used to adjust the work function of the top gate 440. In this embodiment, the second device structure 400 is used to form a PMOS transistor, and the material of the second work function layer is a P-type work function material.

[0147] The second metal gate electrode layer is used as an electrode to lead out the electrical property of the top gate 440, so as to establish an electrical connection between the top gate 440 and an external circuit or other structures. The material of the second metal gate electrode layer is a metal material.

[0148] In this embodiment, the top gate 440 is formed in the top gate opening 230. Specifically, the top gate 440 fills the top gate opening 230 and the second through groove 270.

[0149] The part of the top gate 440 located between adjacent second channel layers 430, or located between the second channel layer 430 and the bottom gate 340, or located at the top of the second channel layer 430 is used as the first part 440(1) of the top gate. The top gate 440 that straddles the second channel structure layer and the first part 440(1) of the top gate and covers the top and side walls of the second channel structure layer is used as the second part 440(2) of the top gate. Specifically, the first part 440(1) of the top gate is located in the second through groove 270, and the second part 440(2) of the top gate is located in the top gate opening 230.

[0150] In this embodiment, along the transverse direction, the side wall of the first part 440(1) of the top gate is indented relative to the side wall of the same side of the first part 340(1) of the bottom gate.

[0151] It should be noted that the forming method further includes: after removing the second functional layer 120 in the second stacked structure 220 and before forming the top gate 440, a gate dielectric layer 450 surrounding the second channel layer 430 is formed, and the gate dielectric layer 450 is also formed on the bottom gate 340.

[0152] The gate dielectric layer 450 serves as the top gate dielectric layer 450, which is used to achieve electrical isolation between the top gate 440 and the second channel layer 430, and is also used to achieve electrical isolation between the top gate 440 and the bottom gate 340.

[0153] In this embodiment, the top gate dielectric layer 450 is a high-k gate dielectric layer, and the material of the top gate dielectric layer 450 is a high-k dielectric material.

[0154] Reference Figure 21 , in this embodiment, the forming method further includes: after forming the top gate 440, forming an interconnect structure 470 to electrically connect the top gate 440 and the bottom gate 340.

[0155] Electrically connecting the top gate 440 and the bottom gate 340, so that the first device structure 300 and the second device structure 400 are used in cooperation to form a complementary field effect transistor.

[0156] In this embodiment, the step of forming the interconnect structure 470 includes: as Figure 21 (a) shows, forming a conductive via 460 that penetrates the top gate 440, the top gate dielectric layer 450, and a part of the thickness of the bottom gate 340; as Figure 21 (b) shows, filling the interconnect structure 470 in the conductive via 460.

[0157] Specifically, the interconnect structure 470 penetrates the second part 440(2) of the top gate, the top gate dielectric layer 450, and a part of the thickness of the second part 340(2) of the bottom gate.

[0158] Correspondingly, the present invention also provides a semiconductor structure. Figure 20 The structural schematic diagram of an embodiment of the semiconductor structure of the present invention is shown. Figure 20 (a) is a longitudinal sectional view at the top gate 440, Figure 20 (b) is Figure 20 a sectional view of (a) along the x1-x1 direction, Figure 20 (c) is Figure 20 a sectional view of (a) along the x2-x2 direction,

[0159] In this embodiment, the semiconductor structure includes: a substrate 100; a first device structure 300 located on the substrate 100, and the first device structure 300 includes: a first channel structure layer located on the substrate 100 and spaced apart from the substrate 100, and the first channel structure layer includes one or more first channel layers 330 spaced apart from each other; a bottom gate 340 surrounding the first channel layer 330; a second device structure 400 located on the first device structure 300, including: a second channel structure layer located on the first channel structure layer and spaced apart from the first channel structure layer, and the second channel structure layer includes one or more second channel layers 430 spaced apart from each other, the material of the second channel layer 430 is different from that of the first channel layer 330, the first channel layer 330 and the second channel layer 430 extend in the lateral direction, and the direction parallel to the substrate 100 and perpendicular to the lateral direction is the longitudinal direction; a top gate 440 located on the bottom gate 340 and surrounding the second channel layer 430.

[0160] In this embodiment, different channel layers are formed for the first device structure 300 and the second device structure 400 respectively, improving the performance of the complementary field effect transistor (CFET).

[0161] The substrate 100 is used to provide a process platform for the formation of the complementary field effect transistor. In this embodiment, the substrate 100 is a silicon substrate.

[0162] In this embodiment, the semiconductor structure further includes: a trench isolation structure 105 located in the substrate 100 exposed by the first channel structure layer. The trench isolation structure 105 is used to achieve electrical isolation between the substrate 100 and the bottom gate 340, and is also used to isolate adjacent first channel structure layers.

[0163] In this embodiment, the trench isolation structure 105 is a shallow trench isolation structure (STI), and the material of the trench isolation structure 105 is silicon oxide.

[0164] The first device structure 300 is used to form a first-type MOS transistor. In this embodiment, the first device structure 300 is used to form an NMOS transistor. In other embodiments, the first device structure can also be used to form a PMOS transistor.

[0165] The first channel structure layer is used to provide a conductive channel for the first device structure 300. Specifically, the first channel layer 330 is used to provide a conductive channel for the first device structure 300.

[0166] In this embodiment, the first device structure 300 is used to form an NMOS transistor. The material of the first channel layer 330 is Si, so that an Si channel is adopted for the NMOS, which is beneficial to improving the performance of the NMOS transistor. In other embodiments, the first device structure is used to form a PMOS transistor, and the material of the first channel layer is SiGe, so that an SiGe channel is adopted for the PMOS, which is beneficial to improving the performance of the PMOS transistor.

[0167] As an example, the number of the first channel layers 330 is one. In other embodiments, the number of the first channel layers may also be greater than or equal to two.

[0168] The bottom gate 340 is used to control the opening and closing of the conductive channel of the first-type MOS transistor.

[0169] In this embodiment, the bottom gate 340 is a metal gate structure. The bottom gate 340 includes a first work function layer (not shown in the figure) and a first metal gate electrode layer located on the first work function layer.

[0170] The first work function layer is used to adjust the work function of the bottom gate 340. In this embodiment, the first device structure 300 is used to form an NMOS transistor, and the material of the first work function layer is an N-type work function material.

[0171] The first metal gate electrode layer is used as an electrode to lead out the electric property of the bottom gate 340, so as to establish an electrical connection between the bottom gate 340 and an external circuit or other structures. The material of the first metal gate electrode layer is a metal material.

[0172] In this embodiment, the part of the bottom gate 340 located between adjacent first channel layers 330, or between the first channel layer 330 and the substrate 400, or between the first channel layer 330 and the top gate 440 is used as the first part 340(1) of the bottom gate. The bottom gate 340 located along the longitudinal direction on both sides of the first channel structure layer and covering the side walls of the first channel structure layer is used as the second part 340(2) of the bottom gate.

[0173] In this embodiment, the semiconductor structure further includes: a bottom gate dielectric layer 350, located between the first channel layer 330 and the bottom gate 340, and between the bottom gate 340 and the substrate 100.

[0174] The bottom gate dielectric layer 350 is used to electrically isolate the bottom gate 340 from the first channel layer 330.

[0175] In this embodiment, the bottom gate dielectric layer 350 is a high-k gate dielectric layer, and the material of the bottom gate dielectric layer 340 is a high-k dielectric material.

[0176] In this embodiment, the first device structure 300 further includes: a first source / drain doping layer 310, which is located on both sides of the bottom gate 340 along the transverse direction and covers the sidewalls of the first channel structure layer; and a bottom dielectric layer 320, which covers the sidewalls of the bottom gate 340 and the first source / drain doping layer 310.

[0177] The first source / drain doping layer 310 is used as the source region or drain region of the first device structure 300.

[0178] In this embodiment, the first device structure is used to form an NMOS transistor, and the first source / drain doping layer 310 is N-type doped. Specifically, the first source / drain doping layer 310 includes a stress layer doped with N-type ions, and the stress layer is used to provide tensile stress for the channel of the NMOS transistor to improve the mobility of electrons.

[0179] In other embodiments, when the first device structure is used to form a PMOS transistor, the first source / drain doping layer is P-type doped. Specifically, the first source / drain doping layer includes a stress layer doped with P-type ions.

[0180] In this embodiment, an example is given where the first source / drain doping layer 310 covers the substrate 100 along the transverse direction. In other embodiments, a part of the substrate may also be exposed along the transverse direction of the first source / drain doping layer.

[0181] The bottom dielectric layer 320 is used to isolate adjacent first device structures 300, and the bottom dielectric layer 320 is also used to isolate the first device structure 300 from the second device structure 400 in the direction perpendicular to the substrate 100. The bottom dielectric layer 320 is an interlayer dielectric layer (ILD). In this embodiment, the material of the bottom dielectric layer 320 is silicon oxide.

[0182] In this embodiment, the bottom dielectric layer 320 and the bottom gate 340 are located on the trench isolation structure 105.

[0183] In this embodiment, the semiconductor structure further includes: a first inner sidewall 180, which is located between the first part 340(1) of the bottom gate and the first source / drain doping layer 310, and between the first part 340(1) of the bottom gate and the bottom dielectric layer 320 along the transverse direction.

[0184] The first inner sidewall 180 is used to isolate the first part 340(1) of the bottom gate from the first source / drain doping layer 310. The material of the first inner sidewall 180 is a low-k dielectric material or an ultra-low-k dielectric material, which is beneficial to reducing the coupling capacitance between the first part 340(1) of the bottom gate and the first source / drain doping layer 310.

[0185] In this embodiment, the semiconductor structure further includes: a mask sidewall 150 located between the sidewall 340(2) of the second part of the bottom gate and the bottom dielectric layer 320.

[0186] The semiconductor structure includes the mask sidewall 150 because the formation steps of the semiconductor structure include: etching the second stacked structure on both sides of the dummy gate to form a top groove, forming the mask sidewall 150 on the sidewall of the top groove, and the mask sidewall 150 is also formed on the sidewall of the dummy gate. Then, using the dummy gate and the mask sidewall 150 as masks to etch the first stacked structure to form a bottom groove. After forming the first source / drain doping layer 310 in the bottom groove, the bottom dielectric layer 430 covering the first source / drain doping layer 310 is formed. The step of forming the bottom dielectric layer 430 includes the process of removing the dielectric material layer higher than the top surface of the first stacked structure. The mask sidewall 150 located on the partial sidewall of the dummy gate is retained under the coverage of the bottom dielectric layer 430.

[0187] Among them, the mask sidewall 150 is used as a mask for etching the first stacked structure to form the bottom groove, and the mask sidewall 150 correspondingly defines the position of the first source / drain doping layer 310.

[0188] The material of the mask sidewall 150 can be silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride or silicon carbon oxynitride. In this embodiment, the material of the mask sidewall 150 is silicon carbide.

[0189] The first device structure 300 and the second device structure 400 are sequentially stacked on the substrate 100 in a direction perpendicular to the substrate 100 to form a complementary field-effect transistor (CFET), which can save area, improve the transistor integration density, and is beneficial to reducing power consumption and improving cost performance.

[0190] The second device structure 400 is used to form a second-type MOS transistor, and the channel conduction type of the second-type MOS transistor is different from that of the first-type MOS transistor. In this embodiment, the second device structure 400 is used to form a PMOS transistor. In other embodiments, when the first device structure is used to form a PMOS transistor, the second device structure is used to form an NMOS transistor.

[0191] The second channel structure layer is used to provide the channel of the second-type MOS transistor. Specifically, the second channel layer 430 is used to provide the channel of the second-type MOS transistor.

[0192] In this embodiment, the second device structure 400 is used to form a PMOS transistor, and the material of the second channel layer 430 is SiGe. Therefore, using a SiGe channel for the PMOS is beneficial to improving the performance of the PMOS transistor and correspondingly improving the performance of the CFET device.

[0193] In other embodiments, when the second device structure is used to form an NMOS transistor, the material of the second channel layer is Si, so that an Si channel is adopted for the NMOS, which is beneficial to improving the performance of the NMOS transistor and the NMOS transistor.

[0194] In this embodiment, the number of the second channel layers 430 is two. In other embodiments, the number of the second channel layers may also be one or greater than two.

[0195] In this embodiment, since the formation step of the semiconductor structure includes: etching the second stacked structure on both sides of the dummy gate to form a top groove, forming a mask sidewall 150 on the sidewall of the top groove, and then etching the first stacked structure with the dummy gate and the mask sidewall 150 as a mask to form a bottom groove, and forming the first source / drain doping layer 310 in the bottom groove, so that along the transverse direction, the end of the second channel layer 430 is indented relative to the end of the same side of the first channel layer 330.

[0196] Specifically, along the transverse direction, the size of the indentation of the end of the second channel layer 430 relative to the end of the same side of the first channel layer 330 is the thickness of the mask sidewall 150.

[0197] The top gate 440 is used to control the opening and closing of the conductive channel of the second-type MOS transistor.

[0198] In this embodiment, the top gate 440 is a metal gate structure, and the top gate 440 includes a second work function layer (not shown in the figure) and a second metal gate electrode layer located on the second work function layer.

[0199] The second work function layer is used to adjust the work function of the top gate 440. In this embodiment, the second device structure 400 is used to form a PMOS transistor, and the material of the second work function layer is a P-type work function material.

[0200] The second metal gate electrode layer is used as an electrode to lead out the electrical property of the top gate 440, so as to establish an electrical connection between the top gate 440 and an external circuit or other structures. The material of the second metal gate electrode layer is a metal material.

[0201] The part of the top gate 440 located between adjacent second channel layers 430, or located between the second channel layer 430 and the bottom gate 340, or located on the top of the second channel layer 430 is used as the first part 440(1) of the top gate, and the top gate 440 that straddles the second channel structure layer and the first part 440(1) of the top gate and covers the top and sidewalls of the second channel structure layer is used as the second part 440(2) of the top gate.

[0202] In this embodiment, along the transverse direction, the sidewall of the first part 440(1) of the top gate is indented relative to the sidewall of the same side of the first part 340(1) of the bottom gate.

[0203] In this embodiment, the semiconductor structure further includes: a gate dielectric layer 450, which is located between the bottom gate 340 and the top gate 440, and between the top gate 440 and the second channel layer 430.

[0204] The gate dielectric layer 450, as the top gate dielectric layer 450, is used to achieve electrical isolation between the top gate 440 and the second channel layer 430, and is also used to achieve electrical isolation between the top gate 440 and the bottom gate 340.

[0205] In this embodiment, the top gate dielectric layer 450 is a high-k gate dielectric layer, and the material of the top gate dielectric layer 450 is a high-k dielectric material.

[0206] In this embodiment, the second device structure 400 further includes: a second source / drain doping layer 410, which is located on both sides of the top gate 440 along the transverse direction and covers the sidewalls of the second channel structure layer, and the second source / drain doping layer 410 is located on the bottom dielectric layer 320; a top dielectric layer 420, which is located on the second source / drain doping layer 410 and covers the sidewall of the top gate 440.

[0207] The second source / drain doping layer 410 is used as the source region or drain region of the second device structure 400.

[0208] In this embodiment, the second device structure 400 is used to form a PMOS transistor, and the second source / drain doping layer 410 is P-type doped. Specifically, the second source / drain doping layer 410 includes a stress layer doped with P-type ions, and the stress layer is used to provide compressive stress for the channel of the PMOS transistor to improve the mobility of holes.

[0209] In other embodiments, when the second device structure is used to form an NMOS transistor, the second source / drain doping layer is N-type doped. Specifically, the second source / drain doping layer includes a stress layer doped with N-type ions.

[0210] As an example, along the transverse direction, the top surface of a part of the bottom dielectric layer 320 above the first source / drain doping layer 310 is also exposed on both sides of the second source / drain doping layer 410, and the sidewall of the second source / drain doping layer 410 along the transverse direction is indented relative to the sidewall of the same side of the first source / drain doping layer 310. In other embodiments, the second source / drain doping layer may also cover the bottom dielectric layer located above the first source / drain doping layer.

[0211] The top dielectric layer 420 is used to achieve isolation between adjacent second device structures. The top dielectric layer 420 is an interlayer dielectric layer (ILD). In this embodiment, the material of the top dielectric layer 420 is silicon oxide.

[0212] In this embodiment, the semiconductor structure further includes: a second inner sidewall 190, which is located laterally between the first part 440(1) of the top gate and the second source / drain doping layer 410, and between the first part 440(1) of the top gate and the top dielectric layer 420.

[0213] The second inner sidewall 190 is used to isolate the first part 440(1) of the top gate from the second source / drain doping layer 410. The material of the second inner sidewall 190 is a low-k dielectric material or an ultra-low-k dielectric material to reduce the coupling capacitance between the first part 440(1) of the top gate and the second source / drain doping layer 410.

[0214] The semiconductor structure further includes: a gate sidewall 135, which is located between the first part 340(1) of the bottom gate and the mask sidewall 150, and between the first part 440(1) of the top gate and the top dielectric layer 420.

[0215] The gate sidewall 135 is used to protect the sidewalls of the first part 340(1) of the bottom gate and the first part 440(1) of the top gate. The gate sidewall 135 is also used to define the position of the second source / drain doping layer 410. As an example, the gate sidewall 135 is a single-layer structure, and the material of the gate sidewall 135 is silicon nitride.

[0216] The semiconductor structure can be formed by the forming method described in the foregoing embodiment, or can be formed by other forming methods. For the specific description of the semiconductor structure in this embodiment, reference can be made to the corresponding description in the foregoing embodiment, and details are not repeated herein.

[0217] Refer to Figure 21 (b), Figure 21 (b) is a cross-sectional view along the lateral direction at the second part 440(2) of the top gate, showing a schematic structural diagram of another embodiment of the semiconductor structure of the present invention. The same parts of this embodiment and the foregoing embodiment are not repeated herein. The differences between this embodiment and the foregoing embodiment are as follows:

[0218] In this embodiment, the semiconductor structure further includes: an interconnect structure 470, which electrically connects the top gate 440 and the bottom gate 340. By electrically connecting the top gate 440 and the bottom gate 340, the first device structure 300 and the second device structure 400 are used in cooperation to form a complementary metal-oxide-semiconductor field-effect transistor.

[0219] Specifically, the interconnect structure 470 penetrates through the second part of the top gate 440(2), the top gate dielectric layer 450, and the second part of the bottom gate 340(2) with a partial thickness.

[0220] The semiconductor structure can be formed by the formation method described in the foregoing embodiments, or can be formed by other formation methods. For a specific description of the semiconductor structure in this embodiment, reference can be made to the corresponding description in the foregoing embodiments, and details are not repeated herein.

[0221] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be subject to the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, comprising: providing a substrate; forming a stacked structure on the substrate, including a plurality of first functional layers and second functional layers alternately stacked from bottom to top in sequence. One second functional layer and the first functional layer located on the second functional layer are used to form a channel stack. The first functional layer closest to the substrate serves as the bottom functional layer, and the second functional layer farthest from the substrate serves as the top functional layer; the bottom functional layer and one or more of the channel stacks located on the bottom functional layer are used to form a first stacked structure, and the remaining channel stacks located on the first stacked structure and the top functional layer are used to form a second stacked structure; forming a protective sidewall on the sidewalls of the second stacked structure; after forming the protective sidewall, removing the first functional layer in the first stacked structure, so that the second functional layer in the first stacked structure is used as a first channel layer; forming a bottom gate surrounding the first channel layer, and the bottom gate and the first channel layer are used to form a first device structure; after forming the bottom gate, removing the protective sidewall to expose the top surface and sidewalls of the second stacked structure; removing the second functional layer in the second stacked structure, so that the first functional layer in the second stacked structure is used as a second channel layer; forming a top gate surrounding the second channel layer on the bottom gate, and the top gate and the second channel layer are used to form a second device structure.

2. The method for forming a semiconductor structure according to claim 1, characterized in that, the material of the first functional layer is SiGe, the material of the second functional layer is Si, the first device structure is used to form an NMOS transistor, and the second device structure is used to form a PMOS transistor; alternatively, the material of the first functional layer is Si, the material of the second functional layer is SiGe, the first device structure is used to form a PMOS transistor, and the second device structure is used to form an NMOS transistor.

3. The method for forming a semiconductor structure according to claim 1, characterized in that, after forming the stacked structure and before forming the protective sidewall, the method for forming the semiconductor structure further includes: forming a dummy gate across the stacked structure, the dummy gate covering a part of the top and part of the sidewalls of the stacked structure; removing the dummy gate higher than the top surface of the first stacked structure to form a top gate opening, exposing the top surface and sidewalls of the second stacked structure; the protective sidewall is formed on the sidewalls of the second stacked structure exposed by the top gate opening; after forming the protective sidewall and before removing the first functional layer in the first stacked structure, the method for forming the semiconductor structure further includes: removing the remaining dummy gate to form a bottom gate opening located below the top gate opening, exposing the sidewalls of the first stacked structure; through the bottom gate opening, removing the first functional layer in the first stacked structure; the bottom gate is formed in the bottom gate opening; the top gate is formed in the top gate opening.

4. The method for forming a semiconductor structure as described in claim 3, wherein, the step of forming the bottom gate includes: forming an initial bottom gate in the bottom gate opening and the top gate opening, the initial bottom gate surrounding the first channel layer and covering the sidewalls of the second stacked structure; removing the initial bottom gate located in the top gate opening.

5. The method for forming a semiconductor structure as described in claim 3, wherein, along the extending direction of the first functional layer and the second functional layer, the width of the dummy gate is a first width; in the step of forming the protective sidewall, the thickness of the protective sidewall is 5% to 30% of the first width.

6. The method for forming a semiconductor structure as described in claim 3, wherein, after forming the dummy gate and before removing the dummy gate above the top surface of the first stacked structure, the method for forming the semiconductor structure further includes: forming a first source / drain doping layer in the first stacked structure on both sides of the dummy gate, a bottom dielectric layer on the first source / drain doping layer, a second source / drain doping layer in the second stacked structure on both sides of the dummy gate, and a top dielectric layer on the second source / drain doping layer, the bottom dielectric layer covering a part of the sidewall of the dummy gate, and the top dielectric layer being located on the bottom dielectric layer and covering the sidewall of the dummy gate exposed by the bottom dielectric layer; in the step of forming the bottom gate, the bottom gate, the first channel layer, the first source / drain doping layer, and the bottom dielectric layer are used to form the first device structure; in the step of forming the top gate, the top gate, the second channel layer, the second source / drain doping layer, and the top dielectric layer are used to form the second device structure.

7. The method for forming a semiconductor structure as described in claim 6, wherein, the steps of forming the first source / drain doping layer, the bottom dielectric layer, the second source / drain doping layer, and the top dielectric layer include: forming a top groove in the second stacked structure on both sides of the dummy gate; forming a mask sidewall on the sidewall of the second stacked structure exposed by the top groove; forming the first source / drain doping layer in the first stacked structure on both sides of the dummy gate and the mask sidewall; forming the bottom dielectric layer on the first source / drain doping layer, exposing the mask sidewall located on the sidewall of the second stacked structure; after forming the bottom dielectric layer, removing the mask sidewall located on the sidewall of the second stacked structure; forming the second source / drain doping layer in the top groove; forming the top dielectric layer on the second source / drain doping layer.

8. The method for forming a semiconductor structure as described in claim 7, wherein, the step of forming the first source / drain doping layer includes: forming a bottom groove in the first stacked structure on both sides of the dummy gate and the mask sidewall, which is connected to the top groove; forming the first source / drain doping layer in the bottom groove.

9. The method for forming a semiconductor structure as described in claim 8, wherein, The method for forming the semiconductor structure further includes: after forming the bottom groove and before forming the first source / drain doping layer, etching the first functional layer in the first stacked structure along the extending direction of the first functional layer, so that the first functional layer of the first stacked structure and the adjacent second functional layer enclose a first trench; Forming a first inner sidewall in the first trench.

10. The method for forming the semiconductor structure according to claim 7, wherein, The method for forming the semiconductor structure further includes: after removing the mask sidewall on the sidewall of the second stacked structure and before forming the second source / drain doping layer, etching the second functional layer in the second stacked structure along the extending direction of the second functional layer, so that the second functional layer in the second stacked structure and the adjacent first functional layer enclose a second trench; forming a second inner sidewall in the second trench.

11. The method for forming the semiconductor structure according to claim 1, wherein, In the step of forming the protection sidewall, the material of the protection sidewall includes silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride or silicon carbon oxynitride.

12. The method for forming the semiconductor structure according to claim 1, wherein, The method for forming the semiconductor structure further includes: after removing the second functional layer in the second stacked structure and before forming the top gate, forming a gate dielectric layer surrounding the second channel layer, and the gate dielectric layer is also formed on the bottom gate.

13. The method for forming the semiconductor structure according to claim 1 or 12, wherein, The method for forming the semiconductor structure further includes: after forming the top gate, forming an interconnect structure to electrically connect the top gate and the bottom gate.

14. A semiconductor structure, wherein, comprising: a substrate; a first device structure located on the substrate, the first device structure includes: a first channel structure layer located on the substrate and spaced from the substrate, the first channel structure layer includes one or more spaced first channel layers; a bottom gate surrounding the first channel layer; a first source / drain doping layer located laterally on both sides of the bottom gate and covering the sidewalls of the first channel structure layer; a second device structure located on the first device structure, including: a second channel structure layer located on the first channel structure layer and spaced from the first channel structure layer, the second channel structure layer includes one or more spaced second channel layers, the material of the second channel layer is different from that of the first channel layer, the first channel layer and the second channel layer extend along the lateral direction, and the direction parallel to the substrate and perpendicular to the lateral direction is the longitudinal direction; a top gate located on the bottom gate and surrounding the second channel layer; Along the lateral direction, the end of the second channel layer is indented relative to the end of the first channel layer on the same side.

15. The semiconductor structure according to claim 14, wherein, The first device structure is used to form an NMOS transistor, the second device structure is used to form a PMOS transistor, the material of the first channel layer is Si, and the material of the second channel layer is SiGe; Alternatively, the first device structure is used to form a PMOS transistor, the second device structure is used to form an NMOS transistor, the material of the first channel layer is SiGe, and the material of the second channel layer is Si.

16. The semiconductor structure according to claim 14, wherein, the semiconductor structure further includes: a gate dielectric layer located between the bottom gate and the top gate, and between the top gate and the second channel layer.

17. The semiconductor structure according to claim 14, wherein, the part of the bottom gate located between adjacent first channel layers, or between the first channel layer and the substrate, or between the first channel layer and the top gate is used as the first part of the bottom gate; the part of the top gate located between adjacent second channel layers, or between the second channel layer and the bottom gate, or at the top of the second channel layer is used as the first part of the top gate; Along the transverse direction, the sidewall of the first part of the top gate is indented relative to the sidewall of the same side of the first part of the bottom gate.

18. The semiconductor structure according to claim 14, wherein, the first device structure further includes: a bottom dielectric layer covering the sidewall of the bottom gate and the first source / drain doping layer; the second device structure further includes: a second source / drain doping layer located on both sides of the top gate along the transverse direction and covering the sidewall of the second channel structure layer, the second source / drain doping layer is located on the bottom dielectric layer; a top dielectric layer located on the second source / drain doping layer and covering the sidewall of the top gate.

19. The semiconductor structure according to claim 18, wherein, the bottom gate located on both sides of the first channel structure layer along the longitudinal direction and covering the sidewall of the first channel structure layer is used as the second part of the bottom gate; the semiconductor structure further includes: a mask sidewall located between the sidewall of the second part of the bottom gate and the bottom dielectric layer.

20. The semiconductor structure according to claim 18, wherein, the part of the bottom gate located between adjacent first channel layers, or between the first channel layer and the substrate, or between the first channel layer and the top gate is used as the first part of the bottom gate; the part of the top gate located between adjacent second channel layers, or between the second channel layer and the bottom gate, or at the top of the second channel layer is used as the first part of the top gate; the semiconductor structure further includes: a first inner sidewall located along the transverse direction between the first part of the bottom gate and the first source / drain doping layer, and between the first part of the bottom gate and the bottom dielectric layer; a second inner sidewall located along the transverse direction between the first part of the top gate and the second source / drain doping layer, and between the first part of the top gate and the top dielectric layer.

Images