Semiconductor structure, method for preparing semiconductor structure and semiconductor device

Abstract

The present application discloses a semiconductor structure, a method for preparing the semiconductor structure, and a semiconductor device, and relates to the semiconductor field. A semiconductor structure includes a substrate and a stacking structure, the stacking structure includes a plurality of unit layer structures, each unit layer structure includes a dielectric layer, a first buffer layer, and a conductive layer, the first buffer layer is arranged between the dielectric layer and the conductive layer; the stacking structure also includes a second buffer layer, the second buffer layer is arranged between the conductive layer of one of the two adjacent unit layer structures and the dielectric layer of the other; the lattice parameters of the first buffer layer and the second buffer layer are each between the first lattice parameter and the second lattice parameter. A method for preparing a semiconductor structure, used for preparing the above-mentioned semiconductor structure. A semiconductor device includes the above-mentioned semiconductor structure. The present application can at least solve the problem of delamination between the conductive layer and the dielectric layer.

Description

Technical Field

[0001] The present application belongs to the field of semiconductor technology, and specifically relates to a semiconductor structure, a method for preparing the semiconductor structure, and a semiconductor device. Background Art

[0002] 3D NAND flash memory is an emerging type of storage that can create a storage device with a storage capacity more than three times that of planar NAND by vertically stacking multiple layers of data storage units. Currently, planar NAND flash memory has reached its expansion limit. In order to further increase the storage capacity, 3D NAND memory has been proposed. 3D NAND supports higher storage capacity in a smaller space, thereby saving costs and reducing energy consumption.

[0003] At present, the manufacturing process of some 3D NAND Flash is very complicated. The key process technologies in the manufacturing process include: trench excavation with high aspect ratio, N-type doping in source and drain, completely parallel sidewalls, many levels of stairs (or steps), uniform deposition layer on the entire wafer surface, one-step photolithography stair formation, hard mask etching, through-hole process, hole inner wall deposition process, polysilicon channel, charge trapping storage, etching of various materials, and deposition of many layers of materials. In 3D NAND, the stacking structure is the core part of the entire memory. Each stacking structure contains alternating deposited conductive layers and dielectric layers. Ensuring the continuity of the stacking structure is the most basic link.

[0004] Currently, some W / SiO 2 The stacked structure was prepared by PVD process at room temperature. 2 and W, in SiO 2 In the chamber and W chamber, SiO is repeatedly prepared using the PVD process. 2 In order to better control thermal stress, the temperature during the preparation of W and SiO films is relatively low. 2 The stress caused by the large difference in lattice constants cannot be eliminated by lowering the preparation temperature. The local stress is quite different, and there is even a phenomenon of coexistence of positive stress and negative stress. 2 Stress accumulates at the film interface, so that 2 When a stacked structure with multiple layers is formed, delamination and disconnection occur at the film interface due to the accumulation of stress, such as Figure 1 As shown, delamination occurs in the area circled by the box, which prevents the transmission of carriers between the conductive layer and the dielectric layer, thereby seriously affecting the yield of the device. Summary of the invention

[0005] The purpose of the embodiments of the present application is to provide a semiconductor structure, a method for preparing the semiconductor structure, and a semiconductor device, which can at least solve the problem of delamination between the conductive layer and the dielectric layer affecting the device yield.

[0006] In order to solve the above technical problems, this application is implemented as follows:

[0007] The embodiment of the present application provides a semiconductor structure, which is applied to a semiconductor device. The semiconductor structure includes a substrate and a stacked structure arranged on the substrate. The stacked structure includes a plurality of groups of unit layer structures stacked in layers. Each group of the unit layer structures includes a dielectric layer, a first buffer layer and a conductive layer. The first buffer layer is arranged between the dielectric layer and the conductive layer.

[0008] The stacked structure further includes a second buffer layer, which is disposed between the conductive layer of one of the two adjacent groups of the unit layer structures and the dielectric layer of the other one;

[0009] The dielectric layer has a first lattice parameter, the conductive layer has a second lattice parameter, and the first buffer layer and the second buffer layer each have a lattice parameter between the first lattice parameter and the second lattice parameter.

[0010] The present invention provides a method for preparing a semiconductor structure, the method comprising:

[0011] providing a substrate, and forming a dielectric layer having a first lattice parameter on the substrate;

[0012] forming a first buffer layer having a third lattice parameter on the dielectric layer;

[0013] forming a conductive layer having a second lattice parameter on the first buffer layer, wherein the third lattice parameter is between the first lattice parameter and the second lattice parameter, so as to form a group of unit layer structures on the substrate;

[0014] forming a second buffer layer having a fourth lattice parameter on the conductive layer, wherein the fourth lattice parameter is between the first lattice parameter and the second lattice parameter;

[0015] The unit layer structure and the second buffer layer are cyclically prepared to obtain a semiconductor structure formed by at least the substrate, a plurality of groups of the unit layer structures and a plurality of layers of the second buffer layer.

[0016] An embodiment of the present application also provides a semiconductor device, comprising the above-mentioned semiconductor structure.

[0017] In the embodiment of the present application, a first buffer layer is arranged between the dielectric layer and the conductive layer of each group of unit layer structures, and a second buffer layer is arranged between the conductive layer of one of two adjacent groups of unit layer structures and the dielectric layer of the other, so that the buffer layer and the dielectric layer and the conductive layer can have a good match with each other, thereby releasing the stress at the interface between the dielectric layer and the conductive layer, and further effectively solving the problem of stratification in the stacked structure, thereby improving the yield of semiconductor devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 W / SiO in the related technology 2 TEM (Transmission Electron Microscope) image of the stacked structure, where the box shows the delamination at the interface between W and SiO2;

[0019] Figure 2 A schematic diagram of the structure of a stacked semiconductor structure disclosed in an embodiment of the present application;

[0020] Figure 3 It is a TEM image of the semiconductor structure disclosed in the embodiment of the present application, wherein the dotted line is the buffer layer;

[0021] Figure 4 The present invention is a flow chart of a method for preparing a semiconductor structure disclosed in an embodiment of the present application.

[0022] Description of reference numerals:

[0023] 100-dielectric layer;

[0024] 200-first buffer layer;

[0025] 300-conductive layer;

[0026] 400- second buffer layer;

[0027] 500-substrate;

[0028] A-unit layer structure. DETAILED DESCRIPTION

[0029] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0030] The terms "first", "second", etc. in the specification and claims of the present application are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable under appropriate circumstances, so that the embodiments of the present application can be implemented in an order other than those illustrated or described here, and the objects distinguished by "first", "second", etc. are generally of one type, and the number of objects is not limited. For example, the first object can be one or more. In addition, "and / or" in the specification and claims represents at least one of the connected objects, and the character " / " generally indicates that the objects associated with each other are in an "or" relationship.

[0031] refer to Figure 2 and Figure 3 , the embodiment of the present application discloses a semiconductor structure, which can be applied to a semiconductor device. The semiconductor structure may include a substrate 500 and a stacked structure, and the stacked structure may be arranged on the surface of the substrate 500. Optionally, the substrate 500 may include silicon or other semiconductor wafers of different sizes and different materials, such as a 200 mm wafer, a 300 mm wafer, or a 450 mm wafer. The substrate 500 may also be a semiconductor wafer deposited with multiple layers of materials, wherein the multiple layers of materials include but are not limited to conductor materials, electrolyte materials, semiconductor materials, etc.

[0032] The stacking structure includes multiple groups of unit layer structures A and a second buffer layer 400 , wherein the multiple groups of unit layer structures A are stacked and sequentially arranged on one side surface of the substrate 500 to form a stacking structure on one side surface of the substrate 500 .

[0033] Each unit layer structure A includes a dielectric layer 100 , a first buffer layer 200 and a conductive layer 300 . The first buffer layer 200 is disposed between the dielectric layer 100 and the conductive layer 300 , so that the dielectric layer 100 is separated from the conductive layer 300 by the first buffer layer 200 .

[0034] The second buffer layer 400 is disposed between the conductive layer 300 of one of the two adjacent groups of unit layer structures A and the dielectric layer 100 of the other. Specifically, the second buffer layer 400 can be disposed between the conductive layer 300 of the first group of unit layer structures A and the dielectric layer 100 of the second group of unit layer structures A. Of course, it can also be disposed between the dielectric layer 100 of the third group of unit layer structures A and the conductive layer 300 of the second group of unit layer structures A. In this way, the two adjacent groups of unit layer structures A can be separated by the second buffer layer 400.

[0035] Furthermore, the dielectric layer 100 has a first lattice parameter, the conductive layer 300 has a second lattice parameter, and the first buffer layer 200 and the second buffer layer 400 each have a lattice parameter between the first lattice parameter and the second lattice parameter.

[0036] It should be noted here that, considering that the materials of the dielectric layer 100 and the conductive layer 300 are different, the first lattice parameter and the second lattice parameter are quite different, and because of factors such as the relatively high film preparation temperature, a large stress is generated at the interface between the dielectric layer 100 and the conductive layer 300 in the formed stacked structure. The large stress will cause stratification at the interface between the dielectric layer 100 and the conductive layer 300.

[0037] In the embodiment of the present application, a first buffer layer 200 is arranged between the dielectric layer 100 and the conductive layer 300 in a single group of unit layer structures A, and a second buffer layer 400 is arranged between the conductive layer 300 of one group of unit layer structures A and the dielectric layer 100 of the other group of unit layer structures A in two adjacent groups of unit layer structures A, and the lattice parameters of the first buffer layer 200 and the second buffer layer 400 are respectively between the first lattice parameter and the second lattice parameter, so that the first buffer layer 200 and the second buffer layer 400 each have a good match with the dielectric layer 100 and the conductive layer 300, and the stress caused by the lattice distortion at the interface between the dielectric layer 100 and the conductive layer 300 can be effectively eliminated, that is, the stress accumulation at the interface between the dielectric layer 100 and the conductive layer 300 can be released, thereby alleviating the problem of delamination between the dielectric layer 100 and the conductive layer 300 due to the large stress, which is beneficial to improving the quality of the semiconductor structure and improving the yield of semiconductor devices using the semiconductor structure.

[0038] In some embodiments, the dielectric layer 100 may include oxide, nitride or oxynitride. Further, the dielectric layer 100 may include at least one of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, an aluminum oxide layer or a titanium oxide layer. Further preferably, the dielectric layer 100 may be a silicon dioxide layer.

[0039] The conductive layer 300 may include a metal material. Further, the conductive layer 300 may include at least one of a tungsten layer, a titanium layer, a tantalum layer, a copper layer, a nickel layer or a molybdenum layer. Further preferably, the conductive layer 300 may be a tungsten layer.

[0040] In addition, the first buffer layer 200 and the second buffer layer 400 may be made of the same material, and may include at least one element in the dielectric layer 100 and at least one element in the conductive layer 300. Further preferably, the first buffer layer 200 and the second buffer layer 400 are both tungsten silicide layers. In this case, the third lattice parameter is the same as the first lattice parameter.

[0041] Of course, the first buffer layer 200 and the second buffer layer 400 may also be made of different materials as long as the requirements are met. In this case, the third lattice parameter is different from the first lattice parameter.

[0042] Based on the above-mentioned configuration, in the stacked semiconductor structure in the embodiment of the present application, the silicon dioxide layer exists as the dielectric layer 100, the tungsten layer exists as the conductive layer 300, the silicon dioxide layer and the tungsten layer constitute the main body of the semiconductor structure, and the tungsten silicide layer exists as the first buffer layer 200 and the second buffer layer 400. It can be seen that the tungsten silicide layer includes both the silicon element in the silicon dioxide layer and the tungsten element in the tungsten layer. In this way, the lattice of the tungsten silicide layer can have a good match with the tungsten layer and the silicon dioxide layer, which can help alleviate the problem of lattice distortion caused by large lattice differences, and further, help reduce the stress at the interface.

[0043] In order to further improve the matching degree between the tungsten silicide layer and the tungsten layer and the silicon dioxide layer, the ratio of tungsten element to silicon element in the tungsten silicide layer can be appropriately changed. In some embodiments, the atomic percentage of silicon in the tungsten silicide layer is 50% to 80%, and can specifically include 50%, 55%, 60%, 65%, 70%, 75% and 80%, etc., and of course, it can also be other atomic percentages. Based on this, the stress at the interface between the tungsten layer and the silicon dioxide layer can be reduced to a certain extent, thereby effectively alleviating the occurrence of the delamination phenomenon.

[0044] Furthermore, the atomic percentage of silicon in the tungsten silicide layer is between 60% and 70%, so that the tungsten silicide layer has good lattice matching with the tungsten layer and the silicon dioxide layer, thereby effectively preventing the occurrence of delamination caused by stress generated by lattice mismatch.

[0045] In some embodiments, the thickness of the first buffer layer 200 is several nanometers. Optionally, the thickness of the first buffer layer 200 can be 2nm to 8nm, including 2nm, 3nm, 4nm, 5nm, 6nm, 7nm and 8nm, etc., and of course other values. Based on this, it can be avoided that the spacing between the dielectric layer 100 and the conductive layer 300 in each unit layer structure A is too large to affect carrier transport.

[0046] In addition, the thickness of the second buffer layer 400 is several nanometers. Optionally, the thickness of the second buffer layer 400 can be 2nm to 8nm, including 2nm, 3nm, 4nm, 5nm, 6nm, 7nm and 8nm, etc., and of course other values. Based on this, it can be avoided that the distance between the dielectric layer 100 and the conductive layer 300 in two adjacent groups of unit layer structures A is too large to affect carrier transport.

[0047] In some embodiments, the thickness of the dielectric layer 100 is between several nanometers and tens of nanometers. Optionally, the thickness of the dielectric layer 100 can be 5nm to 80nm, including 5nm, 10nm, 20nm, 40nm, 60nm and 80nm, etc., and of course it can also be other values.

[0048] The thickness of the conductive layer 300 is between several nanometers and tens of nanometers. Optionally, the thickness of the conductive layer 300 can be 5nm to 80nm, including 5nm, 10nm, 20nm, 40nm, 60nm and 80nm, etc., and of course can also be other values.

[0049] In addition, ohmic contacts can be formed between the conductive layer 300 and the first buffer layer 200 , and between the conductive layer 300 and the second buffer layer 400 , and therefore, the conductive performance of the conductive layer 300 is not affected.

[0050] In some embodiments, the dielectric layer 100 , the conductive layer 300 , the first buffer layer 200 , and the second buffer layer 400 can be respectively formed by at least one of a physical vapor deposition (PVD) process, a chemical vapor deposition (CVD) process, or an atomic layer deposition (ALD) process.

[0051] In a more specific embodiment, the conductive layer 300 can be manufactured by a PVD process; the dielectric layer 100 can be manufactured by an ALD process, which can ensure that its flatness is maintained when ten or even hundreds of unit layer structures A are stacked; the first buffer layer 200 and the second buffer layer 400 are both manufactured by a PVD process.

[0052] refer to Figures 2 to 4 The present application also discloses a method for preparing a semiconductor structure, which is used to prepare the above-mentioned semiconductor structure. The disclosed preparation method includes:

[0053] Providing a substrate 500, and forming a dielectric layer 100 having a first lattice parameter on the substrate 500;

[0054] forming a first buffer layer 200 having a third lattice parameter on the dielectric layer 100;

[0055] Forming a conductive layer 300 having a second lattice parameter on the first buffer layer 200, wherein the third lattice parameter is between the first lattice parameter and the second lattice parameter, so as to form a unit layer structure A on the substrate 500;

[0056] forming a second buffer layer 400 having a fourth lattice parameter on the conductive layer 300, wherein the fourth lattice parameter is between the first lattice parameter and the second lattice parameter;

[0057] The unit layer structure A and the second buffer layer 400 are cyclically prepared to obtain a semiconductor structure formed of at least a substrate 500, a plurality of unit layer structures A and a plurality of second buffer layers.

[0058] Optionally, the dielectric layer 100 can be manufactured by an ALD process, specifically, a layer of silicon dioxide film is deposited on the surface of the substrate 500 by an ALD process, and the silicon dioxide film is used as the dielectric layer 100; the first buffer layer 200 can be manufactured by a PVD process, specifically, a layer of tungsten silicide film is deposited on the surface of the silicon dioxide film away from the substrate 500 by a PVD process, and the tungsten silicide film is used as the first buffer layer 200; the conductive layer 300 can be manufactured by a PVD process, specifically, a layer of tungsten film is deposited on the surface of the tungsten silicide film away from the silicon dioxide film by a PVD process, and the tungsten film is used as the conductive layer 300; the second buffer layer 400 can be manufactured by a PVD process, specifically, a layer of tungsten silicide film is deposited on the side of the tungsten film away from the tungsten silicide film by a PVD process, and the tungsten silicide film is used as the second buffer layer 400.

[0059] Based on the above process, by forming the first buffer layer 200, the stress at the interface between the dielectric layer 100 and the conductive layer 300 in each unit layer structure A can be effectively reduced, and the lattice matching degree at the interface can be improved, thereby preventing the occurrence of delamination due to lattice mismatch; by forming the second buffer layer 400, the stress at the interface between the dielectric layer 100 and the conductive layer 300 between two adjacent unit layer structures A can be effectively reduced, and the lattice matching degree at the interface can be improved, thereby preventing the occurrence of delamination due to lattice mismatch. Therefore, it is beneficial to improve the quality of the semiconductor structure and further improve the yield of semiconductor devices using the semiconductor structure.

[0060] Optionally, before providing the substrate 500, the preparation method may further include:

[0061] The substrate 500 is subjected to a degassing treatment, and after the degassing treatment is completed, the substrate 500 is subjected to a pre-cleaning treatment. Specifically, the substrate 500 can be transported to a degassing chamber for degassing treatment, so that the gas or water vapor adsorbed on the surface of the substrate 500 can be removed to prevent the gas or water vapor adsorbed on the surface of the substrate 500 from adversely affecting the dielectric layer 100 formed on the surface of the substrate 500.

[0062] Among them, the base used to support the substrate 500 in the degassing chamber can be a high-temperature base. During the process of removing impurities, a large amount of inert gas is introduced into the degassing chamber to make the degassing chamber in a high-pressure environment. In this way, the substrate 500 can reach a higher temperature in a short time, and the purpose of removing impurities can be achieved after maintaining the pressure for a period of time.

[0063] After the impurities of the substrate 500 are removed, the substrate 500 is transported to a pre-cleaning chamber, where the plasma excited by the radio frequency system bombards the surface of the substrate 500, thereby removing impurities such as organic matter or other metal compounds on the surface of the substrate 500 to ensure the cleanliness of the surface of the substrate 500 and prevent the impurities from adversely affecting the formation of the dielectric layer 100 on the surface of the substrate 500.

[0064] The preparation process of the semiconductor structure in the embodiment of the present application is as follows:

[0065] Step 1: The substrate 500 enters a degassing chamber for degassing to remove impurities on the surface of the substrate 500;

[0066] Step 2: The substrate 500 enters a pre-cleaning chamber from the degassing chamber to remove impurities on the surface of the substrate 500;

[0067] Step 3: The substrate 500 enters the silicon dioxide chamber from the pre-cleaning chamber to deposit a silicon dioxide film on the substrate 500;

[0068] Step 4, the substrate 500 enters the tungsten silicide chamber from the silicon dioxide chamber to form a tungsten silicide film on the silicon dioxide surface;

[0069] Step 5, the substrate 500 enters the tungsten chamber from the tungsten silicide chamber to form a tungsten film on the surface of the tungsten silicide;

[0070] Step 6: The substrate 500 enters a tungsten silicide chamber from a tungsten chamber to form a tungsten silicide film on the tungsten surface;

[0071] Step 7: Repeat steps 3 to 6 until a semiconductor structure with the required number of layers is prepared. It should be noted that after the semiconductor structure is prepared, the layer farthest from the substrate 500 is the conductive layer 300 .

[0072] An embodiment of the present application further discloses a semiconductor device, which includes the above-mentioned semiconductor structure or a semiconductor structure manufactured by the above-mentioned manufacturing method.

[0073] In some embodiments, the semiconductor structure may include multiple groups of unit layer structures A, such as three groups, four groups, five groups, etc., which are stacked in sequence on the substrate 500, and a second buffer layer 400 is arranged between each two adjacent groups of unit layer structures A. In this way, the substrate 500, the multiple groups of unit layer structures A and the multiple second buffer layers 400 together form a semiconductor structure. The embodiments of the present application do not specifically limit the number of unit layer structures A.

[0074] Optionally, the semiconductor device may be a 3D NAND flash memory. In addition, the semiconductor device may also be other devices, and the embodiments of the present application do not specifically limit the specific type of the semiconductor device.

[0075] To sum up, in the embodiments of the present application, a buffer layer is formed between the dielectric layer 100 and the conductive layer 300, and the buffer layer has a good match with the dielectric layer 100 and the conductive layer 300, so that the stress at the interface between the dielectric layer 100 and the conductive layer 300 can be released, thereby effectively solving the problem of stratification in the stacked structure, thereby improving the yield of semiconductor devices.

[0076] In addition, tungsten films prepared by the PVD process can have relatively excellent production capacity, and silicon dioxide films prepared by the ALD process have relatively excellent roughness. The combination of the two methods can maintain the flatness of the semiconductor structure while ensuring production capacity when stacked to dozens to hundreds of layers.

[0077] The embodiments of the present application are described above in conjunction with the accompanying drawings, but the present application is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the guidance of the present application, ordinary technicians in this field can also make many forms without departing from the purpose of the present application and the scope of protection of the claims, all of which are within the protection of the present application.

Claims

1. A semiconductor structure, applied to a semiconductor device, characterized in that: The semiconductor structure comprises a substrate (500) and a stacking structure arranged on the substrate (500), the stacking structure comprising a plurality of groups of unit layer structures (A) arranged in a stacked manner, each group of the unit layer structures (A) comprising a dielectric layer (100), a first buffer layer (200) and a conductive layer (300), the first buffer layer (200) being arranged between the dielectric layer (100) and the conductive layer (300); The stacked structure further comprises a second buffer layer (400), wherein the second buffer layer (400) is disposed between the conductive layer (300) of one of the two adjacent groups of the unit layer structures (A) and the dielectric layer (100) of the other one; The dielectric layer (100) has a first lattice parameter, the conductive layer (300) has a second lattice parameter, the first buffer layer (200) and the second buffer layer (400) each have a lattice parameter between the first lattice parameter and the second lattice parameter, and the first buffer layer (200) and the second buffer layer (400) each include at least one element in the dielectric layer (100) and at least one element in the conductive layer (300).

2. The semiconductor structure according to claim 1, characterized in that: The dielectric layer (100) comprises oxide, nitride or oxynitride, and the conductive layer (300) comprises a metal material.

3. The semiconductor structure according to claim 2, characterized in that: The dielectric layer (100) includes at least one of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, an aluminum oxide layer or a titanium oxide layer, and the conductive layer (300) includes at least one of a tungsten layer, a titanium layer, a tantalum layer, a copper layer, a nickel layer or a molybdenum layer.

4. The semiconductor structure according to claim 3, characterized in that: The dielectric layer (100) is a silicon dioxide layer, the conductive layer (300) is a tungsten layer, and the first buffer layer (200) and the second buffer layer (400) are both tungsten silicide layers.

5. The semiconductor structure according to claim 4, characterized in that: The atomic percentage of silicon in the tungsten silicide layer is 50% to 80%.

6. The semiconductor structure according to claim 1, characterized in that The lattice parameter of the first buffer layer (200) is the same as the lattice parameter of the second buffer layer (400).

7. The semiconductor structure according to claim 1, characterized in that: The thickness of the first buffer layer (200) is 2nm to 8nm; And / or, the thickness of the second buffer layer (400) is 2nm to 8nm; And / or, the thickness of the dielectric layer (100) is 5 nm to 80 nm; And / or, the thickness of the conductive layer (300) is 5 nm to 80 nm.

8. The semiconductor structure according to any one of claims 1 to 7, characterized in that: The dielectric layer (100), the conductive layer (300), the first buffer layer (200) and the second buffer layer (400) are each made by at least one of a physical vapor deposition process, a chemical vapor deposition process or an atomic layer deposition process.

9. A method for preparing a semiconductor structure, characterized in that: The preparation method comprises: Providing a substrate (500), and forming a dielectric layer (100) having a first lattice parameter on the substrate (500); forming a first buffer layer (200) having a third lattice parameter on the dielectric layer (100); forming a conductive layer (300) having a second lattice parameter on the first buffer layer (200), wherein the third lattice parameter is between the first lattice parameter and the second lattice parameter, so as to form a group of unit layer structures (A) on the substrate (500); forming a second buffer layer (400) having a fourth lattice parameter on the conductive layer (300), wherein the fourth lattice parameter is between the first lattice parameter and the second lattice parameter; The unit layer structure (A) and the second buffer layer (400) are cyclically prepared to obtain a semiconductor structure formed by at least the substrate (500), a plurality of groups of the unit layer structures (A) and a plurality of layers of the second buffer layer (400); wherein: The first buffer layer (200) and the second buffer layer (400) both include at least one element in the dielectric layer (100) and at least one element in the conductive layer (300).

10. The preparation method according to claim 9, characterized in that: Before providing the substrate (500), the preparation method further comprises: Performing a degassing treatment on the substrate (500); After the impurity removal process is completed, the substrate (500) is pre-cleaned.

11. The preparation method according to claim 9, characterized in that: The dielectric layer (100) is formed by an ALD process, the conductive layer (300) is formed by a PVD process, and the first buffer layer (200) and the second buffer layer (400) are formed by PVD processes respectively.

12. A semiconductor device, characterized in that: A semiconductor structure comprising any one of claims 1 to 8 or a semiconductor structure manufactured by the manufacturing method of any one of claims 9 to 11.

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