Silicon carbide metal oxide semiconductor field effect transistor

Abstract

A silicon carbide-metal oxide semiconductor field effect transistor. The present invention aims to suppress a decrease in withstand voltage and an increase in on-voltage and increase a body diode current. A SiC-MOSFET (101) has: a SiC substrate (1) of a first conductivity type; a drift layer (2) of the first conductivity type formed on the SiC substrate (1); a base region (3) of a second conductivity type formed in a surface layer of the drift layer (2); a source region (4) of the first conductivity type formed in a surface layer of the base region (3); a gate electrode (6) opposed to a region of the base region (3) sandwiched by the drift layer (2) and the source region (4), i.e., a channel region, through a gate insulating film (5); a source electrode (8) in electrical contact with the source region (4); and a plurality of first filled regions (10) of the second conductivity type formed adjacent to a lower surface of the base region (3). The plurality of first filled regions (10) are formed greater than or equal to three separately from each other at least directly below both end portions of the base region (3).

Description

TECHNICAL FIELD

[0001] The present application relates to a SiC-MOSFET. BACKGROUND

[0002] In power electronics, an insulated gate type semiconductor device such as an IGBT (Insulated Gate Bipolar Transistor) or a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) is widely used as a switching element that controls the supply of electric power to a load such as a motor.

[0003] In particular, a MOSFET or an IGBT using a wide band gap semiconductor such as silicon carbide (SiC) is expected to be applied to a technical field that handles a voltage of about 1 kV or more as a switching element of the next generation. As the wide band gap semiconductor, in addition to SiC, there are, for example, gallium nitride (GaN)-based materials, diamond, and the like.

[0004] In a MOSFET of a vertical structure, a reverse pn diode called a body diode is formed by a pn junction of an n-type drift layer and a p-type base region. By using the body diode, it is possible to omit an external diode connected in parallel to the MOSFET, reducing the number of elements of a circuit. However, it is known that if a current (hereinafter referred to as a "body diode current") flows in a body diode of a MOSFET using SiC as a semiconductor material (hereinafter referred to as a "SiC-MOSFET"), a stacking fault in the crystal is elongated due to energy generated at the time of recombination of an electron-hole pair. The stacking fault functions as a high-resistance layer, and thus, if the stacking fault is elongated, the characteristics of the MOSFET and the body diode are deteriorated. Therefore, in order to use the body diode of the SiC-MOSFET, it is necessary to suppress the elongation of the stacking fault.

[0005] The stacking fault elongated due to the body diode current is almost derived from a defect existing in a substrate. More than or equal to 99% of defects existing in the substrate are transformed into harmless defects at an interface between the substrate and the drift layer, and do not elongate into the drift layer. However, if the body diode current increases, holes reach the interface between the drift layer and the substrate, and a large number of stacking faults are elongated starting from the defects existing in the substrate. The stacking fault functions as a high-resistance layer, and thus, if the stacking fault is elongated, the characteristics of the MOSFET and the body diode are greatly deteriorated. Furthermore, the holes injected into the drift layer behave as minority carriers in the drift layer, and thus, the depth to which they reach depends on the lifetime of the minority carriers.

[0006] On the other hand, a technique is known in which an SBD (Schottky Barrier Diode) is provided in a MOSFET so that a diode current flows through the SBD. Thus, the start voltage of the SBD provided in parallel with the body diode is lower than the start voltage of the pn junction of SiC constituting the body diode, and therefore, the diode current at the time of turn-off of the MOSFET does not flow through the body diode but flows through the SBD. The current flowing through the SBD is an electron current in which no holes participate, and therefore, elongation of a stacking fault caused by the current does not occur, and deterioration of the characteristics of the MOSFET or the like does not occur. However, if the diode current increases to some extent, the body diode operates and a hole current flows. In addition, the area of the MOSFET decreases due to the provision of the SBD in the unit cell. For these reasons, there is a problem in that the on-voltage increases.

[0007] Patent Document 1 proposes a structure in which a plurality of additional p-type regions are provided adjacently below a p-type base region in a unit cell of a MOSFET. According to the structure of Patent Document 1, the lifetime of injected holes is shortened in a region of the drift layer sandwiched by the p-type regions, and therefore, the number of holes reaching the interface between the drift layer and the substrate can be reduced.

[0008] Patent Document 1: Japanese Patent Application Publication No. 2005-285984

[0009] In the structure of Patent Document 1, no additional p-type region exists below the end portion of the p-type base region (paragraph 0045), and therefore, there is a problem in that the withstand voltage decreases. This is because if the width of the n-type region adjacent to the end portion of the p-type base region is widened, the depletion layer can not sufficiently expand, the electric field concentrates, and the withstand voltage decreases. SUMMARY

[0010] The present application has been made in view of the above problems, and it is an object to suppress the decrease in the withstand voltage and the increase in the on-voltage, and to increase the body diode current, for a SiC-MOSFET.

[0011] The SiC-MOSFET of the present application has: a SiC substrate of a first conductivity type; a drift layer of the first conductivity type formed on the SiC substrate; a base region of a second conductivity type formed in a surface layer of the drift layer; a source region of the first conductivity type formed in a surface layer of the base region; a gate electrode opposed to a channel region of the base region sandwiched by the drift layer and the source region with a gate insulating film interposed; a source electrode in electrical contact with the source region; and a plurality of first filled regions of the second conductivity type formed adjacently on a lower surface of the base region. The plurality of first filled regions are formed to be separated from each other by three or more at least directly below both end portions of the base region.

[0012] Effects of the Invention

[0013] According to the SiC-MOSFET of the present application, the lifetime of holes is reduced in the region of the drift layer between the first filled regions, and thus the number of holes reaching the interface between the drift layer and the substrate is reduced, and the elongation of the stacking faults is suppressed. Thus, the body diode current can be increased. In addition, the first filled regions are formed directly below both end portions of the base region, and thus the decrease in the withstand voltage is suppressed. In addition, even if the first filled regions are provided, the conduction path of the MOSFET does not change, and thus the increase in the on-voltage does not occur. BRIEF DESCRIPTION OF DRAWINGS

[0014] Figure 1 is a cross-sectional view of a SiC-MOSFET of a first comparative example of Embodiment 1.

[0015] Figure 2 is a cross-sectional view of a SiC-MOSFET of a second comparative example of Embodiment 1.

[0016] Figure 3 is a cross-sectional view of a SiC-MOSFET of Embodiment 1.

[0017] Figure 4 is a cross-sectional view of a SiC-MOSFET of a modified example of Embodiment 1.

[0018] Figure 5 is a cross-sectional view of a SiC-MOSFET of a comparative example of Embodiment 2.

[0019] Figure 6 is a cross-sectional view of a SiC-MOSFET of Embodiment 2.

[0020] Figure 7 is a cross-sectional view of a SiC-MOSFET of a first modified example of Embodiment 2.

[0021] Figure 8 is a cross-sectional view of a SiC-MOSFET of a second modified example of Embodiment 2. DETAILED DESCRIPTION

[0022] Hereinafter, the structures of various SiC-MOSFETs will be described, but the n-type or p-type in the structural elements of each SiC-MOSFET can be the opposite conduction type.

[0023] <A. Embodiment 1>

[0024] <A-1. Comparative Example>

[0025] Figure 1is a sectional view of the SiC-MOSFET 151 of Example 1. The SiC-MOSFET 151 is a MOSFET of a vertical structure. The SiC-MOSFET 151 is configured to have an n-type SiC substrate 1, an n-type drift layer 2, a p-type base region 3, an n-type source region 4, a gate insulating film 5, a gate electrode 6, an interlayer insulating film 7, a source electrode 8, and a drain electrode 9. The n-type drift layer 2 is formed on the upper surface of the SiC substrate 1. The p-type base region 3 is formed on the surface layer of the drift layer 2. The n-type source region 4 is formed on the surface layer of the base region 3. The portion of the surface layer of the base region 3 that is sandwiched by the drift layer 2 and the source region 4 becomes a channel region. The gate insulating film 5 is formed on the channel region, and the gate electrode 6 is formed on the gate insulating film 5. That is, the gate electrode 6 is formed at a position opposite the channel region with the gate insulating film 5 interposed therebetween. The side surface and the upper surface of the gate electrode 6 are covered with the interlayer insulating film 7. The source electrode 8 is formed so as to cover the source region 4, the base region 3, and the interlayer insulating film 7. The source electrode 8 is in contact with the upper surface of the base region 3 other than the channel region, on which the source region 4 is not formed. The drain electrode 9 is formed on the lower surface of the SiC substrate 1.

[0026] In the case of the SiC-MOSFET 151, a reverse pn diode called a body diode is formed by a pn junction of the n-type drift layer 2 and the p-type base region 3. By using this body diode, it is possible to omit an external diode connected in parallel with the SiC-MOSFET 151, reducing the number of components of the circuit. However, if a body diode current flows in the SiC-MOSFET, the stacking faults in the crystal are elongated due to the energy generated when electron-hole pairs recombine, degrading the characteristics of the MOSFET and the body diode. Therefore, in order to use the body diode of the SiC-MOSFET, it is necessary to suppress the elongation of the stacking faults.

[0027] Figure 2is a cross-sectional view of the SiC-MOSFET 152 of Comparative Example 2 of Embodiment 1. The SiC-MOSFET 152 differs from the SiC-MOSFET 151 of Comparative Example 1 in that a plurality of first filled regions 10 of p-type are provided adjacent to the lower surface of the base region 3. The plurality of first filled regions 10 are provided for one base region 3. The region of the drift layer 2 sandwiched by two first filled regions 10 adjacent to each other is referred to as an n-type region 11. According to the SiC-MOSFET 152, the lifetime of the holes injected in the n-type region 11 is shortened, and thus the number of holes reaching the interface between the drift layer 2 and the SiC substrate 1 is reduced. However, the first filled region 10 is not provided under the end portion of the base region 3, and thus there is a problem of a reduction in the withstand voltage. This is because if the width of the n-type region adjacent to the end portion of the base region 3 is widened, the depletion layer can not sufficiently expand, the electric field can concentrate, and the withstand voltage can be reduced.

[0028] <A-2. Structure>

[0029] Figure 3 is a cross-sectional view of the SiC-MOSFET 101 of Embodiment 1. The SiC-MOSFET 101 differs from the SiC-MOSFET 102 of Comparative Example 2 in that the first filled region 10 is also provided directly below the end portion of the base region 3.

[0030] In the case of the SiC-MOSFET 151 of Comparative Example 1, the body diode current flows from the entire base region 3 including the portion located below the source region 4 to the drift layer 2. The lifetime of the holes in the drift layer 2 is constant.

[0031] In contrast, in the case of the SiC-MOSFET 101, the lifetime of the holes is reduced around the first filled region 10. Thus, even if the same body diode current as that of the SiC-MOSFET 151 of Comparative Example 1 flows in the SiC-MOSFET 101, a part of the holes flowing from the base region 3 to the n-type region 11 is recombined in the n-type region 11. As a result, the holes reaching the interface between the drift layer 2 and the SiC substrate 1 are reduced. That is, the SiC-MOSFET 101 does not generate a defect elongation, and can flow a larger body diode current, as compared with the SiC-MOSFET 151 of Comparative Example 1.

[0032] The effect of the decrease in the lifetime of the holes is generated around the first filled region 10. This is because, since the holes are recombined in the n-type region 11 sandwiched by the first filled region 10, it is difficult to reach the drift layer 2 further below. Therefore, it is preferable that the interval of the adjacent first filled regions 10, that is, the width of the n-type region 11 be narrow. However, if the area ratio of the n-type region 11 with respect to the base region 3 becomes small, the holes flowing from the first filled region 10 to the drift layer 2 become dominant compared to the holes flowing from the n-type region 11 to the drift layer 2, and therefore, the n-type region 11 needs to have a certain degree of width. Therefore, it is preferable that the width of the n-type region 11 be greater than or equal to 0.4 μm and less than or equal to 4.0 μm. On the other hand, if the width of the first filled region 10 becomes large, the holes flowing from the first filled region 10 to the drift layer 2 increase. Therefore, the width of the first filled region 10 is preferably greater than or equal to 0.5 times and less than or equal to 2 times the width of the n-type region 11.

[0033] Further, although it also depends on the width of the base region 3, it is preferable that more than or equal to two n-type regions 11 be provided with respect to one base region 3. In other words, it is preferable that more than or equal to three first filled regions 10 be provided with respect to one base region 3. At this time, the widths of the first filled regions 10 and the n-type region 11 can also be different. Therefore, as shown in FIG. 6, the width of the first filled region 10 located directly below the both end portions of the base region 3 can be wider than the width of the first filled region 10 not located directly below the both end portions of the base region 3. Figure 3

[0034] The portion of the base region 3 or the source region 4 in contact with the source electrode 8 is referred to as a source contact region. Below the source contact region, particularly at the center thereof, the inflow amount of the holes is large. Therefore, with respect to the first filled region 10 below the source contact region, it is also possible to improve the elimination effect of the holes by making the width of the first filled region 10 located at the center the narrowest, and the width of the first filled region 10 widens as it goes outward from the center. Further, it is also possible to arrange the first filled regions 10 at equal intervals with respect to one base region 3. By arranging the first filled regions 10 at equal intervals, the body diode current flows equally from the first filled regions 10, and has the effect of stabilizing the current characteristics.

[0035] The deeper the n-type region 11, the longer the distance that the holes move in the region with a low lifetime. Therefore, the ratio of the depth of the first filled region 10 to the depth of the base region 3 is at least greater than or equal to 1.2, and preferably greater than or equal to 1.5. By making the depth of the first filled region 10 located directly below the end portion of the base region 3 the same as the depth of the other first filled regions 10, the withstand voltage is improved.

[0036] As shown in FIG. 6, the width of the first filled region 10 located directly below the both end portions of the base region 3 can be wider than the width of the first filled region 10 not located directly below the both end portions of the base region 3. Figure 3 ​In the case where the n-type region 11 is also formed directly below the source region 4 as shown, if the width of the n-type region 11 is widened, there is a possibility that the depletion layer cannot sufficiently expand and the electric field concentrates, and the withstand voltage decreases. Therefore, it is preferable that the width of the n-type region 11 be narrow. In this case, the width of the n-type region 11 can also be narrower than the above "greater than or equal to 0.4 μm and less than or equal to 4.0 μm". The depth of the first filled region 10 in this case is also the same as described above, and the ratio with respect to the depth of the base region 3 is greater than or equal to 1.2, and preferably greater than or equal to 1.5.

[0037] The higher the impurity concentration of the first filled region 10, the greater the effect of decreasing the lifetime of holes. However, if the impurity concentration of the first filled region 10 is made high, when the SiC-MOSFET 101 is in the off state and a high voltage is maintained, the electric field applied to the lower part of the first filled region 10 becomes high, and therefore, care needs to be taken when making the impurity concentration high.

[0038] Because of the configuration in which the n-type region 11 is interposed between the first filled regions 10, it is necessary to provide a plurality of first filled regions 10 directly below the base region 3. The planar shape of the unit cell is exemplified by a lattice type or a strip type composed of four sides, six sides, or a circle, and the like. In the case where the planar shape of the unit cell is a lattice type, the planar shape of the first filled region 10 can be either a concentric circle shape or a strip shape. In the case where the planar shape of the unit cell is a strip type, the arrangement of the first filled region 10 can be either parallel or perpendicular to the long side direction of the strip of the unit cell. In addition, the arrangement of the first filled region 10 can also be a pattern in which a concentric circle shape is periodically repeated along the long side direction of the strip of the unit cell.

[0039] < A-3. Modification >

[0040] Figure 4 A cross-sectional view of a SiC-MOSFET 102 which is a modification of Embodiment 1. In the case of the SiC-MOSFET 102, a recess 12 is formed on the upper surface of the source region 4 and the source contact portion of the base region 3, and the source electrode 8 enters the recess 12. Also, the first filled region 10 is formed below the end portion of the base region 3 and below the recess 12. According to the structure of the SiC-MOSFET 102 having the recess 12, the first filled region 10 can be formed using the mask at the time of forming the base region 3, and therefore, has the effect of reducing the mask.

[0041] Depending on the relationship between the depth of the recess 12 and the depth of the first filled region 10, there is a possibility that the first filled region 10 is separated from the base region 3, and even in such a case, it is preferable that the first filled region 10 be grounded. If, for example, the depth of the recess 12 is greater than the depth of the first filled region 10, the first filled region 10 is separated from the base region 3, and therefore, the first filled region 10 is not in contact with the base region 3. Figure 4By burying the source electrode 8 in the recess 12 as shown, the first filled region 10 can be grounded. Alternatively, a part or all of the side wall of the recess 12 can be made p-type to connect the base region 3 and the first filled region 10.

[0042] <A-4. Effects>

[0043] The SiC-MOSFET 101 of Embodiment 1 has a SiC substrate 1 of a first conductivity type; a drift layer 2 of the first conductivity type formed on the SiC substrate 1; a base region 3 of a second conductivity type formed on a surface layer of the drift layer 2; a source region 4 of the first conductivity type formed on a surface layer of the base region 3; a gate electrode 6 opposed to a region of the base region 3 sandwiched by the drift layer 2 and the source region 4, i.e., a channel region, through a gate insulating film 5; a source electrode 8 in electrical contact with the source region 4; and a plurality of first filled regions 10 of the second conductivity type formed adjacent to a lower surface of the base region 3. Further, the plurality of first filled regions 10 are formed to be separated from each other by at least three or more under both end portions of the base region 3. The region of the drift layer 2 between the first filled regions 10 has a reduced lifetime of holes, and thus, the number of holes reaching an interface between the drift layer 2 and the SiC substrate 1 can be reduced, and the elongation of a stacking fault can be suppressed. Thus, the body diode current can be increased. In addition, the first filled regions 10 are formed under both end portions of the base region 3, and thus, the decrease in the withstand voltage is suppressed. In addition, even if the first filled regions 10 are provided, the conduction path of the MOSFET does not change, and thus, the rise in the on-voltage does not occur.

[0044] <B. Embodiment 2>

[0045] <B-1. Comparative Example>

[0046] Figure 5 A cross-sectional view of a SiC-MOSFET 251, which is a comparative example of Embodiment 2, is shown. The SiC-MOSFET 251 is configured to have an active region 14 having unit cells that function as MOSFETs, and a peripheral region 13 that is more outward than the active region 14. The structure of the active region 14 of the SiC-MOSFET 251 is the same as that of the SiC-MOSFET 151 of the first comparative example of Embodiment 1. In addition, the SiC substrate 1, the drift layer 2, the source electrode 8, and the drain electrode 9 are common to the active region 14 and the peripheral region 13.

[0047] In the outer peripheral region 13, a plurality of guard rings 15 are provided in the surface layer of the drift layer 2. The guard rings 15 are regions of p-type, and are configured in a concentric circular shape so as to surround the active region 14. The width of each guard ring 15 gradually decreases from the inner side to the outer side of the outer peripheral region 13. In addition, depending on the structure of the SiC-MOSFET, a gate electrode 6 and a gate pad or a field oxide film, or the like, are sometimes provided in the outer peripheral region 13.

[0048] In the case of the SiC-MOSFET 251, a current called displacement current is generated in association with the expansion and contraction of the depletion layer generated in the drift layer 2 and at the guard rings 15 at the time of on-off operation. If the potential inside the guard ring 15 becomes high due to this current, the potential difference between the source electrode 8 or the gate electrode 6 becomes large, and the field insulation film, the interlayer insulation film 7, or the gate insulation film 5 provided therebetween is destroyed. Therefore, the innermost guard ring 15, that is, the guard ring 15a, is provided with a portion in electrical contact with the source electrode 8, that is, a source contact portion 16. The guard ring 15a having this source contact portion 16 also functions as a body diode, and therefore, elongation of the stacking fault due to the body diode current becomes a problem.

[0049] <B-2. Structure>

[0050] Figure 6 is a cross-sectional view of the SiC-MOSFET 201 of Embodiment 2. The active region 14 of the SiC-MOSFET 201 has the same structure as that of the SiC-MOSFET 101 of Embodiment 1. The outer peripheral region 13 of the SiC-MOSFET 201 differs from the outer peripheral region 13 of the SiC-MOSFET 251 of the comparative example in that a plurality of p-type second fill-in regions 20 are provided adjacently below the innermost guard ring 15a. The region of the drift layer 2 sandwiched by the adjacent second fill-in regions 20 is referred to as an n-type region 21.

[0051] In Figure 6 , the second fill-in regions 20 are formed not only directly below the source contact portion 16 but also below both end portions of the guard ring 15a. However, the second fill-in regions 20 can be provided only directly below the source contact portion 16. As explained in Embodiment 1 with respect to the first fill-in region 10 and the n-type region 11, the lifetime of the holes of the n-type region 21 can be decreased by providing the second fill-in regions 20.

[0052] The width, depth, and impurity concentration of the second fill-in regions 20 are the same as those of the first fill-in region 10. In addition, it is preferable that two or more n-type regions 21 be provided with respect to the guard ring 15a. In other words, it is preferable that three or more second fill-in regions 20 be provided with respect to the guard ring 15a.

[0053] Further, the second filled region 20 of the outer peripheral region 13 can also be the same depth as the first filled region 10 of the active region 14. The depths of both are the same, whereby the withstand voltage is improved. In addition, the second filled region 20 of the outer peripheral region 13 can also gradually deepen from the outside toward the active region 14 side.

[0054] <B-3. Modification>

[0055] Figure 7 is a cross-sectional view of a SiC-MOSFET 202 that is a first modification of Embodiment 2. The SiC-MOSFET 202 differs from the SiC-MOSFET 201 of Embodiment 2 in that, in the active region 14, a recess 12 is formed on the upper surface of the source region 4 and the source contact portion of the base region 3, and in the outer peripheral region 13, a recess 22 is formed on the upper surface of the innermost protective ring 15a. The active region 14 of the SiC-MOSFET 202 is the same structure as the SiC-MOSFET 102 of the modification of Embodiment 1. The gate insulating film 5, the interlayer insulating film 7, or the source electrode 8 enters the recess 22.

[0056] Figure 8 is a cross-sectional view of a SiC-MOSFET 203 that is a second modification of Embodiment 2. The SiC-MOSFET 203 makes the width of the recess 22 larger than the width of the recess 22 of the SiC-MOSFET 202, and aligns the height of the upper surface of the outer end portion of the protective ring 15a and the upper surface of the protective ring 15 that is more outside than the protective ring 15a with the bottom surface of the recess 22.

[0057] Further, in the above-described SiC-MOSFETs 101, 102, 201, 202, 203, a planar type unit cell was used, but a trench type unit cell can also be used.

[0058] <B-4. Effects>

[0059] The SiC-MOSFET 201 of Embodiment 2 has an active region 14 in which a plurality of unit cells each composed of a gate electrode 6, a base region 3, and a source region 4 are arranged, and an outer peripheral region 13 that surrounds the active region 14. The outer peripheral region 13 has a plurality of protective rings 15 of the second conductivity type formed on the surface layer of the drift layer 2, and a plurality of second filled regions 20 of the second conductivity type formed adjacent to the lower surface of the innermost protective ring 15a among the plurality of protective rings 15. The plurality of second filled regions 20 are formed separately from each other in at least three or more on the lower surface of both end portions of the innermost protective ring 15a. Thus, according to the SiC-MOSFET 201, the following effects can be achieved in the outer peripheral region 13, that is, the threading dislocation elongation does not occur, and the flowable body diode current increases.

[0060] Furthermore, each embodiment can be freely combined, or appropriately modified, omitted, etc.

[0061] Explanation of Reference Numerals

[0062] 1 SiC substrate, 2 drift layer, 3 base region, 4 source region, 5 gate insulating film, 6 gate electrode, 7 interlayer insulating film, 8 source electrode, 9 drain electrode, 10 first buried region, 11, 21 n-type region, 12, 22 recess, 13 peripheral region, 14 active region, 15, 15a guard ring, 16 source contact, 20 second buried region.

Claims

1. A silicon carbide-metal oxide semiconductor field effect transistor (SiC-MOSFET) having: a SiC substrate of a first conductivity type; a drift layer of the first conductivity type formed on the SiC substrate; a base region of a second conductivity type formed on a surface layer of the drift layer; a source region of the first conductivity type formed on a surface layer of the base region; a gate electrode opposed to a region of the base region sandwiched by the drift layer and the source region, i.e., a channel region, through a gate insulating film; a source electrode in electrical contact with the source region; and a plurality of first filled regions of the second conductivity type adjacently formed on a lower surface of the base region, the plurality of first filled regions being formed at least directly below both end portions of the base region, being separated from each other in a width direction of the base region by three or more, a width of the drift layer sandwiched by two adjacent first filled regions being 0.4 μm or more and 4.0 μm or less.

2. The SiC-MOSFET according to claim 1, wherein the plurality of first filled regions are arranged at equal intervals in the width direction of the base region.

3. A silicon carbide-metal oxide semiconductor field effect transistor (SiC-MOSFET) having: a SiC substrate of a first conductivity type; a drift layer of the first conductivity type formed on the SiC substrate; a base region of a second conductivity type formed on a surface layer of the drift layer; a source region of the first conductivity type formed on a surface layer of the base region; a gate electrode opposed to a region of the base region sandwiched by the drift layer and the source region, i.e., a channel region, through a gate insulating film; a source electrode in electrical contact with the source region; and a plurality of first filled regions of the second conductivity type adjacently formed on a lower surface of the base region, the plurality of first filled regions being formed at least directly below both end portions of the base region, being separated from each other in a width direction of the base region by three or more, a ratio of a depth of the first filled region to a depth of the base region being 1.2 or more.

4. The SiC-MOSFET according to claim 3, wherein the plurality of first filled regions are arranged at equal intervals in the width direction of the base region.

5. A silicon carbide-metal oxide semiconductor field effect transistor (SiC-MOSFET) having: a SiC substrate of a first conductivity type; a drift layer of the first conductivity type formed on the SiC substrate; a base region of a second conductivity type formed on a surface layer of the drift layer; a source region of the first conductivity type formed on a surface layer of the base region; a gate electrode opposed to a region of the base region sandwiched by the drift layer and the source region, i.e., a channel region, through a gate insulating film; a source electrode in electrical contact with the source region; and a plurality of first filled regions of the second conductivity type adjacently formed on a lower surface of the base region, the plurality of first filled regions being formed at least directly below both end portions of the base region, being separated from each other in a width direction of the base region by three or more, a ratio of a depth of the first filled region to a depth of the base region being 1.2 or more. ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ A plurality of first landfill regions of the second conductivity type are formed adjacent to each other on the lower surface of the base region. Multiple first landfill areas are formed at least directly below both ends of the base region, and three or more of these areas are separated from each other in the width direction of the base region. The width of the first landfill area located directly below both ends of the base region is wider than the width of the first landfill area not located directly below both ends of the base region.

6. The silicon carbide-metal oxide semiconductor field-effect transistor (SiC-MOSFET) according to any one of claims 1 to 5, wherein, The depth of the first landfill area located directly below both ends of the base region is the same as the depth of the first landfill area not located directly below both ends of the base region.

7. A silicon carbide-metal oxide semiconductor field-effect transistor (SiC-MOSFET), comprising: SiC substrate of the first conductivity type; A drift layer of the first conductivity type is formed on the SiC substrate; The base region of the second conductivity type is formed on the surface of the drift layer; The source region of the first conductivity type is formed on the surface of the base region; The gate electrode is separated from the base region, i.e. the channel region, by the gate insulating film; Source electrode, which is in electrical contact with the source region; as well as A plurality of first landfill regions of the second conductivity type are formed adjacent to each other on the lower surface of the base region. Multiple first landfill areas are formed at least directly below both ends of the base region, and three or more of these areas are separated from each other in the width direction of the base region. The silicon carbide-metal oxide semiconductor field-effect transistor has the following characteristics: An active region having a plurality of unit cells comprising the gate electrode, the base region, and the source region; and The outer peripheral region surrounds the active region. The peripheral region has: Multiple protective rings of the second conductivity type are formed on the surface of the drift layer; as well as The second conductive type comprises multiple second landfill regions, which are formed adjacent to each other on the lower surface of the innermost protective ring among the multiple protective rings. The plurality of said second landfill areas are adjacent to the lower surfaces of both ends of the innermost protective ring, forming more than or equal to three separate from each other.

8. The silicon carbide-metal oxide semiconductor field-effect transistor (SiC-MOSFET) according to claim 7, wherein, The first landfill area has the same depth as the second landfill area.

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