Voltage conversion circuit

Abstract

This disclosure provides a voltage conversion circuit, comprising: a first input module connected to a first voltage and having a first input terminal, the first input terminal being used to receive an input signal and output a converted signal, wherein a high level of the input signal is a second voltage, the second voltage being less than the first voltage; and a second input module connected to the first input module, having a second input terminal and an output terminal, the second input terminal being used to receive a sampling signal, sample the converted signal according to the sampling signal, and output an output signal through the output terminal. Embodiments of this disclosure can convert a low-voltage input signal into a high-voltage output signal through a simple structure, reducing the footprint and power consumption of the voltage conversion circuit.

Description

Technical Field

[0001] This disclosure relates to the field of integrated circuit technology, and more specifically, to a voltage conversion circuit capable of converting a low-voltage input signal into a high-voltage output signal. Background Technology

[0002] To reduce the power consumption of memory chips, in low-speed mode, the operating voltage of some circuits can be reduced to decrease the power consumption of those circuits. In this case, the operating voltage of other circuits will be higher than that of this lower-voltage circuit. When a signal is transmitted from other circuits to this lower-voltage circuit, it can be used directly. However, when a signal is transmitted from this lower-voltage circuit to other circuits, it usually needs to be boosted; otherwise, leakage current will occur.

[0003] In related technologies, voltage level shifters are typically used to boost signals. When there are many interface signals between the voltage-reducing circuit and other circuits, a separate voltage level shifter is required for each signal, resulting in large component space and high total power consumption for multiple voltage level shifters. Therefore, a voltage conversion scheme with low power consumption and small component footprint is needed.

[0004] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0005] The purpose of this disclosure is to provide a voltage conversion circuit that at least partially overcomes the problems of large area and high power consumption in existing voltage conversion schemes due to limitations and defects in related technologies.

[0006] According to a first aspect of this disclosure, a voltage conversion circuit is provided, comprising: a first input module connected to a first voltage and having a first input terminal, the first input terminal being used to receive an input signal and output a conversion signal, wherein a high level of the input signal is a second voltage, the second voltage being less than the first voltage; and a second input module connected to the first input module, having a second input terminal and an output terminal, the second input terminal being used to receive a sampling signal, sample the conversion signal according to the sampling signal, and output an output signal through the output terminal.

[0007] In one exemplary embodiment of this disclosure, the first input module includes: a first P-type transistor with its gate connected to a first input terminal and its source connected to the first voltage; and a first N-type transistor with its gate connected to the first input terminal and its source grounded.

[0008] In one exemplary embodiment of this disclosure, the second input module includes: a second P-type transistor, the gate of which is electrically connected to the second input terminal, the source of which is connected to the drain of the first P-type transistor, and the drain of which is connected to the output terminal; and a second N-type transistor, the gate of which is electrically connected to the second input terminal, the source of which is connected to the drain of the first N-type transistor, and the drain of which is connected to the output terminal.

[0009] In one exemplary embodiment of this disclosure, the second input module further includes a first inverter.

[0010] In one exemplary embodiment of this disclosure, the enable level of the sampling signal is high, the gate of the second P-type transistor is connected to the second input terminal through the first inverter, and the gate of the second N-type transistor is connected to the second input terminal.

[0011] In one exemplary embodiment of this disclosure, the enable level of the sampling signal is low, the gate of the second P-type transistor is connected to the second input terminal, and the gate of the second N-type transistor is connected to the second input terminal through the first inverter.

[0012] In one exemplary embodiment of this disclosure, the voltage conversion circuit further includes a latch module, wherein the input terminal of the latch module is connected to the output terminal and is used to latch the output signal.

[0013] In one exemplary embodiment of this disclosure, the latch module includes: a second inverter, the input terminal of which is connected to the output terminal of the voltage conversion circuit, and the output terminal of which is connected to the output terminal of the latch module; and a feedback inverter, the input terminal of which is connected to the output terminal of the latch module, and the output terminal of which is connected to the output terminal of the voltage conversion circuit.

[0014] In one exemplary embodiment of this disclosure, the feedback inverter is in a closed state when the sampling signal is in an enabled state.

[0015] In one exemplary embodiment of this disclosure, the enable level of the sampling signal occurs within a preset time period during which the input signal undergoes a level change.

[0016] In one exemplary embodiment of this disclosure, the duration of the enable level of the sampling signal is less than half the duration of the high level in the input signal.

[0017] In one exemplary embodiment of this disclosure, the sampling signal is a pulse signal with a set period.

[0018] In one exemplary embodiment of this disclosure, the duty cycle of the enable level in the sampled signal is less than 1 / 2.

[0019] In one exemplary embodiment of this disclosure, the value of the second voltage causes the pull-up capability of the first P-type transistor to be greater than the pull-down capability of the first N-type transistor.

[0020] In one exemplary embodiment of this disclosure, the difference between the first voltage and the second voltage is less than or equal to the threshold voltage of the first P-type transistor.

[0021] The embodiments disclosed herein use a first input module to convert a lower voltage input signal into a higher voltage signal, and a second input module to sample and output the higher voltage signal. This allows for the conversion of a lower voltage input signal into a higher voltage output signal using very few components, reducing the area occupied and power consumption of components during the voltage conversion process.

[0022] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0023] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0024] Figure 1 This is a schematic diagram of the voltage conversion circuit in an exemplary embodiment of this disclosure.

[0025] Figure 2 This is a circuit diagram of a voltage conversion circuit in one embodiment of the present disclosure.

[0026] Figure 3 yes Figure 2 Timing control diagram in the illustrated embodiment.

[0027] Figures 4A to 4D yes Figure 3 Under the timing control shown Figure 2 The equivalent circuit diagram of the level conversion circuit shown is shown.

[0028] Figure 5 A circuit diagram of a voltage conversion circuit in another embodiment of this disclosure.

[0029] Figure 6 yes Figure 5 Timing control diagram in the illustrated embodiment.

[0030] Figures 7A to 7D yes Figure 5 The voltage conversion circuit of the embodiment shown is in Figure 6 The equivalent circuit diagram under the given timing is shown. Detailed Implementation

[0031] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided to make this disclosure more comprehensive and complete, and to fully convey the concept of the example embodiments to those skilled in the art. The described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a full understanding of embodiments of this disclosure. However, those skilled in the art will recognize that the technical solutions of this disclosure can be practiced with one or more of the specific details omitted, or other methods, components, apparatus, steps, etc., can be employed. In other instances, well-known technical solutions are not shown or described in detail to avoid obscuring various aspects of this disclosure.

[0032] Furthermore, the accompanying drawings are merely illustrative of this disclosure, and the same reference numerals in the drawings denote the same or similar parts, thus repeated descriptions of them will be omitted. Some block diagrams shown in the drawings are functional entities and do not necessarily correspond to physically or logically independent entities. These functional entities may be implemented in software, in one or more hardware modules or integrated circuits, or in different network and / or processor devices and / or microcontroller devices.

[0033] The exemplary embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0034] Figure 1 This is a schematic diagram of the voltage conversion circuit in an exemplary embodiment of this disclosure.

[0035] refer to Figure 1 The voltage conversion circuit 100 may include:

[0036] The first input module 11 is connected to the first voltage VCC_High and has a first input terminal 111. The first input terminal 111 is used to receive the input signal Si and output the conversion signal Sc. The high level of the input signal Si is the second voltage VCC_Low. The second voltage VCC_Low is less than the first voltage VCC_High.

[0037] The second input module 12 is connected to the first input module 11 and has a second input terminal 121 and an output terminal 122. The second input terminal 121 is used to receive the sampling signal Ss and sample the conversion signal Sc according to the sampling signal Ss to output the output signal So through the output terminal 122.

[0038] In this embodiment of the disclosure, the first input module 11 operates under the first voltage VCC_High. Therefore, the conversion signal Sc generated based on the input signal Si is a signal under the first voltage VCC_High. By sampling the conversion signal Sc through the second input module 12, an output signal under the first voltage VCC_High can be output, thereby realizing the voltage boosting of the input signal Si.

[0039] In one embodiment of this disclosure, the enable level of the sampling signal Ss can occur within a preset time period when the input signal Si changes level, that is, the sampling signal Ss can be triggered by the polarity change of the input signal Si, so that the timing of the output signal So is consistent with that of the input signal Si.

[0040] In another embodiment of this disclosure, the sampling signal Ss can also be a pulse signal with a set period, thereby converting the non-periodic input signal Si into a periodic output signal So, making the timing of the signal easier to control. Input signals with different timings can be processed by the sampling signal to form a signal group with the same timing, which is more beneficial for the use of subsequent circuits.

[0041] In another embodiment of this disclosure, the sampling signal Ss can also sample the input signal Si according to the control signal.

[0042] Due to its simple structure, the voltage conversion circuit 100 provided in this embodiment can be implemented with fewer components, which greatly reduces the component area and power consumption of the voltage conversion function.

[0043] Figure 2 This is a circuit diagram of a voltage conversion circuit in one embodiment of the present disclosure.

[0044] refer to Figure 2 In the voltage conversion circuit 200, the first input module 11 may include:

[0045] The first P-type transistor M1 has its gate connected to the first input terminal 111 and its source connected to the first voltage VCC_High.

[0046] The first N-type transistor M4 has its gate connected to the first input terminal 111 and its source grounded.

[0047] The second input module 12 may include:

[0048] The second P-type transistor M2 has its gate electrically connected to the second input terminal 121, its source connected to the drain of the first P-type transistor M1, and its drain connected to the output terminal 122.

[0049] The second N-type transistor M3 has its gate electrically connected to the second input terminal 121, its source connected to the drain of the first N-type transistor M4, and its drain connected to the output terminal 122.

[0050] exist Figure 2 In the embodiment shown, the second input module 12 further includes a first inverter OP1.

[0051] In one embodiment, the enable level of the sampling signal Ss is high, and the gate of the second P-type transistor M2 is connected to the second input terminal 121 (e.g., via the first inverter) through the first inverter. Figure 2 As shown), the gate of the second N-type transistor M3 is connected to the second input terminal 121.

[0052] In another embodiment, the enable level of the sampling signal Ss is low, the gate of the second P-type transistor M2 is connected to the second input terminal 121 (not shown), and the gate of the second N-type transistor M3 is connected to the second input terminal 121 through the first inverter.

[0053] The following explains the control timing. Figure 2 The working principle of the voltage conversion circuit in the illustrated embodiment.

[0054] Figure 3 yes Figure 2 Timing control diagram in the illustrated embodiment.

[0055] exist Figure 3 In the illustrated embodiment, the input signal Si is a periodic signal, and the sampling signal Ss is also a periodic signal. The sampling signal Ss appears within a preset time period during which the input signal Si undergoes a level change, and the output signal So changes level with the appearance of the sampling signal Ss. It can be seen that the level change range of the input signal Si is the second voltage VCC_Low, and the sampling signal Ss and the inverted signal of the sampling signal Ss after passing through the first inverter OP1... The output signal So's level varies within the range of the first voltage VCC_High.

[0056] Figures 4A to 4D yes Figure 3 Under the timing control shown Figure 2 The equivalent circuit diagram of the level conversion circuit shown is shown.

[0057] refer to Figure 4A When the input signal Si is low and the sampling signal Ss is high, the first P-type transistor M1, the second P-type transistor M2, and the first N-type transistor M3 are turned on, and the second N-type transistor M4 is turned off. At this time, the first voltage VCC_High is output to the output terminal 122 through the first P-type transistor M1 and the second P-type transistor M2, generating a current I1, making the output signal So VCC_High, i.e., high level.

[0058] refer to Figure 4BWhen the input signal Si is high and the sampling signal Ss is high, the second P-type transistor M2, the first N-type transistor M3, and the second N-type transistor M4 are turned on, and the first P-type transistor M1 is turned off (or at least the pull-up capability of M1 is less than the pull-down capability of M4). At this time, the output terminal 122 is grounded through the first N-type transistor M3 and the second N-type transistor M4, generating a discharge current I2, making the output signal So 0, i.e., low level. It can be understood that since the high level of the input signal Si is VCC_Low, and VCC_Low is less than VCC_High, for example, VCC_Low is 0.9V and VCC_High is 1.1V, the first P-type transistor M1 may not be completely turned off, and there will be a certain charging current I3. The charging current I3 is from VCC_High to the output terminal 122, and the discharge current I2 is from the output terminal 122 to the ground terminal.

[0059] In order to make the charging current I3 much smaller than the discharging current I2, thereby making the output signal So of the output terminal 122 reach 0V, in this embodiment of the disclosure, the value of the second voltage VCC_Low needs to make the pull-up capability of the first P-type transistor M1 less than the pull-down capability of the first N-type transistor M4. In an exemplary embodiment of the present disclosure, the difference between the first voltage VCC_High and the second voltage VCC_Low can, for example, be less than or equal to the threshold voltage Vp1 of the first P-type transistor M1, and the value of Vp1 can, for example, be 0.5V.

[0060] from Figure 4A and Figure 4B As can be seen from the embodiment shown, the level conversion circuit 200 can convert the input signal Si with a low voltage variation range (VCC_Low~0) into an output signal So with a high voltage variation range (VCC_High~0), and the phase of the output signal So is opposite to that of the input signal Si.

[0061] If it is necessary to set the phase of the output signal So to be the same as that of the input signal Si, an inverter can be connected to the output terminal 122, which will not be elaborated here.

[0062] refer to Figure 4C and Figure 4D When the sampling signal Ss is low, the output terminal 122 does not produce any signal change regardless of the input signal Si. To ensure that the output signal So of the output terminal 122 is in phase with the input signal Si, one approach is to keep the sampling signal Ss constantly high. In this case, the second input module 12 can be removed. However, this approach will continuously generate a charging current I3 to ground when the input signal Si is high, causing an increase in circuit power consumption. Another approach is to connect a latch after the output terminal 122 so that the output signal of the entire circuit remains unchanged when the sampling signal Ss is low.

[0063] Figure 5 A circuit diagram of a voltage conversion circuit in another embodiment of this disclosure.

[0064] refer to Figure 5 In one exemplary embodiment of this disclosure, the voltage conversion circuit 500 further includes:

[0065] The latch module 13 has its input terminal connected to the output terminal 122 and is used to latch the output signal So.

[0066] exist Figure 3 In the illustrated embodiment, the latch module 13 includes a second inverter OP2 and a feedback inverter OP3. The input terminal of the second inverter OP2 is connected to the output terminal 122 of the voltage conversion circuit, and the output terminal of the second inverter is connected to the output terminal 131 of the latch module 13. The input terminal of the feedback inverter OP3 is connected to the output terminal 131 of the latch module 13, and the output terminal of the feedback inverter OP3 is connected to the output terminal 122 of the voltage conversion circuit. Both the second inverter OP2 and the feedback inverter OP3 are connected to a first voltage VCC_High, which is not shown in the figure.

[0067] Figure 6 yes Figure 5 Timing control diagram in the illustrated embodiment.

[0068] refer to Figure 6 ,and Figure 3 compared to, Figure 6 The timing diagram of the output signal Output of the output terminal 131 of the latch module 13 has been added. Due to the latch delay, the level change of the output signal Output is later than that of the output signal So.

[0069] Figures 7A to 7D yes Figure 5 The voltage conversion circuit of the embodiment shown is in Figure 6 The equivalent circuit diagram under the given timing is shown.

[0070] refer to Figure 7A When the input signal Si is low and the sampling signal Ss is high, the first P-type transistor M1, the second P-type transistor M2, and the first N-type transistor M3 are turned on, and the second N-type transistor M4 is turned off (or at least the pull-up capability of M1 is less than the pull-down capability of M4). At this time, the first voltage VCC_High is output to the output terminal 122 through the first P-type transistor M1 and the second P-type transistor M2, generating a current I1, making the output signal So VCC_High, i.e., high level.

[0071] The output signal So enters the second inverter OP2 and outputs a low-level output signal Output through output terminal 131. The phase of the output signal Output is synchronized with the phase of the sampled signal Ss. The output signal Output returns to output terminal 122 via feedback inverter OP3, and remains at a high level. Since feedback inverter OP3 is not required to maintain the voltage at output terminal 122 at this time, to reduce power consumption, feedback inverter OP3 can be controlled to be in the off state in this state.

[0072] refer to Figure 7B When the input signal Si is high and the sampling signal Ss is high, the second P-type transistor M2, the first N-type transistor M3, and the second N-type transistor M4 are turned on, while the first P-type transistor M1 is turned off. At this time, the output terminal 122 is grounded through the first N-type transistor M3 and the second N-type transistor M4, generating a discharge current I2, which makes the output signal So 0, i.e., low level. It can be understood that since the high level of the input signal Si is VCC_Low, the first P-type transistor M1 will not be completely turned off, and there will be a certain charging current I3.

[0073] The output signal So is transmitted through the second inverter OP2 and outputs a high-level output signal Output through output terminal 131. The phase of the output signal Output is synchronized with the phase of the sampled signal Ss. The output signal Output is then transmitted back to output terminal 122 via feedback inverter OP3, remaining at a low level. Since feedback inverter OP3 is not required to maintain the voltage at output terminal 122 at this time, it can be turned off in this state to reduce power consumption.

[0074] That is, when the sampling signal Ss is enabled, the feedback inverter OP3 can be set to the off state.

[0075] refer to Figure 7C When the sampling signal Ss is low, the output terminal 122 will not change regardless of the input signal Si. Before this state is formed, that is, before the control sampling signal Ss is low, the feedback inverter OP3 can be enabled to form a feedback path between the output terminal 122 and the output terminal 131. Since the second inverter OP2 and the feedback inverter OP3 are both active devices, the latch module 13 can maintain the voltage of the output terminal 122 when it is working, thereby maintaining the voltage of the output terminal 131 unchanged. Figure 7D The embodiments shown are similar, and will not be described again here.

[0076] Since a charging current I3 will be generated when the sampling signal Ss is in the enabled state and the input signal Si is at a high level, increasing power consumption, the enable state maintenance time of the sampling signal Ss can be reduced as much as possible when the latch module 13 is used to keep the output signal unchanged, so as to reduce the power consumption of the circuit.

[0077] In one embodiment of this disclosure, when the enable level of the sampling signal Ss occurs within a preset time period during which the input signal Si changes level, the duration of the enable level of the sampling signal Ss can, for example, be less than half of the high-level time in the input signal Si.

[0078] In another embodiment of this disclosure, when the sampling signal Ss is a pulse signal with a set period, the duty cycle of the enable level in the sampling signal Ss can be, for example, less than 1 / 2. To further reduce power consumption, the duty cycle of the sampling signal Ss can be even lower, for example, less than 1 / 4, less than 1 / 10, or less than 1 / 20.

[0079] The above values ​​are for illustrative purposes only. In practical applications, those skilled in the art can set the enable level duration of the sampling signal Ss according to the actual situation.

[0080] In addition, the charging current I3 can also be reduced by decreasing the size of the components in the second input module 12.

[0081] The high level of the sampling signal Ss is VCC_High, and the low level is 0. The sampling signal Ss can be generated by the control circuit powered by VCC_High.

[0082] The embodiments of this disclosure convert a lower voltage input signal Si into a higher voltage output signal So by using a lower voltage input signal Si to drive a transistor operating at a higher voltage. By using a sampling signal in conjunction with a latch to sample and maintain the output signal So, the enable level maintenance time of the sampling signal is greatly reduced, leakage current is reduced, and the power consumption of the entire circuit is lowered. Compared with the prior art, the voltage conversion circuit provided by the embodiments of this disclosure has fewer components, smaller component area, and lower power consumption, and can be widely used in circuits with multiple signal voltage conversion requirements.

[0083] It should be noted that although several modules or units for the device used to perform actions have been mentioned in the detailed description above, this division is not mandatory. In fact, according to embodiments of this disclosure, the features and functions of two or more modules or units described above can be embodied in one module or unit. Conversely, the features and functions of one module or unit described above can be further divided and embodied by multiple modules or units.

[0084] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and concept of this disclosure are indicated by the claims.

Claims

1. A voltage conversion circuit, characterized in that, include: A first input module is connected to a first voltage and has a first input terminal. The first input terminal is used to receive an input signal and output a conversion signal. The high level of the input signal is a second voltage, and the second voltage is less than the first voltage. The second input module is connected to the first input module and has a second input terminal and an output terminal. The second input terminal is used to receive the sampling signal and sample the conversion signal according to the sampling signal, and output the output signal through the output terminal of the second input module. The first input module includes: The first P-type transistor has its gate connected to the first input terminal and its source connected to the first voltage. The first N-type transistor has its gate connected to the first input terminal and its source grounded. The value of the second voltage makes the pull-up capability of the first P-type transistor less than the pull-down capability of the first N-type transistor; A latching module, wherein the input terminal of the latching module is connected to the output terminal, and is used to latch the output signal; The latch module includes: The second inverter has its input terminal connected to the output terminal of the voltage conversion circuit, and its output terminal connected to the output terminal of the latch module. A feedback inverter, wherein the input terminal of the feedback inverter is connected to the output terminal of the latch module, and the output terminal of the feedback inverter is connected to the output terminal of the voltage conversion circuit; When the sampling signal is enabled, the feedback inverter is disabled.

2. The voltage conversion circuit as described in claim 1, characterized in that, The second input module includes: The second P-type transistor has its gate electrically connected to the second input terminal, its source connected to the drain of the first P-type transistor, and its drain connected to the output terminal of the second input module. The second N-type transistor has its gate electrically connected to the second input terminal, its source connected to the drain of the first N-type transistor, and its drain connected to the output terminal of the second input module.

3. The voltage conversion circuit as described in claim 2, characterized in that, The second input module also includes a first inverter.

4. The voltage conversion circuit as described in claim 3, characterized in that, The enable level of the sampling signal is high, the gate of the second P-type transistor is connected to the second input terminal through the first inverter, and the gate of the second N-type transistor is connected to the second input terminal.

5. The voltage conversion circuit as described in claim 3, characterized in that, The enable level of the sampling signal is low, the gate of the second P-type transistor is connected to the second input terminal, and the gate of the second N-type transistor is connected to the second input terminal through the first inverter.

6. The voltage conversion circuit according to any one of claims 1 to 5, characterized in that, The enable level of the sampling signal occurs within a preset time period when the input signal level changes.

7. The voltage conversion circuit as described in claim 6, characterized in that, The duration of the enable level of the sampling signal is less than half the duration of the high level in the input signal.

8. The voltage conversion circuit according to any one of claims 1 to 5, characterized in that, The sampling signal is a pulse signal with a set period.

9. The voltage conversion circuit as described in claim 8, characterized in that, The duty cycle of the enable level in the sampled signal is less than 1 / 2.

10. The voltage conversion circuit as described in claim 1, characterized in that, The difference between the first voltage and the second voltage is less than or equal to the threshold voltage of the first P-type transistor.

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