A multi-core processing system and its task scheduling method, chip, and storage medium

Abstract

The embodiment of the present application discloses a multi-core processing system and its task scheduling method, chip, and storage medium. The multi-core processing system includes multiple control cores and multiple processing cores. The multiple control cores are respectively connected to the multiple processing cores. The first control core reads a first instruction and executes the first instruction when it is determined that the first instruction is a control instruction executed by the control core; when the first control core determines that the first instruction is a data processing instruction executed by the processing core, it sends the first instruction to the first processing core for execution. In this way, a one-to-many topological structure is configured between the control core and the processing core according to the processing requirements, so as to improve the parallelism of data processing instruction processing, thereby improving data processing efficiency and reducing chip area.

Description

Technical Field

[0001] The present application relates to computer technology, and in particular to a multi-core processing system and its task scheduling method, chip, and storage medium. Background Art

[0002] At present, multi-core processors are widely used in chips. Multi-core processors can simultaneously process high-bandwidth data, execute system applications, respond to real-time requests, and meet industry security standards. Multi-core processors have become an important direction for the development of processor architecture due to their many advantages such as high chip area utilization, low processor power consumption, and high degree of parallelization.

[0003] The disadvantage of the multi-core processor structure is that its special structure inevitably brings about a series of problems such as the connection method between cores, communication synchronization method, differences in core structure, memory resource allocation strategy, multi-clock domain allocation strategy, hardware and software collaborative design optimization, etc. Its development difficulty becomes more and more difficult as the chip scale increases. Any link that is not handled well may affect the performance and power consumption of the entire processor. For scenarios where a small amount of control is combined with a large amount of data calculation, a series of core expansion technologies have also emerged. Although these technologies solve the problem that multi-core processor systems are not applicable in this scenario, the one-to-one topological relationship between the control core and the expansion processing unit naturally limits its application flexibility and performance bottlenecks. Summary of the invention

[0004] The embodiments of the present application are intended to provide a multi-core processing system and its task scheduling method, chip, and storage medium.

[0005] The technical solution of this application is implemented as follows:

[0006] In a first aspect, a multi-core processing system is provided, wherein the multi-core processing system comprises a plurality of control cores and a plurality of processing cores.

[0007] A first control core among the plurality of control cores reads a first instruction;

[0008] When the first control core determines that the first instruction is a control instruction executed by the control core, executing the first instruction;

[0009] When the first control core determines that the first instruction is a data processing instruction executed by a processing core, the first control core sends the first instruction to a first processing core among the multiple processing cores, and the first processing core executes the first instruction.

[0010] In a second aspect, a chip is provided, wherein the chip includes the multi-core processing system described in the first aspect.

[0011] In a third aspect, a task scheduling method for a multi-core processing system is provided, wherein the multi-core processing system is the multi-core processing system in the first aspect, and the method comprises:

[0012] Reading a first instruction through a first control core among the plurality of control cores;

[0013] When the first control core determines that the first instruction is a control instruction executed by the control core, executing the first instruction;

[0014] When the first control core determines that the first instruction is a data processing instruction executed by a processing core, the first instruction is sent to a first processing core among the multiple processing cores, and the first processing core executes the first instruction.

[0015] In a fourth aspect, a computer-readable storage medium is provided, on which a computer program is stored, wherein the computer program implements the steps of the aforementioned method when executed by a processor.

[0016] By adopting the above technical solution, a one-to-many topology structure is configured between the control core and the processing core according to the processing requirements, so as to improve the parallelism of data processing instruction processing, thereby improving data processing efficiency and reducing chip area. In addition, the processing core can flexibly select homogeneous processing cores and heterogeneous processing cores. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 This is a schematic diagram of the first component structure of the multi-core processing system in an embodiment of the present application;

[0018] Figure 2 This is a schematic diagram of a second component structure of a multi-core processing system in an embodiment of the present application;

[0019] Figure 3 A flowchart of a task scheduling method for a multi-core processing system in an embodiment of the present application;

[0020] Figure 4 It is a schematic diagram of the composition structure of the chip of the embodiment of the present application. DETAILED DESCRIPTION

[0021] In order to enable a more detailed understanding of the features and technical contents of the embodiments of the present application, the implementation of the embodiments of the present application is described in detail below in conjunction with the accompanying drawings. The attached drawings are for reference only and are not used to limit the embodiments of the present application.

[0022] The embodiment of the present application provides a multi-core processing system, wherein the multi-core processing system includes multiple control cores and multiple processing cores, and is used to implement task scheduling. Figure 1 Schematic diagram of the first component structure of the system in the embodiment of the present application. Figure 1As shown, the multi-core processing system 10 includes: a plurality of control cores 110 and a plurality of processing cores 120, and each control core is connected to a plurality of processing cores.

[0023] A first control core among the plurality of control cores reads a first instruction;

[0024] When the first control core determines that the first instruction is a control instruction executed by the control core, executing the first instruction;

[0025] When the first control core determines that the first instruction is a data processing instruction executed by a processing core, the first control core sends the first instruction to a first processing core among the multiple processing cores, and the first processing core executes the first instruction.

[0026] Exemplarily, the first control core obtains the first instruction corresponding to the first control core from the instruction cache unit. The first control core is any one of the multiple control cores, and the first processing core is one or more of the multiple processing cores that need to execute the first instruction. The first control core and the first processing core are only used to illustrate the task scheduling process between the control core and the processing core in the embodiment of the present application, and are not used to limit a specific control core or a specific processing core. In other words, any control core can be regarded as the first control core, and any processing core can be regarded as the first processing core.

[0027] In some embodiments, the first control core sequentially fetches instructions from the instruction cache unit according to a preset instruction fetching order, sequentially decodes and sequentially sends instructions. In this way, a simple sequential instruction fetching method is used to process instructions in parallel, and the software development difficulty of the multi-core processing system provided by the embodiment of the present application is very low and easy to implement.

[0028] In other embodiments, the instructions may not need to be executed in the order specified by the program. For example, the instructions may be sent out of order and executed out of order.

[0029] Specifically, after reading the first instruction, the first control core decodes the first instruction and determines that the first instruction is a control instruction executed by the control core according to the decoding result, or determines that the first instruction is a data processing instruction executed by the processing core according to the decoding result. In other words, the first control core is used to fetch instructions, decode instructions, and execute control instructions.

[0030] Exemplarily, multiple control cores may use microprocessors without internal interlocked pipeline stages (Microprocessorwithout interlocked piped stages, MIPIS), fifth-generation reduced instruction set processors (Microprocessorwithout interlocked piped stages, RISC-V) and other small cores that are easy to expand. Among them, RISC-V is an open instruction set architecture (Instruction Set Architecture, ISA) based on the principle of Reduced Instruction Set Computer (RISC), and V represents the fifth generation RISC.

[0031] In some embodiments, each processing core includes at least one processing unit for executing data processing instructions. When the processing core includes more than two processing units, at least two instructions can be processed in parallel.

[0032] In some embodiments, the processing core determines the idle information of the processing core according to the idle state of the at least one processing unit; the first control core obtains the idle information of the multiple processing cores, and determines the first processing core according to the idle information of the multiple processing cores. Exemplarily, the idle information of the processing core may include whether the processing unit is in an idle state or a non-idle state. Furthermore, the idle degree of the processing core may be determined according to the number of processing units in an idle state in the idle information of the processing core, and the processing core with the highest idle degree (i.e., the processing core with the largest number of processing units in an idle state) is selected as the first processing core. When multiple processing cores with the same idle degree are stored, one is arbitrarily selected as the first processing core, or one is selected as the first processing core according to a preset selection order or priority.

[0033] In some embodiments, the first control core obtains the idle information and priorities of the multiple processing cores; the first control core determines the first processing core according to the idle information and priorities of the multiple processing cores. Exemplarily, the search starts from a high priority, and the processing core with a processing unit in an idle state is determined as the first processing core.

[0034] In some embodiments, when the first control core determines that the plurality of processing cores have no idle processing units based on the idle information of the plurality of processing cores, the first control core stops sending the first instruction. When the first control core determines that the plurality of processing cores have idle processing units based on the idle information of the plurality of processing cores, the first control core sends the first instruction to the first processing core having the idle processing unit.

[0035] In some embodiments, the first processing core receives the first instruction and sends the first instruction to the first processing unit for execution according to the instruction type of the first instruction and the idle state of the processing unit.

[0036] Specifically, when the processing instructions of the processing units are of the same type, the first processing core may send the first instruction to the first processing unit in an idle state according to a preset sending order.

[0037] When the processing instruction types of the processing units are not exactly the same, the first processing core receives the first instruction and determines the instruction type of the first instruction; the first processing core determines the first processing unit that executes the first instruction based on the mapping relationship between the processing unit and the instruction type, according to the instruction type of the first instruction and the idle state of the processing unit.

[0038] Exemplarily, the processing unit may be a vector processing unit, a scalar processing unit, a Fourier transform processing unit, a filter processing unit, or an accelerated processing unit based on a fixed hardware algorithm. Accordingly, the vector processing unit processes vector data, the scalar processing unit processes scalar data, the Fourier transform processing unit performs Fourier transform on data, the filter processing unit performs filtering on data, and the accelerated processing unit is used to accelerate data processing of a specific algorithm.

[0039] Exemplarily, in some embodiments, the multi-core processing system also includes a data synchronization network, and when the first processing core executes the first instruction, it determines to perform a first operation on the register of the first control core, and synchronizes the first operation data of the register of the first control core through the data synchronization network; wherein, when the first operation is a read operation, the first operation data is read data; when the first operation is a write operation, the first operation data is write data.

[0040] Exemplarily, in some embodiments, after the first processing core synchronizes the first operation data of the register of the first control core through the data synchronization network, the first control core reads the second instruction; if the first processing core does not synchronize the first operation data of the register of the first control core through the data synchronization network, the first control core stops reading the second instruction; wherein, when the second instruction is executed, a second operation is performed on the register of the first control core, and the first operation and the second operation are data-related operations. Exemplarily, the first operation is a register write operation, and the second operation is a register read operation; or, the first operation is a register read operation, and the second operation is a register write operation; or, the first operation is a register write operation, and the second operation is a register write operation.

[0041] Here, the use of general registers inside the control core is synchronized through the data synchronization network. Since instructions may be blocked when sent from the control core to the processing core and then from the processing core to each processing unit, the operation time of the processing core on the general registers inside the control core is uncertain. Through the design of the data synchronization network, if there is a data correlation conflict between the control core and any processing unit, the control core will stop fetching instructions to achieve the function of data synchronization. Here, data correlation conflicts include: read-after-write correlation, write-after-read correlation, and write-after-write correlation.

[0042] Exemplarily, in some embodiments, the multi-core processing system further includes a control synchronization network.

[0043] After the first control core reads all instructions in the current instruction set, the first control core sends a wait request to a second processing core among the multiple processing cores through the control synchronization network, and stops reading instructions in the next instruction set; wherein the second processing core is part or all of the processing cores among the multiple processing cores;

[0044] The second processing core determines, in response to the wait request, that the second processing core has finished executing the instructions in the current instruction set received, and generates an end response; and sends the end response to the first control core through the control synchronization network;

[0045] The first control core determines that the execution of all instructions in the current instruction set has ended according to the received end response, and starts to read instructions in the next instruction set.

[0046] That is to say, in order to achieve control synchronization, in the embodiment of the present application, after the first control core reads all instructions in the current instruction set, it sends a wait request, and the first control core stops fetching instructions and decoding. Until all second processing cores have executed the instruction programs that must be executed and returned an end response, the first control core can determine whether the current instruction set has been executed, and continue to read the next instruction set after the execution is completed to avoid related data conflicts. Here, the second processing core can refer to the first processing core that receives the first instruction, or it can refer to each processing core.

[0047] Figure 2 Schematic diagram of the second component structure of the system in the embodiment of the present application. Figure 2 As shown, the system 20 includes: multiple control cores 201 and multiple processing cores 202. The multiple control cores 201 are connected to the multiple processing cores 202 through a control synchronization network 203 and a data synchronization network 204 respectively. Each processing core includes at least two processing units for realizing parallel processing of at least two instructions.

[0048] Specifically, the multiple control cores 201 include control core 1, control core 2, ..., control core N, and the multiple processing cores 102 include processing core 1, processing core 2, ..., processing core M, where N and M are integers greater than or equal to 2. Each processing core includes at least one processing unit, for example, processing core 1 includes processing unit 1, processing unit 2, ..., processing unit j, and the multiple control cores 101 and the multiple processing cores 102 are connected via a control synchronization network 203 and a data synchronization network 204.

[0049] like Figure 2 As shown, the control synchronization network 203 includes at least N control core terminals and M groups of processing core terminals, the N control core terminals are respectively connected to the N control cores, the M groups of processing core terminals are respectively connected to the M processing cores, each group of processing core terminals includes N processing core terminals, and the N processing core terminals respectively form N instruction paths with the N control core terminals. In other words, each control core and processing core transmit instructions through an independent instruction path. For example, the instruction path transmits the first instruction, the wait request, and the end response, etc.

[0050] When the first control core reads all instructions in the current instruction set, it generates a wait request. The wait request may include a control core identifier. When the system includes N control cores and M processing cores, WAIT_m indicates that the control core initiates a wait request. The control core stops fetching instructions and decoding until the corresponding processing core completes the processing instructions that must be executed, and returns DONE_n to provide the control core with corresponding identification information. Furthermore, the wait request also includes the control core identifier. For example, WAIT_m_n indicates a wait request sent by control core n to processing core m. The end response also includes a processing core identifier. For example, DONE_n_m indicates an end response sent by processing core m to control core n. Wherein, n is an integer from 1 to N, and m is an integer from 1 to M.

[0051] The data synchronization network 204 also includes N control core terminals and M groups of processing core terminals. The N control core terminals are connected to the N control cores respectively, and the M groups of processing core terminals are connected to the M processing cores respectively. Each group of processing core terminals includes N processing core terminals, and the N processing core terminals form N data paths with the N control core terminals respectively. In other words, each control core and processing core synchronize register data through an independent data path.

[0052] In some embodiments, the control synchronization network and the data synchronization network may also be the same synchronization network, that is, the control core and the processing core are connected via a synchronization network, and instruction synchronization and data synchronization are achieved through transmission control.

[0053] The functions of each part are as follows:

[0054] 1. Multiple control cores 201: MIPS, RISC-V and other small cores that are easy to expand can be used. They are used to fetch instructions and decode them for the first time. If the instructions are control instructions, they are executed in the control core. If they are task processing instructions, the instructions can be sent to the corresponding processing core according to the instruction information.

[0055] Alternatively, instructions may be sent to appropriate processing cores according to the idleness of each processing core and a specific priority mechanism. If all processing cores have no idle processing units to receive redundant instructions, instruction fetching is stopped and the idle processing units are waited for.

[0056] 2. Multiple processing cores 202: receive instructions sent by each control core, perform a second decoding to check the idle status of each processing unit, check the data correlation between the received instructions, and send executable instructions to each processing unit for calculation.

[0057] 3. Data synchronization network 204: Data synchronization is performed on the use of general registers inside the control core through the data synchronization network. Since there may be a blockage when sending from the control core to the processing core and then from the processing core to each processing unit, the operation time of the processing core on the general registers inside the control core is uncertain. Through the design of the data synchronization network, if there is a data correlation conflict between the control core and any processing unit (including write-after-read correlation, read-after-write correlation, and write-after-write correlation), the control core will stop fetching instructions to achieve the function of data synchronization.

[0058] 4. Control synchronization network 203: Customized instructions WAIT_m and DONE_n are used to implement different processing cores and different processing units from the perspective of execution to synchronize instructions with the control core. When the control core initiates a WAIT_m request, the control core stops fetching instructions and decoding. Until the corresponding processing core completes the program that must be executed and executes DONE_n, the corresponding identification information is provided to the control core. When the control core detects that the processing core has completed the task, it continues to fetch instructions and execute subsequent programs. Among them, n is an integer from 1 to N, and m is an integer from 1 to M.

[0059] By using the above multi-core processing system, a one-to-many topology is configured between the control core and the processing core according to the processing requirements, that is, one control core can send processing instructions to multiple processing cores for parallel processing, thereby improving the parallelism of data processing instructions and thus improving data processing efficiency. In particular, the speed of processing complex tasks can be improved, such as designing the processing unit as a vector processing unit for use in communication chips, which can speed up the processing of large amounts of parallel data; and designing the processing unit as an acceleration module for a fixed hardware algorithm can reduce the execution time of a specific algorithm.

[0060] Based on the multi-core processing system provided in the embodiment of the present application, the embodiment of the present application also provides a task scheduling method for the multi-core processing system. The multi-core processing system is any multi-core processing system in the embodiment of the present application, Figure 3 FIG. 1 is a flow chart of a task scheduling method for a multi-core processing system in an embodiment of the present application. Figure 3 As shown, the method may specifically include:

[0061] Step 301: reading a first instruction through a first control core among a plurality of control cores;

[0062] Exemplarily, the first control core sequentially fetches instructions from the instruction cache unit according to a preset instruction fetching order, sequentially decodes and sequentially sends instructions. In this way, a simple sequential instruction fetching method is used to process instructions in parallel, and the software development difficulty of the multi-core processing system provided by the embodiment of the present application is very low and easy to implement.

[0063] In other embodiments, the instructions may not need to be executed in the order specified by the program. For example, the instructions may be sent out of order and executed out of order.

[0064] Step 302: When the first control core determines that the first instruction is a control instruction executed by the control core, execute the first instruction;

[0065] Specifically, after reading the first instruction, the first control core decodes the first instruction and determines that the first instruction is a control instruction executed by the control core according to the decoding result, or determines that the first instruction is a data processing instruction executed by the processing core according to the decoding result. In other words, the first control core is used to fetch instructions, decode instructions, and execute control instructions.

[0066] Multiple control cores can use small cores that are easy to expand, such as microprocessors without interlocked piped stages (MIPIS) and fifth-generation reduced instruction set processors (RISC-V). Among them, RISC-V is an open instruction set architecture (ISA) based on the principle of reduced instruction set computing (RISC), and V represents the fifth-generation RISC.

[0067] Step 303: When the first control core determines that the first instruction is a data processing instruction to be executed by a processing core, the first control core sends the first instruction to a first processing core among the multiple processing cores, and the first processing core executes the first instruction.

[0068] In some embodiments, each processing core includes at least one processing unit for executing data processing instructions. When the processing core includes more than two processing units, at least two instructions can be processed in parallel.

[0069] In some embodiments, the method further includes: the processing core determines the idle information of the processing core according to the idle state of the at least one processing unit; the first control core obtains the idle information of the multiple processing cores, and determines the first processing core according to the idle information of the multiple processing cores. Exemplarily, the idle information of the processing core may include whether the processing unit is in an idle state or a non-idle state. Further, the idle degree of the processing core can be determined according to the number of processing units in an idle state in the idle information of the processing core, and the processing core with the highest idle degree (i.e., the processing core with the largest number of processing units in an idle state) is selected as the first processing core. When multiple processing cores with the same idle degree are stored, one is arbitrarily selected as the first processing core, or one is selected as the first processing core according to a preset selection order or priority.

[0070] In some embodiments, the first control core obtains the idle information and priorities of the multiple processing cores; the first control core determines the first processing core according to the idle information and priorities of the multiple processing cores. Exemplarily, the search starts from a high priority, and the processing core with a processing unit in an idle state is determined as the first processing core.

[0071] In some embodiments, when the first control core determines that the plurality of processing cores have no idle processing units based on the idle information of the plurality of processing cores, the first control core stops sending the first instruction. When the first control core determines that the plurality of processing cores have idle processing units based on the idle information of the plurality of processing cores, the first control core sends the first instruction to the first processing core having the idle processing unit.

[0072] In some embodiments, the first processing core receives the first instruction and sends the first instruction to the first processing unit for execution according to the instruction type of the first instruction and the idle state of the processing unit.

[0073] Specifically, when the processing instructions of the processing units are of the same type, the first processing core may send the first instruction to the first processing unit in an idle state according to a preset sending order.

[0074] When the processing instruction types of the processing units are not exactly the same, the first processing core receives the first instruction and determines the instruction type of the first instruction; the first processing core determines the first processing unit that executes the first instruction based on the mapping relationship between the processing unit and the instruction type, according to the instruction type of the first instruction and the idle state of the processing unit.

[0075] Exemplarily, the processing unit may be a vector processing unit, a scalar processing unit, a Fourier transform processing unit, a filter processing unit, or an accelerated processing unit based on a fixed hardware algorithm. Accordingly, the vector processing unit processes vector data, the scalar processing unit processes scalar data, the Fourier transform processing unit performs Fourier transform on data, the filter processing unit performs filtering on data, and the accelerated processing unit is used to accelerate data processing of a specific algorithm.

[0076] Exemplarily, in some embodiments, the multi-core processing system also includes a data synchronization network, and the method also includes: when the first processing core executes the first instruction, determining to perform a first operation on a register of the first control core, and synchronizing first operation data of the register of the first control core through the data synchronization network; wherein, when the first operation is a read operation, the first operation data is read data; when the first operation is a write operation, the first operation data is write data.

[0077] Exemplarily, in some embodiments, the method further includes: after the first processing core synchronizes the first operation data of the register of the first control core through the data synchronization network, the first control core reads the second instruction; if the first processing core fails to synchronize the first operation data of the register of the first control core through the data synchronization network, the first control core stops reading the second instruction; wherein, when the second instruction is executed, a second operation is performed on the register of the first control core, and the first operation and the second operation are data-related operations.

[0078] Exemplarily, the first operation is a register write operation, and the second operation is a register read operation; or, the first operation is a register read operation, and the second operation is a register write operation; or, the first operation is a register write operation, and the second operation is a register write operation.

[0079] Here, the use of general registers inside the control core is synchronized through the data synchronization network. Since instructions may be blocked when sent from the control core to the processing core and then from the processing core to each processing unit, the operation time of the processing core on the general registers inside the control core is uncertain. Through the design of the data synchronization network, if there is a data correlation conflict between the control core and any processing unit, the control core will stop fetching instructions to achieve the function of data synchronization. Here, data correlation conflicts include: read-after-write correlation, write-after-read correlation, and write-after-write correlation.

[0080] Exemplarily, in some embodiments, the multi-core processing system further includes a control synchronization network, and the method further includes: after the first control core reads all instructions in the current instruction set, the first control core sends a wait request to a second processing core among the multiple processing cores through the control synchronization network, and stops reading instructions in the next instruction set; wherein the second processing core is part or all of the processing cores among the multiple processing cores;

[0081] The second processing core determines, in response to the wait request, that the second processing core has finished executing the instructions in the current instruction set received, and generates an end response; and sends the end response to the first control core through the control synchronization network;

[0082] The first control core determines that the execution of all instructions in the current instruction set has ended according to the received end response, and starts to read instructions in the next instruction set.

[0083] That is to say, in order to achieve control synchronization, in the embodiment of the present application, after the first control core reads all instructions in the current instruction set, it sends a wait request, and the first control core stops fetching instructions and decoding. Until all second processing cores have executed the instruction programs that must be executed and returned an end response, the first control core can determine whether the current instruction set has been executed, and continue to read the next instruction set after the execution is completed to avoid related data conflicts. Here, the second processing core can refer to the first processing core that receives the first instruction, or it can refer to each processing core.

[0084] Here, the wait request can include the control core identifier, Figure 2For example, when the system includes N control cores and M processing cores, WAIT_m indicates that the control core initiates a wait request, and the control core stops fetching instructions and decoding until the corresponding processing core executes the processing instructions that must be executed, and returns DONE_n to provide the control core with corresponding identification information. Furthermore, the wait request also includes the control core identification, for example, WAIT_m_n indicates a wait request sent by the control core n to the processing core m. The end response also includes the processing core identification, for example, DONE_n_m indicates an end response sent by the processing core m to the control core n. Wherein, n is an integer from 1 to N, and m is an integer from 1 to M.

[0085] It should be noted that the first control core obtains the first instruction corresponding to the first control core from the instruction cache unit. The first control core is any one of the multiple control cores, and the first processing core is one or more of the multiple processing cores that need to execute the first instruction. The first control core and the first processing core are only used to illustrate the task scheduling process between the control core and the processing core in the embodiment of the present application, and are not used to limit a specific control core or a specific processing core. In other words, any control core can be regarded as the first control core, and any processing core can be regarded as the first processing core. The task scheduling method of the multi-core processing system implemented by the interaction of the first control core and multiple processing cores in the embodiment of the present application can be understood as the task scheduling method of the multi-core processing system implemented by the interaction of any control core and multiple processing cores.

[0086] By using the task scheduling method of the multi-core processing system, a one-to-many topology is configured between the control core and the processing core according to the processing requirements, that is, one control core can send processing instructions to multiple processing cores for parallel processing, thereby improving the parallelism of data processing instruction processing and thus improving data processing efficiency. In particular, for the speed of processing complex tasks, such as designing the processing unit as a vector processing unit for use in communication chips, it can speed up the processing of large amounts of parallel data; and for example, designing the processing unit as an acceleration module for a fixed hardware algorithm can reduce the execution time of a specific algorithm.

[0087] The embodiment of the present application also provides a chip, Figure 4 4 is a schematic diagram of the composition structure of the chip of the embodiment of the present application. The chip 40 includes: a multi-core processing system 401, the multi-core processing system includes multiple control cores and multiple processing cores, and the multi-core processing system is any multi-core processing system provided in the embodiment of the present application, which is used to call and run a computer program from a memory, so that an electronic device equipped with the chip is used to execute the steps of the task scheduling method of the multi-core processing system in the embodiment of the present application.

[0088] Alternatively, if Figure 4As shown, the chip 40 may further include a memory 402. The multi-core processing system 401 may call and run a computer program from the memory 402 to implement the method in the embodiment of the present application.

[0089] The memory 402 may be a separate device independent of the multi-core processing system 401 , or may be integrated into the multi-core processing system 401 .

[0090] Optionally, the chip 40 may further include an input interface 403. The multi-core processing system 401 may control the input interface 403 to communicate with other devices or chips, and specifically, may obtain information or data sent by other devices or chips.

[0091] Optionally, the chip 40 may further include an output interface 404. The multi-core processing system 401 may control the output interface 404 to communicate with other devices or chips, and specifically, may output information or data to other devices or chips.

[0092] Optionally, the various components in the chip are coupled together via a bus system.

[0093] Optionally, the chip can be applied to electronic devices, and the chip can implement the corresponding processes of the various methods implemented in the embodiments of the present application, which will not be described in detail here for the sake of brevity.

[0094] It should be understood that the chip mentioned in the embodiments of the present application can also be called a system-level chip, a system chip, a chip system or a system-on-chip chip, etc.

[0095] In practical applications, the multi-core processing system can be a heterogeneous multi-core processing system or a homogeneous multi-core processing system. From a hardware perspective, multi-core designs are divided into two categories. If all cores or CPUs have the same architecture, it is defined as homogeneous multi-core; if the architecture is different, it is called heterogeneous multi-core. From the application point of view, most homogeneous multi-core processing systems are composed of general-purpose processor cores, and each core can run independently, similar to a single-core processor. Heterogeneous multi-core processing systems often inherit general-purpose processors, digital signal processors (DSP), field-programmable gate arrays (FPGA), media processors, network processors, etc. Each core is set for different requirements, thereby improving the computing performance or real-time performance of the application.

[0096] The above-mentioned memory can be a volatile memory (volatile memory), such as a random access memory (RAM); or a non-volatile memory (non-volatile memory), such as a read-only memory (ROM), a flash memory, a hard disk (HDD) or a solid-state drive (SSD); or a combination of the above-mentioned types of memory, and provide instructions and data to the processor.

[0097] In an exemplary embodiment, the present application also provides an electronic device, which includes the above chip.

[0098] In an exemplary embodiment, the present application also provides a computer-readable storage medium, such as a memory including a computer program, which can be executed by a processor to complete the steps of the aforementioned method. Here, the processor can be understood as a multi-core processor including a multi-core processing system.

[0099] An embodiment of the present application also provides a computer program product, including computer program instructions.

[0100] Optionally, the computer program product can be applied to the processor in the embodiments of the present application, and the computer program instructions enable the computer to execute the corresponding processes implemented by the processor in the various methods of the embodiments of the present application. For the sake of brevity, they are not repeated here.

[0101] The embodiment of the present application also provides a computer program.

[0102] Optionally, the computer program can be applied to the processor in the embodiments of the present application. When the computer program runs on a computer, the computer executes the corresponding processes implemented by the processor in the various methods in the embodiments of the present application. For the sake of brevity, they are not described here.

[0103] It should be understood that the terms used in the present application are only for the purpose of describing specific embodiments, but are not intended to limit the present application. The singular forms of "a", "said" and "the" used in the present application and the appended claims are also intended to include plural forms, unless the context clearly indicates other meanings. It should also be understood that the term "and / or" used in this article refers to and includes any or all possible combinations of one or more associated listed items. The expressions "having", "may have", "include" and "include", or "may include" and "may include" in this application can be used to indicate the presence of corresponding features (e.g., elements such as numerical values, functions, operations or components), but the presence of additional features is not excluded.

[0104] It should be understood that although the terms first, second, third, etc. may be used in this application to describe various information, such information should not be limited to these terms. These terms are only used to distinguish the same type of information from each other and are not necessarily used to describe a specific order or sequence. For example, without departing from the scope of the present invention, the first information may also be referred to as the second information, and similarly, the second information may also be referred to as the first information.

[0105] The technical solutions described in the embodiments of the present application can be combined arbitrarily without conflict.

[0106] In the several embodiments provided in the present application, it should be understood that the disclosed methods, devices and equipment can be implemented in other ways. The embodiments described above are only schematic. For example, the division of units is only a logical function division. There may be other division methods in actual implementation, such as: multiple units or components can be combined, or can be integrated into another system, or some features can be ignored or not executed. In addition, the coupling, direct coupling, or communication connection between the components shown or discussed can be through some interfaces, and the indirect coupling or communication connection of devices or units can be electrical, mechanical or other forms.

[0107] The units described above as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units; some or all of the units may be selected according to actual needs to achieve the purpose of the present embodiment.

[0108] In addition, all functional units in the embodiments of the present application may be integrated into one processing unit, or each unit may be a separate unit, or two or more units may be integrated into one unit; the above-mentioned integrated units may be implemented in the form of hardware or in the form of hardware plus software functional units.

[0109] The above description is only a specific implementation manner of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application.

Claims

1. A multi-core processing system, characterized in that: The multi-core processing system includes multiple control cores and multiple processing cores. A first control core among the plurality of control cores reads a first instruction; When the first control core determines that the first instruction is a control instruction executed by the control core, executing the first instruction; When the first control core determines that the first instruction is a data processing instruction executed by a processing core, the first control core sends the first instruction to a first processing core among the plurality of processing cores, and the first processing core executes the first instruction; Wherein, each processing core includes at least two processing units for implementing parallel processing of at least two instructions; The multi-core processing system also includes a data synchronization network and a control synchronization network, and the multiple control cores and the multiple processing cores are connected through the data synchronization network and the control synchronization network; the data synchronization network is used to synchronize data of the general registers inside the control core, and the control synchronization network is used to perform control synchronization and transmit the first instruction.

2. The multi-core processing system according to claim 1, characterized in that: When the first processing core executes the first instruction, determining to perform a first operation on a register of the first control core, and synchronizing first operation data of the register of the first control core through the data synchronization network; When the first operation is a read operation, the first operation data is read data; when the first operation is a write operation, the first operation data is write data.

3. The multi-core processing system according to claim 2, characterized in that: After the first processing core synchronizes the first operation data of the register of the first control core through the data synchronization network, the first control core reads the second instruction; The first processing core fails to synchronize the first operation data of the register of the first control core through the data synchronization network, and the first control core stops reading the second instruction; When the second instruction is executed, a second operation is performed on a register of the first control core, and the first operation and the second operation are data-related operations.

4. The multi-core processing system according to claim 1, characterized in that: After the first control core reads all instructions in the current instruction set, the first control core sends a wait request to a second processing core among the multiple processing cores through the control synchronization network, and stops reading instructions in the next instruction set; wherein the second processing core is part or all of the multiple processing cores; The second processing core determines, in response to the wait request, that the second processing core has finished executing the instructions in the current instruction set received, and generates an end response; and sends the end response to the first control core through the control synchronization network; The first control core determines that the execution of all instructions in the current instruction set has ended according to the received end response, and starts to read instructions in the next instruction set.

5. The multi-core processing system according to claim 1, characterized in that: The processing core determines idle information of the processing core according to idle states of the at least two processing units; The first control core obtains idle information of the multiple processing cores, and determines the first processing core according to the idle information of the multiple processing cores.

6. The multi-core processing system according to claim 5, characterized in that: When the first control core determines, based on the idle information of the multiple processing cores, that there is no idle processing unit in the multiple processing cores, the first control core stops sending the first instruction.

7. The multi-core processing system according to claim 1, characterized in that: The first processing core receives the first instruction, and sends the first instruction to the first processing unit for execution according to the instruction type of the first instruction and the idle state of the processing unit.

8. A chip, characterized in that: The chip comprises the multi-core processing system according to any one of claims 1 to 7.

9. A task scheduling method for a multi-core processing system, characterized in that: The multi-core processing system includes multiple control cores and multiple processing cores, and the method includes: Reading a first instruction through a first control core among the plurality of control cores; When the first control core determines that the first instruction is a control instruction executed by the control core, executing the first instruction; When the first control core determines that the first instruction is a data processing instruction executed by a processing core, the first instruction is sent to a first processing core among the plurality of processing cores, and the first processing core executes the first instruction; Wherein, each processing core includes at least two processing units for implementing parallel processing of at least two instructions; The multi-core processing system also includes a data synchronization network and a control synchronization network, and the multiple control cores and the multiple processing cores are connected through the data synchronization network and the control synchronization network; the data synchronization network is used to synchronize data of the general registers inside the control core, and the control synchronization network is used to perform control synchronization and transmit the first instruction.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to claim 9 are implemented.

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